drivers/gpu/drm/arm/hdlcd_drv.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  *  ARM HDLCD Controller register definition
   4  */
   5
   6 #ifndef __HDLCD_DRV_H__
   7 #define __HDLCD_DRV_H__
   8
   9 struct hdlcd_drm_private {
  10         void __iomem                    *mmio;
  11         struct clk                      *clk;
  12         struct drm_crtc                 crtc;
  13         struct drm_plane                *plane;
  14 #ifdef CONFIG_DEBUG_FS
  15         atomic_t buffer_underrun_count;
  16         atomic_t bus_error_count;
  17         atomic_t vsync_count;
  18         atomic_t dma_end_count;
  19 #endif
  20 };
  21
  22 #define crtc_to_hdlcd_priv(x)   container_of(x, struct hdlcd_drm_private, crtc)
  23
  24 static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd,
  25                                unsigned int reg, u32 value)
  26 {
  27         writel(value, hdlcd->mmio + reg);
  28 }
  29
  30 static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg)
  31 {
  32         return readl(hdlcd->mmio + reg);
  33 }
  34
  35 int hdlcd_setup_crtc(struct drm_device *dev);
  36 void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
  37
  38 #endif /* __HDLCD_DRV_H__ */