drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

   1 /*
   2 * Analogix DP (Display Port) core interface driver.
   3 *
   4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5 * Author: Jingoo Han <jg1.han@samsung.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms of the GNU General Public License as published by the
   9 * Free Software Foundation; either version 2 of the License, or (at your
  10 * option) any later version.
  11 */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/of.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/gpio.h>
  23 #include <linux/component.h>
  24 #include <linux/phy/phy.h>
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_panel.h>
  31
  32 #include <drm/bridge/analogix_dp.h>
  33
  34 #include "analogix_dp_core.h"
  35 #include "analogix_dp_reg.h"
  36
  37 #define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
  38
  39 static const bool verify_fast_training;
  40
  41 struct bridge_init {
  42         struct i2c_client *client;
  43         struct device_node *node;
  44 };
  45
  46 static int analogix_dp_init_dp(struct analogix_dp_device *dp)
  47 {
  48         int ret;
  49
  50         analogix_dp_reset(dp);
  51
  52         analogix_dp_swreset(dp);
  53
  54         analogix_dp_init_analog_param(dp);
  55         analogix_dp_init_interrupt(dp);
  56
  57         /* SW defined function Normal operation */
  58         analogix_dp_enable_sw_function(dp);
  59
  60         analogix_dp_config_interrupt(dp);
  61         ret = analogix_dp_init_analog_func(dp);
  62         if (ret)
  63                 return ret;
  64
  65         analogix_dp_init_hpd(dp);
  66         analogix_dp_init_aux(dp);
  67         return 0;
  68 }
  69
  70 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  71 {
  72         int timeout_loop = 0;
  73
  74         while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  75                 if (analogix_dp_get_plug_in_status(dp) == 0)
  76                         return 0;
  77
  78                 timeout_loop++;
  79                 usleep_range(1000, 1100);
  80         }
  81
  82         /*
  83          * Some edp screen do not have hpd signal, so we can't just
  84          * return failed when hpd plug in detect failed, DT property
  85          * "force-hpd" would indicate whether driver need this.
  86          */
  87         if (!dp->force_hpd)
  88                 return -ETIMEDOUT;
  89
  90         /*
  91          * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  92          * will not work, so we need to give a force hpd action to
  93          * set HPD_STATUS manually.
  94          */
  95         dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  96
  97         analogix_dp_force_hpd(dp);
  98
  99         if (analogix_dp_get_plug_in_status(dp) != 0) {
 100                 dev_err(dp->dev, "failed to get hpd plug in status\n");
 101                 return -EINVAL;
 102         }
 103
 104         dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
 105
 106         return 0;
 107 }
 108
 109 int analogix_dp_psr_enabled(struct analogix_dp_device *dp)
 110 {
 111
 112         return dp->psr_enable;
 113 }
 114 EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled);
 115
 116 int analogix_dp_enable_psr(struct analogix_dp_device *dp)
 117 {
 118         struct edp_vsc_psr psr_vsc;
 119
 120         if (!dp->psr_enable)
 121                 return 0;
 122
 123         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 124         memset(&psr_vsc, 0, sizeof(psr_vsc));
 125         psr_vsc.sdp_header.HB0 = 0;
 126         psr_vsc.sdp_header.HB1 = 0x7;
 127         psr_vsc.sdp_header.HB2 = 0x2;
 128         psr_vsc.sdp_header.HB3 = 0x8;
 129
 130         psr_vsc.DB0 = 0;
 131         psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
 132
 133         return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
 134 }
 135 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
 136
 137 int analogix_dp_disable_psr(struct analogix_dp_device *dp)
 138 {
 139         struct edp_vsc_psr psr_vsc;
 140         int ret;
 141
 142         if (!dp->psr_enable)
 143                 return 0;
 144
 145         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 146         memset(&psr_vsc, 0, sizeof(psr_vsc));
 147         psr_vsc.sdp_header.HB0 = 0;
 148         psr_vsc.sdp_header.HB1 = 0x7;
 149         psr_vsc.sdp_header.HB2 = 0x2;
 150         psr_vsc.sdp_header.HB3 = 0x8;
 151
 152         psr_vsc.DB0 = 0;
 153         psr_vsc.DB1 = 0;
 154
 155         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 156         if (ret != 1) {
 157                 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
 158                 return ret;
 159         }
 160
 161         return analogix_dp_send_psr_spd(dp, &psr_vsc, false);
 162 }
 163 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
 164
 165 static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
 166 {
 167         unsigned char psr_version;
 168         int ret;
 169
 170         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
 171         if (ret != 1) {
 172                 dev_err(dp->dev, "failed to get PSR version, disable it\n");
 173                 return ret;
 174         }
 175
 176         dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
 177
 178         dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
 179
 180         return 0;
 181 }
 182
 183 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
 184 {
 185         unsigned char psr_en;
 186         int ret;
 187
 188         /* Disable psr function */
 189         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
 190         if (ret != 1) {
 191                 dev_err(dp->dev, "failed to get psr config\n");
 192                 goto end;
 193         }
 194
 195         psr_en &= ~DP_PSR_ENABLE;
 196         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 197         if (ret != 1) {
 198                 dev_err(dp->dev, "failed to disable panel psr\n");
 199                 goto end;
 200         }
 201
 202         /* Main-Link transmitter remains active during PSR active states */
 203         psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
 204         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 205         if (ret != 1) {
 206                 dev_err(dp->dev, "failed to set panel psr\n");
 207                 goto end;
 208         }
 209
 210         /* Enable psr function */
 211         psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
 212                  DP_PSR_CRC_VERIFICATION;
 213         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 214         if (ret != 1) {
 215                 dev_err(dp->dev, "failed to set panel psr\n");
 216                 goto end;
 217         }
 218
 219         analogix_dp_enable_psr_crc(dp);
 220
 221         return 0;
 222 end:
 223         dev_err(dp->dev, "enable psr fail, force to disable psr\n");
 224         dp->psr_enable = false;
 225
 226         return ret;
 227 }
 228
 229 static int
 230 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 231                                        bool enable)
 232 {
 233         u8 data;
 234         int ret;
 235
 236         ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
 237         if (ret != 1)
 238                 return ret;
 239
 240         if (enable)
 241                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 242                                          DP_LANE_COUNT_ENHANCED_FRAME_EN |
 243                                          DPCD_LANE_COUNT_SET(data));
 244         else
 245                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 246                                          DPCD_LANE_COUNT_SET(data));
 247
 248         return ret < 0 ? ret : 0;
 249 }
 250
 251 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
 252                                                   u8 *enhanced_mode_support)
 253 {
 254         u8 data;
 255         int ret;
 256
 257         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 258         if (ret != 1) {
 259                 *enhanced_mode_support = 0;
 260                 return ret;
 261         }
 262
 263         *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
 264
 265         return 0;
 266 }
 267
 268 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 269 {
 270         u8 data;
 271         int ret;
 272
 273         ret = analogix_dp_is_enhanced_mode_available(dp, &data);
 274         if (ret < 0)
 275                 return ret;
 276
 277         ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 278         if (ret < 0)
 279                 return ret;
 280
 281         analogix_dp_enable_enhanced_mode(dp, data);
 282
 283         return 0;
 284 }
 285
 286 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 287 {
 288         int ret;
 289
 290         analogix_dp_set_training_pattern(dp, DP_NONE);
 291
 292         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 293                                  DP_TRAINING_PATTERN_DISABLE);
 294
 295         return ret < 0 ? ret : 0;
 296 }
 297
 298 static void
 299 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 300                                        int pre_emphasis, int lane)
 301 {
 302         switch (lane) {
 303         case 0:
 304                 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 305                 break;
 306         case 1:
 307                 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 308                 break;
 309
 310         case 2:
 311                 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 312                 break;
 313
 314         case 3:
 315                 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 316                 break;
 317         }
 318 }
 319
 320 static int analogix_dp_link_start(struct analogix_dp_device *dp)
 321 {
 322         u8 buf[4];
 323         int lane, lane_count, pll_tries, retval;
 324
 325         lane_count = dp->link_train.lane_count;
 326
 327         dp->link_train.lt_state = CLOCK_RECOVERY;
 328         dp->link_train.eq_loop = 0;
 329
 330         for (lane = 0; lane < lane_count; lane++)
 331                 dp->link_train.cr_loop[lane] = 0;
 332
 333         /* Set link rate and count as you want to establish*/
 334         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 335         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 336
 337         /* Setup RX configuration */
 338         buf[0] = dp->link_train.link_rate;
 339         buf[1] = dp->link_train.lane_count;
 340         retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
 341         if (retval < 0)
 342                 return retval;
 343         /* set enhanced mode if available */
 344         retval = analogix_dp_set_enhanced_mode(dp);
 345         if (retval < 0) {
 346                 dev_err(dp->dev, "failed to set enhance mode\n");
 347                 return retval;
 348         }
 349
 350         /* Set TX pre-emphasis to minimum */
 351         for (lane = 0; lane < lane_count; lane++)
 352                 analogix_dp_set_lane_lane_pre_emphasis(dp,
 353                         PRE_EMPHASIS_LEVEL_0, lane);
 354
 355         /* Wait for PLL lock */
 356         pll_tries = 0;
 357         while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 358                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 359                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
 360                         return -ETIMEDOUT;
 361                 }
 362
 363                 pll_tries++;
 364                 usleep_range(90, 120);
 365         }
 366
 367         /* Set training pattern 1 */
 368         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 369
 370         /* Set RX training pattern */
 371         retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 372                                     DP_LINK_SCRAMBLING_DISABLE |
 373                                         DP_TRAINING_PATTERN_1);
 374         if (retval < 0)
 375                 return retval;
 376
 377         for (lane = 0; lane < lane_count; lane++)
 378                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 379                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 380
 381         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
 382                                    lane_count);
 383         if (retval < 0)
 384                 return retval;
 385
 386         return 0;
 387 }
 388
 389 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 390 {
 391         int shift = (lane & 1) * 4;
 392         u8 link_value = link_status[lane >> 1];
 393
 394         return (link_value >> shift) & 0xf;
 395 }
 396
 397 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 398 {
 399         int lane;
 400         u8 lane_status;
 401
 402         for (lane = 0; lane < lane_count; lane++) {
 403                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 404                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 405                         return -EINVAL;
 406         }
 407         return 0;
 408 }
 409
 410 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 411                                      int lane_count)
 412 {
 413         int lane;
 414         u8 lane_status;
 415
 416         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 417                 return -EINVAL;
 418
 419         for (lane = 0; lane < lane_count; lane++) {
 420                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 421                 lane_status &= DP_CHANNEL_EQ_BITS;
 422                 if (lane_status != DP_CHANNEL_EQ_BITS)
 423                         return -EINVAL;
 424         }
 425
 426         return 0;
 427 }
 428
 429 static unsigned char
 430 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 431 {
 432         int shift = (lane & 1) * 4;
 433         u8 link_value = adjust_request[lane >> 1];
 434
 435         return (link_value >> shift) & 0x3;
 436 }
 437
 438 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 439                                         u8 adjust_request[2],
 440                                         int lane)
 441 {
 442         int shift = (lane & 1) * 4;
 443         u8 link_value = adjust_request[lane >> 1];
 444
 445         return ((link_value >> shift) & 0xc) >> 2;
 446 }
 447
 448 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 449                                                u8 training_lane_set, int lane)
 450 {
 451         switch (lane) {
 452         case 0:
 453                 analogix_dp_set_lane0_link_training(dp, training_lane_set);
 454                 break;
 455         case 1:
 456                 analogix_dp_set_lane1_link_training(dp, training_lane_set);
 457                 break;
 458
 459         case 2:
 460                 analogix_dp_set_lane2_link_training(dp, training_lane_set);
 461                 break;
 462
 463         case 3:
 464                 analogix_dp_set_lane3_link_training(dp, training_lane_set);
 465                 break;
 466         }
 467 }
 468
 469 static unsigned int
 470 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
 471                                    int lane)
 472 {
 473         u32 reg;
 474
 475         switch (lane) {
 476         case 0:
 477                 reg = analogix_dp_get_lane0_link_training(dp);
 478                 break;
 479         case 1:
 480                 reg = analogix_dp_get_lane1_link_training(dp);
 481                 break;
 482         case 2:
 483                 reg = analogix_dp_get_lane2_link_training(dp);
 484                 break;
 485         case 3:
 486                 reg = analogix_dp_get_lane3_link_training(dp);
 487                 break;
 488         default:
 489                 WARN_ON(1);
 490                 return 0;
 491         }
 492
 493         return reg;
 494 }
 495
 496 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 497 {
 498         analogix_dp_training_pattern_dis(dp);
 499         analogix_dp_set_enhanced_mode(dp);
 500
 501         dp->link_train.lt_state = FAILED;
 502 }
 503
 504 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 505                                                  u8 adjust_request[2])
 506 {
 507         int lane, lane_count;
 508         u8 voltage_swing, pre_emphasis, training_lane;
 509
 510         lane_count = dp->link_train.lane_count;
 511         for (lane = 0; lane < lane_count; lane++) {
 512                 voltage_swing = analogix_dp_get_adjust_request_voltage(
 513                                                 adjust_request, lane);
 514                 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 515                                                 adjust_request, lane);
 516                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 517                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 518
 519                 if (voltage_swing == VOLTAGE_LEVEL_3)
 520                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 521                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 522                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 523
 524                 dp->link_train.training_lane[lane] = training_lane;
 525         }
 526 }
 527
 528 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 529 {
 530         int lane, lane_count, retval;
 531         u8 voltage_swing, pre_emphasis, training_lane;
 532         u8 link_status[2], adjust_request[2];
 533
 534         usleep_range(100, 101);
 535
 536         lane_count = dp->link_train.lane_count;
 537
 538         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 539         if (retval < 0)
 540                 return retval;
 541
 542         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 543                                   adjust_request, 2);
 544         if (retval < 0)
 545                 return retval;
 546
 547         if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 548                 /* set training pattern 2 for EQ */
 549                 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 550
 551                 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 552                                             DP_LINK_SCRAMBLING_DISABLE |
 553                                                 DP_TRAINING_PATTERN_2);
 554                 if (retval < 0)
 555                         return retval;
 556
 557                 dev_info(dp->dev, "Link Training Clock Recovery success\n");
 558                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 559         } else {
 560                 for (lane = 0; lane < lane_count; lane++) {
 561                         training_lane = analogix_dp_get_lane_link_training(
 562                                                         dp, lane);
 563                         voltage_swing = analogix_dp_get_adjust_request_voltage(
 564                                                         adjust_request, lane);
 565                         pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 566                                                         adjust_request, lane);
 567
 568                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 569                                         voltage_swing &&
 570                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
 571                                         pre_emphasis)
 572                                 dp->link_train.cr_loop[lane]++;
 573
 574                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 575                             voltage_swing == VOLTAGE_LEVEL_3 ||
 576                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 577                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 578                                         dp->link_train.cr_loop[lane],
 579                                         voltage_swing, pre_emphasis);
 580                                 analogix_dp_reduce_link_rate(dp);
 581                                 return -EIO;
 582                         }
 583                 }
 584         }
 585
 586         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 587
 588         for (lane = 0; lane < lane_count; lane++)
 589                 analogix_dp_set_lane_link_training(dp,
 590                         dp->link_train.training_lane[lane], lane);
 591
 592         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 593                                    dp->link_train.training_lane, lane_count);
 594         if (retval < 0)
 595                 return retval;
 596
 597         return 0;
 598 }
 599
 600 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 601 {
 602         int lane, lane_count, retval;
 603         u32 reg;
 604         u8 link_align, link_status[2], adjust_request[2];
 605
 606         usleep_range(400, 401);
 607
 608         lane_count = dp->link_train.lane_count;
 609
 610         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 611         if (retval < 0)
 612                 return retval;
 613
 614         if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 615                 analogix_dp_reduce_link_rate(dp);
 616                 return -EIO;
 617         }
 618
 619         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 620                                   adjust_request, 2);
 621         if (retval < 0)
 622                 return retval;
 623
 624         retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 625                                    &link_align);
 626         if (retval < 0)
 627                 return retval;
 628
 629         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 630
 631         if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 632                 /* traing pattern Set to Normal */
 633                 retval = analogix_dp_training_pattern_dis(dp);
 634                 if (retval < 0)
 635                         return retval;
 636
 637                 dev_info(dp->dev, "Link Training success!\n");
 638                 analogix_dp_get_link_bandwidth(dp, &reg);
 639                 dp->link_train.link_rate = reg;
 640                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 641                         dp->link_train.link_rate);
 642
 643                 analogix_dp_get_lane_count(dp, &reg);
 644                 dp->link_train.lane_count = reg;
 645                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 646                         dp->link_train.lane_count);
 647
 648                 dp->link_train.lt_state = FINISHED;
 649
 650                 return 0;
 651         }
 652
 653         /* not all locked */
 654         dp->link_train.eq_loop++;
 655
 656         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 657                 dev_err(dp->dev, "EQ Max loop\n");
 658                 analogix_dp_reduce_link_rate(dp);
 659                 return -EIO;
 660         }
 661
 662         for (lane = 0; lane < lane_count; lane++)
 663                 analogix_dp_set_lane_link_training(dp,
 664                         dp->link_train.training_lane[lane], lane);
 665
 666         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 667                                    dp->link_train.training_lane, lane_count);
 668         if (retval < 0)
 669                 return retval;
 670
 671         return 0;
 672 }
 673
 674 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 675                                              u8 *bandwidth)
 676 {
 677         u8 data;
 678
 679         /*
 680          * For DP rev.1.1, Maximum link rate of Main Link lanes
 681          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 682          * For DP rev.1.2, Maximum link rate of Main Link lanes
 683          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 684          */
 685         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
 686         *bandwidth = data;
 687 }
 688
 689 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 690                                               u8 *lane_count)
 691 {
 692         u8 data;
 693
 694         /*
 695          * For DP rev.1.1, Maximum number of Main Link lanes
 696          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 697          */
 698         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 699         *lane_count = DPCD_MAX_LANE_COUNT(data);
 700 }
 701
 702 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
 703                                        u32 max_lanes, u32 max_rate)
 704 {
 705         int retval = 0;
 706         bool training_finished = false;
 707
 708         /*
 709          * MACRO_RST must be applied after the PLL_LOCK to avoid
 710          * the DP inter pair skew issue for at least 10 us
 711          */
 712         analogix_dp_reset_macro(dp);
 713
 714         /* Initialize by reading RX's DPCD */
 715         analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 716         analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 717
 718         if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 719             (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 720             (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 721                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 722                         dp->link_train.link_rate);
 723                 dp->link_train.link_rate = DP_LINK_BW_1_62;
 724         }
 725
 726         if (dp->link_train.lane_count == 0) {
 727                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 728                         dp->link_train.lane_count);
 729                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 730         }
 731
 732         /* Setup TX lane count & rate */
 733         if (dp->link_train.lane_count > max_lanes)
 734                 dp->link_train.lane_count = max_lanes;
 735         if (dp->link_train.link_rate > max_rate)
 736                 dp->link_train.link_rate = max_rate;
 737
 738         /* All DP analog module power up */
 739         analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 740
 741         dp->link_train.lt_state = START;
 742
 743         /* Process here */
 744         while (!retval && !training_finished) {
 745                 switch (dp->link_train.lt_state) {
 746                 case START:
 747                         retval = analogix_dp_link_start(dp);
 748                         if (retval)
 749                                 dev_err(dp->dev, "LT link start failed!\n");
 750                         break;
 751                 case CLOCK_RECOVERY:
 752                         retval = analogix_dp_process_clock_recovery(dp);
 753                         if (retval)
 754                                 dev_err(dp->dev, "LT CR failed!\n");
 755                         break;
 756                 case EQUALIZER_TRAINING:
 757                         retval = analogix_dp_process_equalizer_training(dp);
 758                         if (retval)
 759                                 dev_err(dp->dev, "LT EQ failed!\n");
 760                         break;
 761                 case FINISHED:
 762                         training_finished = 1;
 763                         break;
 764                 case FAILED:
 765                         return -EREMOTEIO;
 766                 }
 767         }
 768         if (retval)
 769                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 770
 771         return retval;
 772 }
 773
 774 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
 775 {
 776         int i, ret;
 777         u8 link_align, link_status[2];
 778         enum pll_status status;
 779
 780         analogix_dp_reset_macro(dp);
 781
 782         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 783         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 784
 785         for (i = 0; i < dp->link_train.lane_count; i++) {
 786                 analogix_dp_set_lane_link_training(dp,
 787                         dp->link_train.training_lane[i], i);
 788         }
 789
 790         ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
 791                                  status != PLL_UNLOCKED, 120,
 792                                  120 * DP_TIMEOUT_LOOP_COUNT);
 793         if (ret) {
 794                 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
 795                 return ret;
 796         }
 797
 798         /* source Set training pattern 1 */
 799         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 800         /* From DP spec, pattern must be on-screen for a minimum 500us */
 801         usleep_range(500, 600);
 802
 803         analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 804         /* From DP spec, pattern must be on-screen for a minimum 500us */
 805         usleep_range(500, 600);
 806
 807         /* TODO: enhanced_mode?*/
 808         analogix_dp_set_training_pattern(dp, DP_NONE);
 809
 810         /*
 811          * Useful for debugging issues with fast link training, disable for more
 812          * speed
 813          */
 814         if (verify_fast_training) {
 815                 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 816                                         &link_align);
 817                 if (ret < 0) {
 818                         DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
 819                                       ret);
 820                         return ret;
 821                 }
 822
 823                 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
 824                                        2);
 825                 if (ret < 0) {
 826                         DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
 827                                       ret);
 828                         return ret;
 829                 }
 830
 831                 if (analogix_dp_clock_recovery_ok(link_status,
 832                                                   dp->link_train.lane_count)) {
 833                         DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
 834                         analogix_dp_reduce_link_rate(dp);
 835                         return -EIO;
 836                 }
 837
 838                 if (analogix_dp_channel_eq_ok(link_status, link_align,
 839                                               dp->link_train.lane_count)) {
 840                         DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
 841                         analogix_dp_reduce_link_rate(dp);
 842                         return -EIO;
 843                 }
 844         }
 845
 846         return 0;
 847 }
 848
 849 static int analogix_dp_train_link(struct analogix_dp_device *dp)
 850 {
 851         if (dp->fast_train_enable)
 852                 return analogix_dp_fast_link_train(dp);
 853
 854         return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
 855                                            dp->video_info.max_link_rate);
 856 }
 857
 858 static int analogix_dp_config_video(struct analogix_dp_device *dp)
 859 {
 860         int timeout_loop = 0;
 861         int done_count = 0;
 862
 863         analogix_dp_config_video_slave_mode(dp);
 864
 865         analogix_dp_set_video_color_format(dp);
 866
 867         if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 868                 dev_err(dp->dev, "PLL is not locked yet.\n");
 869                 return -EINVAL;
 870         }
 871
 872         for (;;) {
 873                 timeout_loop++;
 874                 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 875                         break;
 876                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 877                         dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
 878                         return -ETIMEDOUT;
 879                 }
 880                 usleep_range(1000, 1001);
 881         }
 882
 883         /* Set to use the register calculated M/N video */
 884         analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 885
 886         /* For video bist, Video timing must be generated by register */
 887         analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 888
 889         /* Disable video mute */
 890         analogix_dp_enable_video_mute(dp, 0);
 891
 892         /* Configure video slave mode */
 893         analogix_dp_enable_video_master(dp, 0);
 894
 895         /* Enable video */
 896         analogix_dp_start_video(dp);
 897
 898         timeout_loop = 0;
 899
 900         for (;;) {
 901                 timeout_loop++;
 902                 if (analogix_dp_is_video_stream_on(dp) == 0) {
 903                         done_count++;
 904                         if (done_count > 10)
 905                                 break;
 906                 } else if (done_count) {
 907                         done_count = 0;
 908                 }
 909                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 910                         dev_warn(dp->dev,
 911                                  "Ignoring timeout of video streamclk ok\n");
 912                         break;
 913                 }
 914
 915                 usleep_range(1000, 1001);
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 922                                        bool enable)
 923 {
 924         u8 data;
 925         int ret;
 926
 927         if (enable) {
 928                 analogix_dp_enable_scrambling(dp);
 929
 930                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 931                                         &data);
 932                 if (ret != 1)
 933                         return ret;
 934                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 935                                    (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 936         } else {
 937                 analogix_dp_disable_scrambling(dp);
 938
 939                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 940                                         &data);
 941                 if (ret != 1)
 942                         return ret;
 943                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 944                                    (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 945         }
 946         return ret < 0 ? ret : 0;
 947 }
 948
 949 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 950 {
 951         struct analogix_dp_device *dp = arg;
 952         irqreturn_t ret = IRQ_NONE;
 953         enum dp_irq_type irq_type;
 954
 955         irq_type = analogix_dp_get_irq_type(dp);
 956         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 957                 analogix_dp_mute_hpd_interrupt(dp);
 958                 ret = IRQ_WAKE_THREAD;
 959         }
 960
 961         return ret;
 962 }
 963
 964 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 965 {
 966         struct analogix_dp_device *dp = arg;
 967         enum dp_irq_type irq_type;
 968
 969         irq_type = analogix_dp_get_irq_type(dp);
 970         if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 971             irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 972                 dev_dbg(dp->dev, "Detected cable status changed!\n");
 973                 if (dp->drm_dev)
 974                         drm_helper_hpd_irq_event(dp->drm_dev);
 975         }
 976
 977         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 978                 analogix_dp_clear_hotplug_interrupts(dp);
 979                 analogix_dp_unmute_hpd_interrupt(dp);
 980         }
 981
 982         return IRQ_HANDLED;
 983 }
 984
 985 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
 986 {
 987         int ret;
 988         u8 spread;
 989
 990         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
 991         if (ret != 1) {
 992                 dev_err(dp->dev, "failed to read downspread %d\n", ret);
 993                 return ret;
 994         }
 995         dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
 996         dev_dbg(dp->dev, "fast link training %s\n",
 997                 dp->fast_train_enable ? "supported" : "unsupported");
 998         return 0;
 999 }
1000
1001 static int analogix_dp_commit(struct analogix_dp_device *dp)
1002 {
1003         int ret;
1004
1005         /* Keep the panel disabled while we configure video */
1006         if (dp->plat_data->panel) {
1007                 if (drm_panel_disable(dp->plat_data->panel))
1008                         DRM_ERROR("failed to disable the panel\n");
1009         }
1010
1011         ret = analogix_dp_train_link(dp);
1012         if (ret) {
1013                 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
1014                 return ret;
1015         }
1016
1017         ret = analogix_dp_enable_scramble(dp, 1);
1018         if (ret < 0) {
1019                 dev_err(dp->dev, "can not enable scramble\n");
1020                 return ret;
1021         }
1022
1023         analogix_dp_init_video(dp);
1024         ret = analogix_dp_config_video(dp);
1025         if (ret) {
1026                 dev_err(dp->dev, "unable to config video\n");
1027                 return ret;
1028         }
1029
1030         /* Safe to enable the panel now */
1031         if (dp->plat_data->panel) {
1032                 ret = drm_panel_enable(dp->plat_data->panel);
1033                 if (ret) {
1034                         DRM_ERROR("failed to enable the panel\n");
1035                         return ret;
1036                 }
1037         }
1038
1039         ret = analogix_dp_detect_sink_psr(dp);
1040         if (ret)
1041                 return ret;
1042
1043         /* Check whether panel supports fast training */
1044         ret = analogix_dp_fast_link_train_detection(dp);
1045         if (ret)
1046                 dp->psr_enable = false;
1047
1048         if (dp->psr_enable) {
1049                 ret = analogix_dp_enable_sink_psr(dp);
1050                 if (ret)
1051                         return ret;
1052         }
1053
1054
1055         return ret;
1056 }
1057
1058 /*
1059  * This function is a bit of a catch-all for panel preparation, hopefully
1060  * simplifying the logic of functions that need to prepare/unprepare the panel
1061  * below.
1062  *
1063  * If @prepare is true, this function will prepare the panel. Conversely, if it
1064  * is false, the panel will be unprepared.
1065  *
1066  * If @is_modeset_prepare is true, the function will disregard the current state
1067  * of the panel and either prepare/unprepare the panel based on @prepare. Once
1068  * it finishes, it will update dp->panel_is_modeset to reflect the current state
1069  * of the panel.
1070  */
1071 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1072                                      bool prepare, bool is_modeset_prepare)
1073 {
1074         int ret = 0;
1075
1076         if (!dp->plat_data->panel)
1077                 return 0;
1078
1079         mutex_lock(&dp->panel_lock);
1080
1081         /*
1082          * Exit early if this is a temporary prepare/unprepare and we're already
1083          * modeset (since we neither want to prepare twice or unprepare early).
1084          */
1085         if (dp->panel_is_modeset && !is_modeset_prepare)
1086                 goto out;
1087
1088         if (prepare)
1089                 ret = drm_panel_prepare(dp->plat_data->panel);
1090         else
1091                 ret = drm_panel_unprepare(dp->plat_data->panel);
1092
1093         if (ret)
1094                 goto out;
1095
1096         if (is_modeset_prepare)
1097                 dp->panel_is_modeset = prepare;
1098
1099 out:
1100         mutex_unlock(&dp->panel_lock);
1101         return ret;
1102 }
1103
1104 static int analogix_dp_get_modes(struct drm_connector *connector)
1105 {
1106         struct analogix_dp_device *dp = to_dp(connector);
1107         struct edid *edid;
1108         int ret, num_modes = 0;
1109
1110         if (dp->plat_data->panel) {
1111                 num_modes += drm_panel_get_modes(dp->plat_data->panel);
1112         } else {
1113                 ret = analogix_dp_prepare_panel(dp, true, false);
1114                 if (ret) {
1115                         DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1116                         return 0;
1117                 }
1118
1119                 pm_runtime_get_sync(dp->dev);
1120                 edid = drm_get_edid(connector, &dp->aux.ddc);
1121                 pm_runtime_put(dp->dev);
1122                 if (edid) {
1123                         drm_connector_update_edid_property(&dp->connector,
1124                                                            edid);
1125                         num_modes += drm_add_edid_modes(&dp->connector, edid);
1126                         kfree(edid);
1127                 }
1128
1129                 ret = analogix_dp_prepare_panel(dp, false, false);
1130                 if (ret)
1131                         DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1132         }
1133
1134         if (dp->plat_data->get_modes)
1135                 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1136
1137         return num_modes;
1138 }
1139
1140 static struct drm_encoder *
1141 analogix_dp_best_encoder(struct drm_connector *connector)
1142 {
1143         struct analogix_dp_device *dp = to_dp(connector);
1144
1145         return dp->encoder;
1146 }
1147
1148 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1149         .get_modes = analogix_dp_get_modes,
1150         .best_encoder = analogix_dp_best_encoder,
1151 };
1152
1153 static enum drm_connector_status
1154 analogix_dp_detect(struct drm_connector *connector, bool force)
1155 {
1156         struct analogix_dp_device *dp = to_dp(connector);
1157         enum drm_connector_status status = connector_status_disconnected;
1158         int ret;
1159
1160         if (dp->plat_data->panel)
1161                 return connector_status_connected;
1162
1163         ret = analogix_dp_prepare_panel(dp, true, false);
1164         if (ret) {
1165                 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1166                 return connector_status_disconnected;
1167         }
1168
1169         if (!analogix_dp_detect_hpd(dp))
1170                 status = connector_status_connected;
1171
1172         ret = analogix_dp_prepare_panel(dp, false, false);
1173         if (ret)
1174                 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1175
1176         return status;
1177 }
1178
1179 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1180         .fill_modes = drm_helper_probe_single_connector_modes,
1181         .detect = analogix_dp_detect,
1182         .destroy = drm_connector_cleanup,
1183         .reset = drm_atomic_helper_connector_reset,
1184         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1185         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1186 };
1187
1188 static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1189 {
1190         struct analogix_dp_device *dp = bridge->driver_private;
1191         struct drm_encoder *encoder = dp->encoder;
1192         struct drm_connector *connector = NULL;
1193         int ret = 0;
1194
1195         if (!bridge->encoder) {
1196                 DRM_ERROR("Parent encoder object not found");
1197                 return -ENODEV;
1198         }
1199
1200         if (!dp->plat_data->skip_connector) {
1201                 connector = &dp->connector;
1202                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1203
1204                 ret = drm_connector_init(dp->drm_dev, connector,
1205                                          &analogix_dp_connector_funcs,
1206                                          DRM_MODE_CONNECTOR_eDP);
1207                 if (ret) {
1208                         DRM_ERROR("Failed to initialize connector with drm\n");
1209                         return ret;
1210                 }
1211
1212                 drm_connector_helper_add(connector,
1213                                          &analogix_dp_connector_helper_funcs);
1214                 drm_connector_attach_encoder(connector, encoder);
1215         }
1216
1217         /*
1218          * NOTE: the connector registration is implemented in analogix
1219          * platform driver, that to say connector would be exist after
1220          * plat_data->attch return, that's why we record the connector
1221          * point after plat attached.
1222          */
1223          if (dp->plat_data->attach) {
1224                  ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1225                  if (ret) {
1226                          DRM_ERROR("Failed at platform attch func\n");
1227                          return ret;
1228                  }
1229         }
1230
1231         if (dp->plat_data->panel) {
1232                 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1233                 if (ret) {
1234                         DRM_ERROR("Failed to attach panel\n");
1235                         return ret;
1236                 }
1237         }
1238
1239         return 0;
1240 }
1241
1242 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
1243 {
1244         struct analogix_dp_device *dp = bridge->driver_private;
1245         int ret;
1246
1247         ret = analogix_dp_prepare_panel(dp, true, true);
1248         if (ret)
1249                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1250 }
1251
1252 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1253 {
1254         int ret;
1255
1256         pm_runtime_get_sync(dp->dev);
1257
1258         ret = clk_prepare_enable(dp->clock);
1259         if (ret < 0) {
1260                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1261                 goto out_dp_clk_pre;
1262         }
1263
1264         if (dp->plat_data->power_on_start)
1265                 dp->plat_data->power_on_start(dp->plat_data);
1266
1267         phy_power_on(dp->phy);
1268
1269         ret = analogix_dp_init_dp(dp);
1270         if (ret)
1271                 goto out_dp_init;
1272
1273         /*
1274          * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1275          * We should first make sure the HPD signal is asserted high by device
1276          * when we want to establish a link with it.
1277          */
1278         ret = analogix_dp_detect_hpd(dp);
1279         if (ret) {
1280                 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1281                 goto out_dp_init;
1282         }
1283
1284         ret = analogix_dp_commit(dp);
1285         if (ret) {
1286                 DRM_ERROR("dp commit error, ret = %d\n", ret);
1287                 goto out_dp_init;
1288         }
1289
1290         if (dp->plat_data->power_on_end)
1291                 dp->plat_data->power_on_end(dp->plat_data);
1292
1293         enable_irq(dp->irq);
1294         return 0;
1295
1296 out_dp_init:
1297         phy_power_off(dp->phy);
1298         if (dp->plat_data->power_off)
1299                 dp->plat_data->power_off(dp->plat_data);
1300         clk_disable_unprepare(dp->clock);
1301 out_dp_clk_pre:
1302         pm_runtime_put_sync(dp->dev);
1303
1304         return ret;
1305 }
1306
1307 static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1308 {
1309         struct analogix_dp_device *dp = bridge->driver_private;
1310         int timeout_loop = 0;
1311
1312         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1313                 return;
1314
1315         while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1316                 if (analogix_dp_set_bridge(dp) == 0) {
1317                         dp->dpms_mode = DRM_MODE_DPMS_ON;
1318                         return;
1319                 }
1320                 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1321                         timeout_loop);
1322                 timeout_loop++;
1323                 usleep_range(10, 11);
1324         }
1325         dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1326 }
1327
1328 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1329 {
1330         struct analogix_dp_device *dp = bridge->driver_private;
1331         int ret;
1332
1333         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1334                 return;
1335
1336         if (dp->plat_data->panel) {
1337                 if (drm_panel_disable(dp->plat_data->panel)) {
1338                         DRM_ERROR("failed to disable the panel\n");
1339                         return;
1340                 }
1341         }
1342
1343         disable_irq(dp->irq);
1344
1345         if (dp->plat_data->power_off)
1346                 dp->plat_data->power_off(dp->plat_data);
1347
1348         analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1349         phy_power_off(dp->phy);
1350
1351         clk_disable_unprepare(dp->clock);
1352
1353         pm_runtime_put_sync(dp->dev);
1354
1355         ret = analogix_dp_prepare_panel(dp, false, true);
1356         if (ret)
1357                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1358
1359         dp->psr_enable = false;
1360         dp->fast_train_enable = false;
1361         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1362 }
1363
1364 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1365                                         struct drm_display_mode *orig_mode,
1366                                         struct drm_display_mode *mode)
1367 {
1368         struct analogix_dp_device *dp = bridge->driver_private;
1369         struct drm_display_info *display_info = &dp->connector.display_info;
1370         struct video_info *video = &dp->video_info;
1371         struct device_node *dp_node = dp->dev->of_node;
1372         int vic;
1373
1374         /* Input video interlaces & hsync pol & vsync pol */
1375         video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1376         video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1377         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1378
1379         /* Input video dynamic_range & colorimetry */
1380         vic = drm_match_cea_mode(mode);
1381         if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1382             (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1383                 video->dynamic_range = CEA;
1384                 video->ycbcr_coeff = COLOR_YCBCR601;
1385         } else if (vic) {
1386                 video->dynamic_range = CEA;
1387                 video->ycbcr_coeff = COLOR_YCBCR709;
1388         } else {
1389                 video->dynamic_range = VESA;
1390                 video->ycbcr_coeff = COLOR_YCBCR709;
1391         }
1392
1393         /* Input vide bpc and color_formats */
1394         switch (display_info->bpc) {
1395         case 12:
1396                 video->color_depth = COLOR_12;
1397                 break;
1398         case 10:
1399                 video->color_depth = COLOR_10;
1400                 break;
1401         case 8:
1402                 video->color_depth = COLOR_8;
1403                 break;
1404         case 6:
1405                 video->color_depth = COLOR_6;
1406                 break;
1407         default:
1408                 video->color_depth = COLOR_8;
1409                 break;
1410         }
1411         if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1412                 video->color_space = COLOR_YCBCR444;
1413         else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1414                 video->color_space = COLOR_YCBCR422;
1415         else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
1416                 video->color_space = COLOR_RGB;
1417         else
1418                 video->color_space = COLOR_RGB;
1419
1420         /*
1421          * NOTE: those property parsing code is used for providing backward
1422          * compatibility for samsung platform.
1423          * Due to we used the "of_property_read_u32" interfaces, when this
1424          * property isn't present, the "video_info" can keep the original
1425          * values and wouldn't be modified.
1426          */
1427         of_property_read_u32(dp_node, "samsung,color-space",
1428                              &video->color_space);
1429         of_property_read_u32(dp_node, "samsung,dynamic-range",
1430                              &video->dynamic_range);
1431         of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1432                              &video->ycbcr_coeff);
1433         of_property_read_u32(dp_node, "samsung,color-depth",
1434                              &video->color_depth);
1435         if (of_property_read_bool(dp_node, "hsync-active-high"))
1436                 video->h_sync_polarity = true;
1437         if (of_property_read_bool(dp_node, "vsync-active-high"))
1438                 video->v_sync_polarity = true;
1439         if (of_property_read_bool(dp_node, "interlaced"))
1440                 video->interlaced = true;
1441 }
1442
1443 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1444 {
1445         /* do nothing */
1446 }
1447
1448 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1449         .pre_enable = analogix_dp_bridge_pre_enable,
1450         .enable = analogix_dp_bridge_enable,
1451         .disable = analogix_dp_bridge_disable,
1452         .post_disable = analogix_dp_bridge_nop,
1453         .mode_set = analogix_dp_bridge_mode_set,
1454         .attach = analogix_dp_bridge_attach,
1455 };
1456
1457 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1458                                      struct analogix_dp_device *dp)
1459 {
1460         struct drm_bridge *bridge;
1461         int ret;
1462
1463         bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1464         if (!bridge) {
1465                 DRM_ERROR("failed to allocate for drm bridge\n");
1466                 return -ENOMEM;
1467         }
1468
1469         dp->bridge = bridge;
1470
1471         bridge->driver_private = dp;
1472         bridge->funcs = &analogix_dp_bridge_funcs;
1473
1474         ret = drm_bridge_attach(dp->encoder, bridge, NULL);
1475         if (ret) {
1476                 DRM_ERROR("failed to attach drm bridge\n");
1477                 return -EINVAL;
1478         }
1479
1480         return 0;
1481 }
1482
1483 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1484 {
1485         struct device_node *dp_node = dp->dev->of_node;
1486         struct video_info *video_info = &dp->video_info;
1487
1488         switch (dp->plat_data->dev_type) {
1489         case RK3288_DP:
1490         case RK3399_EDP:
1491                 /*
1492                  * Like Rk3288 DisplayPort TRM indicate that "Main link
1493                  * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1494                  */
1495                 video_info->max_link_rate = 0x0A;
1496                 video_info->max_lane_count = 0x04;
1497                 break;
1498         case EXYNOS_DP:
1499                 /*
1500                  * NOTE: those property parseing code is used for
1501                  * providing backward compatibility for samsung platform.
1502                  */
1503                 of_property_read_u32(dp_node, "samsung,link-rate",
1504                                      &video_info->max_link_rate);
1505                 of_property_read_u32(dp_node, "samsung,lane-count",
1506                                      &video_info->max_lane_count);
1507                 break;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1514                                        struct drm_dp_aux_msg *msg)
1515 {
1516         struct analogix_dp_device *dp = to_dp(aux);
1517         int ret;
1518
1519         pm_runtime_get_sync(dp->dev);
1520
1521         ret = analogix_dp_detect_hpd(dp);
1522         if (ret)
1523                 goto out;
1524
1525         ret = analogix_dp_transfer(dp, msg);
1526 out:
1527         pm_runtime_put(dp->dev);
1528
1529         return ret;
1530 }
1531
1532 struct analogix_dp_device *
1533 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1534                  struct analogix_dp_plat_data *plat_data)
1535 {
1536         struct platform_device *pdev = to_platform_device(dev);
1537         struct analogix_dp_device *dp;
1538         struct resource *res;
1539         unsigned int irq_flags;
1540         int ret;
1541
1542         if (!plat_data) {
1543                 dev_err(dev, "Invalided input plat_data\n");
1544                 return ERR_PTR(-EINVAL);
1545         }
1546
1547         dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1548         if (!dp)
1549                 return ERR_PTR(-ENOMEM);
1550
1551         dp->dev = &pdev->dev;
1552         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1553
1554         mutex_init(&dp->panel_lock);
1555         dp->panel_is_modeset = false;
1556
1557         /*
1558          * platform dp driver need containor_of the plat_data to get
1559          * the driver private data, so we need to store the point of
1560          * plat_data, not the context of plat_data.
1561          */
1562         dp->plat_data = plat_data;
1563
1564         ret = analogix_dp_dt_parse_pdata(dp);
1565         if (ret)
1566                 return ERR_PTR(ret);
1567
1568         dp->phy = devm_phy_get(dp->dev, "dp");
1569         if (IS_ERR(dp->phy)) {
1570                 dev_err(dp->dev, "no DP phy configured\n");
1571                 ret = PTR_ERR(dp->phy);
1572                 if (ret) {
1573                         /*
1574                          * phy itself is not enabled, so we can move forward
1575                          * assigning NULL to phy pointer.
1576                          */
1577                         if (ret == -ENOSYS || ret == -ENODEV)
1578                                 dp->phy = NULL;
1579                         else
1580                                 return ERR_PTR(ret);
1581                 }
1582         }
1583
1584         dp->clock = devm_clk_get(&pdev->dev, "dp");
1585         if (IS_ERR(dp->clock)) {
1586                 dev_err(&pdev->dev, "failed to get clock\n");
1587                 return ERR_CAST(dp->clock);
1588         }
1589
1590         clk_prepare_enable(dp->clock);
1591
1592         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1593
1594         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1595         if (IS_ERR(dp->reg_base))
1596                 return ERR_CAST(dp->reg_base);
1597
1598         dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1599
1600         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
1601         if (!gpio_is_valid(dp->hpd_gpio))
1602                 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
1603                                                  "samsung,hpd-gpio", 0);
1604
1605         if (gpio_is_valid(dp->hpd_gpio)) {
1606                 /*
1607                  * Set up the hotplug GPIO from the device tree as an interrupt.
1608                  * Simply specifying a different interrupt in the device tree
1609                  * doesn't work since we handle hotplug rather differently when
1610                  * using a GPIO.  We also need the actual GPIO specifier so
1611                  * that we can get the current state of the GPIO.
1612                  */
1613                 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1614                                             "hpd_gpio");
1615                 if (ret) {
1616                         dev_err(&pdev->dev, "failed to get hpd gpio\n");
1617                         return ERR_PTR(ret);
1618                 }
1619                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1620                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1621         } else {
1622                 dp->hpd_gpio = -ENODEV;
1623                 dp->irq = platform_get_irq(pdev, 0);
1624                 irq_flags = 0;
1625         }
1626
1627         if (dp->irq == -ENXIO) {
1628                 dev_err(&pdev->dev, "failed to get irq\n");
1629                 return ERR_PTR(-ENODEV);
1630         }
1631
1632         ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1633                                         analogix_dp_hardirq,
1634                                         analogix_dp_irq_thread,
1635                                         irq_flags, "analogix-dp", dp);
1636         if (ret) {
1637                 dev_err(&pdev->dev, "failed to request irq\n");
1638                 goto err_disable_pm_runtime;
1639         }
1640         disable_irq(dp->irq);
1641
1642         dp->drm_dev = drm_dev;
1643         dp->encoder = dp->plat_data->encoder;
1644
1645         dp->aux.name = "DP-AUX";
1646         dp->aux.transfer = analogix_dpaux_transfer;
1647         dp->aux.dev = &pdev->dev;
1648
1649         ret = drm_dp_aux_register(&dp->aux);
1650         if (ret)
1651                 return ERR_PTR(ret);
1652
1653         pm_runtime_enable(dev);
1654
1655         ret = analogix_dp_create_bridge(drm_dev, dp);
1656         if (ret) {
1657                 DRM_ERROR("failed to create bridge (%d)\n", ret);
1658                 goto err_disable_pm_runtime;
1659         }
1660
1661         return dp;
1662
1663 err_disable_pm_runtime:
1664
1665         pm_runtime_disable(dev);
1666
1667         return ERR_PTR(ret);
1668 }
1669 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1670
1671 void analogix_dp_unbind(struct analogix_dp_device *dp)
1672 {
1673         analogix_dp_bridge_disable(dp->bridge);
1674         dp->connector.funcs->destroy(&dp->connector);
1675
1676         if (dp->plat_data->panel) {
1677                 if (drm_panel_unprepare(dp->plat_data->panel))
1678                         DRM_ERROR("failed to turnoff the panel\n");
1679                 if (drm_panel_detach(dp->plat_data->panel))
1680                         DRM_ERROR("failed to detach the panel\n");
1681         }
1682
1683         drm_dp_aux_unregister(&dp->aux);
1684         pm_runtime_disable(dp->dev);
1685         clk_disable_unprepare(dp->clock);
1686 }
1687 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1688
1689 #ifdef CONFIG_PM
1690 int analogix_dp_suspend(struct analogix_dp_device *dp)
1691 {
1692         clk_disable_unprepare(dp->clock);
1693         return 0;
1694 }
1695 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1696
1697 int analogix_dp_resume(struct analogix_dp_device *dp)
1698 {
1699         int ret;
1700
1701         ret = clk_prepare_enable(dp->clock);
1702         if (ret < 0) {
1703                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1704                 return ret;
1705         }
1706
1707         return 0;
1708 }
1709 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1710 #endif
1711
1712 int analogix_dp_start_crc(struct drm_connector *connector)
1713 {
1714         struct analogix_dp_device *dp = to_dp(connector);
1715
1716         if (!connector->state->crtc) {
1717                 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1718                           connector->name);
1719                 return -EINVAL;
1720         }
1721
1722         return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1723 }
1724 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1725
1726 int analogix_dp_stop_crc(struct drm_connector *connector)
1727 {
1728         struct analogix_dp_device *dp = to_dp(connector);
1729
1730         return drm_dp_stop_crc(&dp->aux);
1731 }
1732 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1733
1734 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1735 MODULE_DESCRIPTION("Analogix DP Core Driver");
1736 MODULE_LICENSE("GPL v2");