drivers/gpu/drm/bridge/sil-sii8620.c

   1 /*
   2  * Silicon Image SiI8620 HDMI/MHL bridge driver
   3  *
   4  * Copyright (C) 2015, Samsung Electronics Co., Ltd.
   5  * Andrzej Hajda <a.hajda@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <asm/unaligned.h>
  13
  14 #include <drm/bridge/mhl.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_edid.h>
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/i2c.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/kernel.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/slab.h>
  30
  31 #include "sil-sii8620.h"
  32
  33 #define SII8620_BURST_BUF_LEN 288
  34 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
  35 #define MHL1_MAX_LCLK 225000
  36 #define MHL3_MAX_LCLK 600000
  37
  38 enum sii8620_mode {
  39         CM_DISCONNECTED,
  40         CM_DISCOVERY,
  41         CM_MHL1,
  42         CM_MHL3,
  43         CM_ECBUS_S
  44 };
  45
  46 enum sii8620_sink_type {
  47         SINK_NONE,
  48         SINK_HDMI,
  49         SINK_DVI
  50 };
  51
  52 enum sii8620_mt_state {
  53         MT_STATE_READY,
  54         MT_STATE_BUSY,
  55         MT_STATE_DONE
  56 };
  57
  58 struct sii8620 {
  59         struct drm_bridge bridge;
  60         struct device *dev;
  61         struct clk *clk_xtal;
  62         struct gpio_desc *gpio_reset;
  63         struct gpio_desc *gpio_int;
  64         struct regulator_bulk_data supplies[2];
  65         struct mutex lock; /* context lock, protects fields below */
  66         int error;
  67         int pixel_clock;
  68         unsigned int use_packed_pixel:1;
  69         int video_code;
  70         enum sii8620_mode mode;
  71         enum sii8620_sink_type sink_type;
  72         u8 cbus_status;
  73         u8 stat[MHL_DST_SIZE];
  74         u8 xstat[MHL_XDS_SIZE];
  75         u8 devcap[MHL_DCAP_SIZE];
  76         u8 xdevcap[MHL_XDC_SIZE];
  77         u8 avif[HDMI_INFOFRAME_SIZE(AVI)];
  78         struct edid *edid;
  79         unsigned int gen2_write_burst:1;
  80         enum sii8620_mt_state mt_state;
  81         struct list_head mt_queue;
  82         struct {
  83                 int r_size;
  84                 int r_count;
  85                 int rx_ack;
  86                 int rx_count;
  87                 u8 rx_buf[32];
  88                 int tx_count;
  89                 u8 tx_buf[32];
  90         } burst;
  91 };
  92
  93 struct sii8620_mt_msg;
  94
  95 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx,
  96                                   struct sii8620_mt_msg *msg);
  97
  98 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret);
  99
 100 struct sii8620_mt_msg {
 101         struct list_head node;
 102         u8 reg[4];
 103         u8 ret;
 104         sii8620_mt_msg_cb send;
 105         sii8620_mt_msg_cb recv;
 106         sii8620_cb continuation;
 107 };
 108
 109 static const u8 sii8620_i2c_page[] = {
 110         0x39, /* Main System */
 111         0x3d, /* TDM and HSIC */
 112         0x49, /* TMDS Receiver, MHL EDID */
 113         0x4d, /* eMSC, HDCP, HSIC */
 114         0x5d, /* MHL Spec */
 115         0x64, /* MHL CBUS */
 116         0x59, /* Hardware TPI (Transmitter Programming Interface) */
 117         0x61, /* eCBUS-S, eCBUS-D */
 118 };
 119
 120 static void sii8620_fetch_edid(struct sii8620 *ctx);
 121 static void sii8620_set_upstream_edid(struct sii8620 *ctx);
 122 static void sii8620_enable_hpd(struct sii8620 *ctx);
 123 static void sii8620_mhl_disconnected(struct sii8620 *ctx);
 124 static void sii8620_disconnect(struct sii8620 *ctx);
 125
 126 static int sii8620_clear_error(struct sii8620 *ctx)
 127 {
 128         int ret = ctx->error;
 129
 130         ctx->error = 0;
 131         return ret;
 132 }
 133
 134 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len)
 135 {
 136         struct device *dev = ctx->dev;
 137         struct i2c_client *client = to_i2c_client(dev);
 138         u8 data = addr;
 139         struct i2c_msg msg[] = {
 140                 {
 141                         .addr = sii8620_i2c_page[addr >> 8],
 142                         .flags = client->flags,
 143                         .len = 1,
 144                         .buf = &data
 145                 },
 146                 {
 147                         .addr = sii8620_i2c_page[addr >> 8],
 148                         .flags = client->flags | I2C_M_RD,
 149                         .len = len,
 150                         .buf = buf
 151                 },
 152         };
 153         int ret;
 154
 155         if (ctx->error)
 156                 return;
 157
 158         ret = i2c_transfer(client->adapter, msg, 2);
 159         dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret);
 160
 161         if (ret != 2) {
 162                 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n",
 163                         addr, len, ret);
 164                 ctx->error = ret < 0 ? ret : -EIO;
 165         }
 166 }
 167
 168 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr)
 169 {
 170         u8 ret = 0;
 171
 172         sii8620_read_buf(ctx, addr, &ret, 1);
 173         return ret;
 174 }
 175
 176 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf,
 177                               int len)
 178 {
 179         struct device *dev = ctx->dev;
 180         struct i2c_client *client = to_i2c_client(dev);
 181         u8 data[2];
 182         struct i2c_msg msg = {
 183                 .addr = sii8620_i2c_page[addr >> 8],
 184                 .flags = client->flags,
 185                 .len = len + 1,
 186         };
 187         int ret;
 188
 189         if (ctx->error)
 190                 return;
 191
 192         if (len > 1) {
 193                 msg.buf = kmalloc(len + 1, GFP_KERNEL);
 194                 if (!msg.buf) {
 195                         ctx->error = -ENOMEM;
 196                         return;
 197                 }
 198                 memcpy(msg.buf + 1, buf, len);
 199         } else {
 200                 msg.buf = data;
 201                 msg.buf[1] = *buf;
 202         }
 203
 204         msg.buf[0] = addr;
 205
 206         ret = i2c_transfer(client->adapter, &msg, 1);
 207         dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret);
 208
 209         if (ret != 1) {
 210                 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n",
 211                         addr, len, buf, ret);
 212                 ctx->error = ret ?: -EIO;
 213         }
 214
 215         if (len > 1)
 216                 kfree(msg.buf);
 217 }
 218
 219 #define sii8620_write(ctx, addr, arr...) \
 220 ({\
 221         u8 d[] = { arr }; \
 222         sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \
 223 })
 224
 225 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len)
 226 {
 227         int i;
 228
 229         for (i = 0; i < len; i += 2)
 230                 sii8620_write(ctx, seq[i], seq[i + 1]);
 231 }
 232
 233 #define sii8620_write_seq(ctx, seq...) \
 234 ({\
 235         const u16 d[] = { seq }; \
 236         __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
 237 })
 238
 239 #define sii8620_write_seq_static(ctx, seq...) \
 240 ({\
 241         static const u16 d[] = { seq }; \
 242         __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
 243 })
 244
 245 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
 246 {
 247         val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask);
 248         sii8620_write(ctx, addr, val);
 249 }
 250
 251 static inline bool sii8620_is_mhl3(struct sii8620 *ctx)
 252 {
 253         return ctx->mode >= CM_MHL3;
 254 }
 255
 256 static void sii8620_mt_cleanup(struct sii8620 *ctx)
 257 {
 258         struct sii8620_mt_msg *msg, *n;
 259
 260         list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) {
 261                 list_del(&msg->node);
 262                 kfree(msg);
 263         }
 264         ctx->mt_state = MT_STATE_READY;
 265 }
 266
 267 static void sii8620_mt_work(struct sii8620 *ctx)
 268 {
 269         struct sii8620_mt_msg *msg;
 270
 271         if (ctx->error)
 272                 return;
 273         if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue))
 274                 return;
 275
 276         if (ctx->mt_state == MT_STATE_DONE) {
 277                 ctx->mt_state = MT_STATE_READY;
 278                 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg,
 279                                        node);
 280                 list_del(&msg->node);
 281                 if (msg->recv)
 282                         msg->recv(ctx, msg);
 283                 if (msg->continuation)
 284                         msg->continuation(ctx, msg->ret);
 285                 kfree(msg);
 286         }
 287
 288         if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue))
 289                 return;
 290
 291         ctx->mt_state = MT_STATE_BUSY;
 292         msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
 293         if (msg->send)
 294                 msg->send(ctx, msg);
 295 }
 296
 297 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx)
 298 {
 299         u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN;
 300
 301         if (ctx->gen2_write_burst)
 302                 return;
 303
 304         if (ctx->mode >= CM_MHL1)
 305                 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN;
 306
 307         sii8620_write_seq(ctx,
 308                 REG_MDT_RCV_TIMEOUT, 100,
 309                 REG_MDT_RCV_CTRL, ctrl
 310         );
 311         ctx->gen2_write_burst = 1;
 312 }
 313
 314 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx)
 315 {
 316         if (!ctx->gen2_write_burst)
 317                 return;
 318
 319         sii8620_write_seq_static(ctx,
 320                 REG_MDT_XMIT_CTRL, 0,
 321                 REG_MDT_RCV_CTRL, 0
 322         );
 323         ctx->gen2_write_burst = 0;
 324 }
 325
 326 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx)
 327 {
 328         sii8620_write_seq_static(ctx,
 329                 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT
 330                         | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR
 331                         | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD
 332                         | BIT_MDT_XMIT_SM_ERROR,
 333                 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY
 334                         | BIT_MDT_IDLE_AFTER_HAWB_DISABLE
 335                         | BIT_MDT_RFIFO_DATA_RDY
 336         );
 337         sii8620_enable_gen2_write_burst(ctx);
 338 }
 339
 340 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx,
 341                                     struct sii8620_mt_msg *msg)
 342 {
 343         if (msg->reg[0] == MHL_SET_INT &&
 344             msg->reg[1] == MHL_INT_REG(RCHANGE) &&
 345             msg->reg[2] == MHL_INT_RC_FEAT_REQ)
 346                 sii8620_enable_gen2_write_burst(ctx);
 347         else
 348                 sii8620_disable_gen2_write_burst(ctx);
 349
 350         switch (msg->reg[0]) {
 351         case MHL_WRITE_STAT:
 352         case MHL_SET_INT:
 353                 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2);
 354                 sii8620_write(ctx, REG_MSC_COMMAND_START,
 355                               BIT_MSC_COMMAND_START_WRITE_STAT);
 356                 break;
 357         case MHL_MSC_MSG:
 358                 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3);
 359                 sii8620_write(ctx, REG_MSC_COMMAND_START,
 360                               BIT_MSC_COMMAND_START_MSC_MSG);
 361                 break;
 362         case MHL_READ_DEVCAP_REG:
 363         case MHL_READ_XDEVCAP_REG:
 364                 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]);
 365                 sii8620_write(ctx, REG_MSC_COMMAND_START,
 366                               BIT_MSC_COMMAND_START_READ_DEVCAP);
 367                 break;
 368         default:
 369                 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__,
 370                         msg->reg[0]);
 371         }
 372 }
 373
 374 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx)
 375 {
 376         struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL);
 377
 378         if (!msg)
 379                 ctx->error = -ENOMEM;
 380         else
 381                 list_add_tail(&msg->node, &ctx->mt_queue);
 382
 383         return msg;
 384 }
 385
 386 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont)
 387 {
 388         struct sii8620_mt_msg *msg;
 389
 390         if (ctx->error)
 391                 return;
 392
 393         if (list_empty(&ctx->mt_queue)) {
 394                 ctx->error = -EINVAL;
 395                 return;
 396         }
 397         msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
 398         msg->continuation = cont;
 399 }
 400
 401 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2)
 402 {
 403         struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 404
 405         if (!msg)
 406                 return;
 407
 408         msg->reg[0] = cmd;
 409         msg->reg[1] = arg1;
 410         msg->reg[2] = arg2;
 411         msg->send = sii8620_mt_msc_cmd_send;
 412 }
 413
 414 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
 415 {
 416         sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val);
 417 }
 418
 419 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
 420 {
 421         sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask);
 422 }
 423
 424 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
 425 {
 426         sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data);
 427 }
 428
 429 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
 430 {
 431         sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
 432 }
 433
 434 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
 435                                         struct sii8620_mt_msg *msg)
 436 {
 437         u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
 438                         | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 439                         | BIT_EDID_CTRL_EDID_MODE_EN;
 440
 441         if (msg->reg[0] == MHL_READ_XDEVCAP)
 442                 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
 443
 444         sii8620_write_seq(ctx,
 445                 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE,
 446                 REG_EDID_CTRL, ctrl,
 447                 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START
 448         );
 449 }
 450
 451 /* copy src to dst and set changed bits in src */
 452 static void sii8620_update_array(u8 *dst, u8 *src, int count)
 453 {
 454         while (--count >= 0) {
 455                 *src ^= *dst;
 456                 *dst++ ^= *src++;
 457         }
 458 }
 459
 460 static void sii8620_sink_detected(struct sii8620 *ctx, int ret)
 461 {
 462         static const char * const sink_str[] = {
 463                 [SINK_NONE] = "NONE",
 464                 [SINK_HDMI] = "HDMI",
 465                 [SINK_DVI] = "DVI"
 466         };
 467
 468         char sink_name[20];
 469         struct device *dev = ctx->dev;
 470
 471         if (ret < 0)
 472                 return;
 473
 474         sii8620_fetch_edid(ctx);
 475         if (!ctx->edid) {
 476                 dev_err(ctx->dev, "Cannot fetch EDID\n");
 477                 sii8620_mhl_disconnected(ctx);
 478                 return;
 479         }
 480
 481         if (drm_detect_hdmi_monitor(ctx->edid))
 482                 ctx->sink_type = SINK_HDMI;
 483         else
 484                 ctx->sink_type = SINK_DVI;
 485
 486         drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name));
 487
 488         dev_info(dev, "detected sink(type: %s): %s\n",
 489                  sink_str[ctx->sink_type], sink_name);
 490 }
 491
 492 static void sii8620_hsic_init(struct sii8620 *ctx)
 493 {
 494         if (!sii8620_is_mhl3(ctx))
 495                 return;
 496
 497         sii8620_write(ctx, REG_FCGC,
 498                 BIT_FCGC_HSIC_HOSTMODE | BIT_FCGC_HSIC_ENABLE);
 499         sii8620_setbits(ctx, REG_HRXCTRL3,
 500                 BIT_HRXCTRL3_HRX_STAY_RESET | BIT_HRXCTRL3_STATUS_EN, ~0);
 501         sii8620_setbits(ctx, REG_TTXNUMB, MSK_TTXNUMB_TTX_NUMBPS, 4);
 502         sii8620_setbits(ctx, REG_TRXCTRL, BIT_TRXCTRL_TRX_FROM_SE_COC, ~0);
 503         sii8620_setbits(ctx, REG_HTXCTRL, BIT_HTXCTRL_HTX_DRVCONN1, 0);
 504         sii8620_setbits(ctx, REG_KEEPER, MSK_KEEPER_MODE, VAL_KEEPER_MODE_HOST);
 505         sii8620_write_seq_static(ctx,
 506                 REG_TDMLLCTL, 0,
 507                 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST |
 508                         BIT_UTSRST_KEEPER_SRST | BIT_UTSRST_FC_SRST,
 509                 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST,
 510                 REG_HRXINTL, 0xff,
 511                 REG_HRXINTH, 0xff,
 512                 REG_TTXINTL, 0xff,
 513                 REG_TTXINTH, 0xff,
 514                 REG_TRXINTL, 0xff,
 515                 REG_TRXINTH, 0xff,
 516                 REG_HTXINTL, 0xff,
 517                 REG_HTXINTH, 0xff,
 518                 REG_FCINTR0, 0xff,
 519                 REG_FCINTR1, 0xff,
 520                 REG_FCINTR2, 0xff,
 521                 REG_FCINTR3, 0xff,
 522                 REG_FCINTR4, 0xff,
 523                 REG_FCINTR5, 0xff,
 524                 REG_FCINTR6, 0xff,
 525                 REG_FCINTR7, 0xff
 526         );
 527 }
 528
 529 static void sii8620_edid_read(struct sii8620 *ctx, int ret)
 530 {
 531         if (ret < 0)
 532                 return;
 533
 534         sii8620_set_upstream_edid(ctx);
 535         sii8620_hsic_init(ctx);
 536         sii8620_enable_hpd(ctx);
 537 }
 538
 539 static void sii8620_mr_devcap(struct sii8620 *ctx)
 540 {
 541         u8 dcap[MHL_DCAP_SIZE];
 542         struct device *dev = ctx->dev;
 543
 544         sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
 545         if (ctx->error < 0)
 546                 return;
 547
 548         dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
 549                  dcap[MHL_DCAP_MHL_VERSION] / 16,
 550                  dcap[MHL_DCAP_MHL_VERSION] % 16,
 551                  dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L],
 552                  dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]);
 553         sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
 554 }
 555
 556 static void sii8620_mr_xdevcap(struct sii8620 *ctx)
 557 {
 558         sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap,
 559                          MHL_XDC_SIZE);
 560 }
 561
 562 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,
 563                                         struct sii8620_mt_msg *msg)
 564 {
 565         u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
 566                 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 567                 | BIT_EDID_CTRL_EDID_MODE_EN;
 568
 569         if (msg->reg[0] == MHL_READ_XDEVCAP)
 570                 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
 571
 572         sii8620_write_seq(ctx,
 573                 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE
 574                         | BIT_INTR9_EDID_ERROR,
 575                 REG_EDID_CTRL, ctrl,
 576                 REG_EDID_FIFO_ADDR, 0
 577         );
 578
 579         if (msg->reg[0] == MHL_READ_XDEVCAP)
 580                 sii8620_mr_xdevcap(ctx);
 581         else
 582                 sii8620_mr_devcap(ctx);
 583 }
 584
 585 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap)
 586 {
 587         struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 588
 589         if (!msg)
 590                 return;
 591
 592         msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP;
 593         msg->send = sii8620_mt_read_devcap_send;
 594         msg->recv = sii8620_mt_read_devcap_recv;
 595 }
 596
 597 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx,
 598                 struct sii8620_mt_msg *msg)
 599 {
 600         u8 reg = msg->reg[1] & 0x7f;
 601
 602         if (msg->reg[1] & 0x80)
 603                 ctx->xdevcap[reg] = msg->ret;
 604         else
 605                 ctx->devcap[reg] = msg->ret;
 606 }
 607
 608 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg)
 609 {
 610         struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 611
 612         if (!msg)
 613                 return;
 614
 615         msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG;
 616         msg->reg[1] = reg;
 617         msg->send = sii8620_mt_msc_cmd_send;
 618         msg->recv = sii8620_mt_read_devcap_reg_recv;
 619 }
 620
 621 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg)
 622 {
 623         sii8620_mt_read_devcap_reg(ctx, reg | 0x80);
 624 }
 625
 626 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len)
 627 {
 628         u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count];
 629         int size = len + 2;
 630
 631         if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
 632                 dev_err(ctx->dev, "TX-BLK buffer exhausted\n");
 633                 ctx->error = -EINVAL;
 634                 return NULL;
 635         }
 636
 637         ctx->burst.tx_count += size;
 638         buf[1] = len;
 639
 640         return buf + 2;
 641 }
 642
 643 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len)
 644 {
 645         u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count];
 646         int size = len + 1;
 647
 648         if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
 649                 dev_err(ctx->dev, "RX-BLK buffer exhausted\n");
 650                 ctx->error = -EINVAL;
 651                 return NULL;
 652         }
 653
 654         ctx->burst.rx_count += size;
 655         buf[0] = len;
 656
 657         return buf + 1;
 658 }
 659
 660 static void sii8620_burst_send(struct sii8620 *ctx)
 661 {
 662         int tx_left = ctx->burst.tx_count;
 663         u8 *d = ctx->burst.tx_buf;
 664
 665         while (tx_left > 0) {
 666                 int len = d[1] + 2;
 667
 668                 if (ctx->burst.r_count + len > ctx->burst.r_size)
 669                         break;
 670                 d[0] = min(ctx->burst.rx_ack, 255);
 671                 ctx->burst.rx_ack -= d[0];
 672                 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len);
 673                 ctx->burst.r_count += len;
 674                 tx_left -= len;
 675                 d += len;
 676         }
 677
 678         ctx->burst.tx_count = tx_left;
 679
 680         while (ctx->burst.rx_ack > 0) {
 681                 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 };
 682
 683                 if (ctx->burst.r_count + 2 > ctx->burst.r_size)
 684                         break;
 685                 ctx->burst.rx_ack -= b[0];
 686                 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2);
 687                 ctx->burst.r_count += 2;
 688         }
 689 }
 690
 691 static void sii8620_burst_receive(struct sii8620 *ctx)
 692 {
 693         u8 buf[3], *d;
 694         int count;
 695
 696         sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2);
 697         count = get_unaligned_le16(buf);
 698         while (count > 0) {
 699                 int len = min(count, 3);
 700
 701                 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len);
 702                 count -= len;
 703                 ctx->burst.rx_ack += len - 1;
 704                 ctx->burst.r_count -= buf[1];
 705                 if (ctx->burst.r_count < 0)
 706                         ctx->burst.r_count = 0;
 707
 708                 if (len < 3 || !buf[2])
 709                         continue;
 710
 711                 len = buf[2];
 712                 d = sii8620_burst_get_rx_buf(ctx, len);
 713                 if (!d)
 714                         continue;
 715                 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len);
 716                 count -= len;
 717                 ctx->burst.rx_ack += len;
 718         }
 719 }
 720
 721 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size)
 722 {
 723         struct mhl_burst_blk_rcv_buffer_info *d =
 724                 sii8620_burst_get_tx_buf(ctx, sizeof(*d));
 725         if (!d)
 726                 return;
 727
 728         d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO);
 729         d->size = cpu_to_le16(size);
 730 }
 731
 732 static u8 sii8620_checksum(void *ptr, int size)
 733 {
 734         u8 *d = ptr, sum = 0;
 735
 736         while (size--)
 737                 sum += *d++;
 738
 739         return sum;
 740 }
 741
 742 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h,
 743         enum mhl_burst_id id)
 744 {
 745         h->id = cpu_to_be16(id);
 746         h->total_entries = 1;
 747         h->sequence_index = 1;
 748 }
 749
 750 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt)
 751 {
 752         struct mhl_burst_bits_per_pixel_fmt *d;
 753         const int size = sizeof(*d) + sizeof(d->desc[0]);
 754
 755         d = sii8620_burst_get_tx_buf(ctx, size);
 756         if (!d)
 757                 return;
 758
 759         sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT);
 760         d->num_entries = 1;
 761         d->desc[0].stream_id = 0;
 762         d->desc[0].pixel_format = fmt;
 763         d->hdr.checksum -= sii8620_checksum(d, size);
 764 }
 765
 766 static void sii8620_burst_rx_all(struct sii8620 *ctx)
 767 {
 768         u8 *d = ctx->burst.rx_buf;
 769         int count = ctx->burst.rx_count;
 770
 771         while (count-- > 0) {
 772                 int len = *d++;
 773                 int id = get_unaligned_be16(&d[0]);
 774
 775                 switch (id) {
 776                 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO:
 777                         ctx->burst.r_size = get_unaligned_le16(&d[2]);
 778                         break;
 779                 default:
 780                         break;
 781                 }
 782                 count -= len;
 783                 d += len;
 784         }
 785         ctx->burst.rx_count = 0;
 786 }
 787
 788 static void sii8620_fetch_edid(struct sii8620 *ctx)
 789 {
 790         u8 lm_ddc, ddc_cmd, int3, cbus;
 791         unsigned long timeout;
 792         int fetched, i;
 793         int edid_len = EDID_LENGTH;
 794         u8 *edid;
 795
 796         sii8620_readb(ctx, REG_CBUS_STATUS);
 797         lm_ddc = sii8620_readb(ctx, REG_LM_DDC);
 798         ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD);
 799
 800         sii8620_write_seq(ctx,
 801                 REG_INTR9_MASK, 0,
 802                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
 803                 REG_HDCP2X_POLL_CS, 0x71,
 804                 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX,
 805                 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED,
 806         );
 807
 808         for (i = 0; i < 256; ++i) {
 809                 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS);
 810
 811                 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG))
 812                         break;
 813                 sii8620_write(ctx, REG_DDC_STATUS,
 814                               BIT_DDC_STATUS_DDC_FIFO_EMPTY);
 815         }
 816
 817         sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1);
 818
 819         edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
 820         if (!edid) {
 821                 ctx->error = -ENOMEM;
 822                 return;
 823         }
 824
 825 #define FETCH_SIZE 16
 826         for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) {
 827                 sii8620_readb(ctx, REG_DDC_STATUS);
 828                 sii8620_write_seq(ctx,
 829                         REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT,
 830                         REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO,
 831                         REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY
 832                 );
 833                 sii8620_write_seq(ctx,
 834                         REG_DDC_SEGM, fetched >> 8,
 835                         REG_DDC_OFFSET, fetched & 0xff,
 836                         REG_DDC_DIN_CNT1, FETCH_SIZE,
 837                         REG_DDC_DIN_CNT2, 0,
 838                         REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK
 839                 );
 840
 841                 int3 = 0;
 842                 timeout = jiffies + msecs_to_jiffies(200);
 843                 for (;;) {
 844                         cbus = sii8620_readb(ctx, REG_CBUS_STATUS);
 845                         if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) {
 846                                 kfree(edid);
 847                                 edid = NULL;
 848                                 goto end;
 849                         }
 850                         if (int3 & BIT_DDC_CMD_DONE) {
 851                                 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT)
 852                                     >= FETCH_SIZE)
 853                                         break;
 854                         } else {
 855                                 int3 = sii8620_readb(ctx, REG_INTR3);
 856                         }
 857                         if (time_is_before_jiffies(timeout)) {
 858                                 ctx->error = -ETIMEDOUT;
 859                                 dev_err(ctx->dev, "timeout during EDID read\n");
 860                                 kfree(edid);
 861                                 edid = NULL;
 862                                 goto end;
 863                         }
 864                         usleep_range(10, 20);
 865                 }
 866
 867                 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE);
 868                 if (fetched + FETCH_SIZE == EDID_LENGTH) {
 869                         u8 ext = ((struct edid *)edid)->extensions;
 870
 871                         if (ext) {
 872                                 u8 *new_edid;
 873
 874                                 edid_len += ext * EDID_LENGTH;
 875                                 new_edid = krealloc(edid, edid_len, GFP_KERNEL);
 876                                 if (!new_edid) {
 877                                         kfree(edid);
 878                                         ctx->error = -ENOMEM;
 879                                         return;
 880                                 }
 881                                 edid = new_edid;
 882                         }
 883                 }
 884         }
 885
 886         sii8620_write_seq(ctx,
 887                 REG_INTR3_MASK, BIT_DDC_CMD_DONE,
 888                 REG_LM_DDC, lm_ddc
 889         );
 890
 891 end:
 892         kfree(ctx->edid);
 893         ctx->edid = (struct edid *)edid;
 894 }
 895
 896 static void sii8620_set_upstream_edid(struct sii8620 *ctx)
 897 {
 898         sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N
 899                         | BIT_DPD_PD_MHL_CLK_N, 0xff);
 900
 901         sii8620_write_seq_static(ctx,
 902                 REG_RX_HDMI_CTRL3, 0x00,
 903                 REG_PKT_FILTER_0, 0xFF,
 904                 REG_PKT_FILTER_1, 0xFF,
 905                 REG_ALICE0_BW_I2C, 0x06
 906         );
 907
 908         sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER,
 909                         BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff);
 910
 911         sii8620_write_seq_static(ctx,
 912                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 913                         | BIT_EDID_CTRL_EDID_MODE_EN,
 914                 REG_EDID_FIFO_ADDR, 0,
 915         );
 916
 917         sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid,
 918                           (ctx->edid->extensions + 1) * EDID_LENGTH);
 919
 920         sii8620_write_seq_static(ctx,
 921                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID
 922                         | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 923                         | BIT_EDID_CTRL_EDID_MODE_EN,
 924                 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE,
 925                 REG_INTR9_MASK, 0
 926         );
 927 }
 928
 929 static void sii8620_xtal_set_rate(struct sii8620 *ctx)
 930 {
 931         static const struct {
 932                 unsigned int rate;
 933                 u8 div;
 934                 u8 tp1;
 935         } rates[] = {
 936                 { 19200, 0x04, 0x53 },
 937                 { 20000, 0x04, 0x62 },
 938                 { 24000, 0x05, 0x75 },
 939                 { 30000, 0x06, 0x92 },
 940                 { 38400, 0x0c, 0xbc },
 941         };
 942         unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000;
 943         int i;
 944
 945         for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i)
 946                 if (rate <= rates[i].rate)
 947                         break;
 948
 949         if (rate != rates[i].rate)
 950                 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n",
 951                         rate, rates[i].rate);
 952
 953         sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div);
 954         sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1);
 955 }
 956
 957 static int sii8620_hw_on(struct sii8620 *ctx)
 958 {
 959         int ret;
 960
 961         ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 962         if (ret)
 963                 return ret;
 964         usleep_range(10000, 20000);
 965         return clk_prepare_enable(ctx->clk_xtal);
 966 }
 967
 968 static int sii8620_hw_off(struct sii8620 *ctx)
 969 {
 970         clk_disable_unprepare(ctx->clk_xtal);
 971         gpiod_set_value(ctx->gpio_reset, 1);
 972         return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 973 }
 974
 975 static void sii8620_hw_reset(struct sii8620 *ctx)
 976 {
 977         usleep_range(10000, 20000);
 978         gpiod_set_value(ctx->gpio_reset, 0);
 979         usleep_range(5000, 20000);
 980         gpiod_set_value(ctx->gpio_reset, 1);
 981         usleep_range(10000, 20000);
 982         gpiod_set_value(ctx->gpio_reset, 0);
 983         msleep(300);
 984 }
 985
 986 static void sii8620_cbus_reset(struct sii8620 *ctx)
 987 {
 988         sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST
 989                       | BIT_PWD_SRST_CBUS_RST_SW_EN);
 990         usleep_range(10000, 20000);
 991         sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN);
 992 }
 993
 994 static void sii8620_set_auto_zone(struct sii8620 *ctx)
 995 {
 996         if (ctx->mode != CM_MHL1) {
 997                 sii8620_write_seq_static(ctx,
 998                         REG_TX_ZONE_CTL1, 0x0,
 999                         REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1000                                 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1001                                 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
1002                 );
1003         } else {
1004                 sii8620_write_seq_static(ctx,
1005                         REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE,
1006                         REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1007                                 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
1008                 );
1009         }
1010 }
1011
1012 static void sii8620_stop_video(struct sii8620 *ctx)
1013 {
1014         u8 uninitialized_var(val);
1015
1016         sii8620_write_seq_static(ctx,
1017                 REG_TPI_INTR_EN, 0,
1018                 REG_HDCP2X_INTR0_MASK, 0,
1019                 REG_TPI_COPP_DATA2, 0,
1020                 REG_TPI_INTR_ST0, ~0,
1021         );
1022
1023         switch (ctx->sink_type) {
1024         case SINK_DVI:
1025                 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1026                         | BIT_TPI_SC_TPI_AV_MUTE;
1027                 break;
1028         case SINK_HDMI:
1029         default:
1030                 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1031                         | BIT_TPI_SC_TPI_AV_MUTE
1032                         | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI;
1033                 break;
1034         }
1035
1036         sii8620_write(ctx, REG_TPI_SC, val);
1037 }
1038
1039 static void sii8620_set_format(struct sii8620 *ctx)
1040 {
1041         u8 out_fmt;
1042
1043         if (sii8620_is_mhl3(ctx)) {
1044                 sii8620_setbits(ctx, REG_M3_P0CTRL,
1045                                 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED,
1046                                 ctx->use_packed_pixel ? ~0 : 0);
1047         } else {
1048                 if (ctx->use_packed_pixel) {
1049                         sii8620_write_seq_static(ctx,
1050                                 REG_VID_MODE, BIT_VID_MODE_M1080P,
1051                                 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1,
1052                                 REG_MHLTX_CTL6, 0x60
1053                         );
1054                 } else {
1055                         sii8620_write_seq_static(ctx,
1056                                 REG_VID_MODE, 0,
1057                                 REG_MHL_TOP_CTL, 1,
1058                                 REG_MHLTX_CTL6, 0xa0
1059                         );
1060                 }
1061         }
1062
1063         if (ctx->use_packed_pixel)
1064                 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL);
1065         else
1066                 out_fmt = VAL_TPI_FORMAT(RGB, FULL);
1067
1068         sii8620_write_seq(ctx,
1069                 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL),
1070                 REG_TPI_OUTPUT, out_fmt,
1071         );
1072 }
1073
1074 static int mhl3_infoframe_init(struct mhl3_infoframe *frame)
1075 {
1076         memset(frame, 0, sizeof(*frame));
1077
1078         frame->version = 3;
1079         frame->hev_format = -1;
1080         return 0;
1081 }
1082
1083 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame,
1084                  void *buffer, size_t size)
1085 {
1086         const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE;
1087         u8 *ptr = buffer;
1088
1089         if (size < frm_len)
1090                 return -ENOSPC;
1091
1092         memset(buffer, 0, size);
1093         ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR;
1094         ptr[1] = frame->version;
1095         ptr[2] = MHL3_INFOFRAME_SIZE;
1096         ptr[4] = MHL3_IEEE_OUI & 0xff;
1097         ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff;
1098         ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff;
1099         ptr[7] = frame->video_format & 0x3;
1100         ptr[7] |= (frame->format_type & 0x7) << 2;
1101         ptr[7] |= frame->sep_audio ? BIT(5) : 0;
1102         if (frame->hev_format >= 0) {
1103                 ptr[9] = 1;
1104                 ptr[10] = (frame->hev_format >> 8) & 0xff;
1105                 ptr[11] = frame->hev_format & 0xff;
1106         }
1107         if (frame->av_delay) {
1108                 bool sign = frame->av_delay < 0;
1109                 int delay = sign ? -frame->av_delay : frame->av_delay;
1110
1111                 ptr[12] = (delay >> 16) & 0xf;
1112                 if (sign)
1113                         ptr[12] |= BIT(4);
1114                 ptr[13] = (delay >> 8) & 0xff;
1115                 ptr[14] = delay & 0xff;
1116         }
1117         ptr[3] -= sii8620_checksum(buffer, frm_len);
1118         return frm_len;
1119 }
1120
1121 static void sii8620_set_infoframes(struct sii8620 *ctx)
1122 {
1123         struct mhl3_infoframe mhl_frm;
1124         union hdmi_infoframe frm;
1125         u8 buf[31];
1126         int ret;
1127
1128         if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) {
1129                 sii8620_write(ctx, REG_TPI_SC,
1130                         BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI);
1131                 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, ctx->avif + 3,
1132                         ARRAY_SIZE(ctx->avif) - 3);
1133                 sii8620_write(ctx, REG_PKT_FILTER_0,
1134                         BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1135                         BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1136                         BIT_PKT_FILTER_0_DROP_GCP_PKT,
1137                         BIT_PKT_FILTER_1_DROP_GEN_PKT);
1138                 return;
1139         }
1140
1141         ret = hdmi_avi_infoframe_init(&frm.avi);
1142         frm.avi.colorspace = HDMI_COLORSPACE_YUV422;
1143         frm.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
1144         frm.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9;
1145         frm.avi.colorimetry = HDMI_COLORIMETRY_ITU_709;
1146         frm.avi.video_code = ctx->video_code;
1147         if (!ret)
1148                 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf));
1149         if (ret > 0)
1150                 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3);
1151         sii8620_write(ctx, REG_PKT_FILTER_0,
1152                 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1153                 BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1154                 BIT_PKT_FILTER_0_DROP_AVI_PKT |
1155                 BIT_PKT_FILTER_0_DROP_GCP_PKT,
1156                 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS |
1157                 BIT_PKT_FILTER_1_DROP_GEN_PKT |
1158                 BIT_PKT_FILTER_1_DROP_VSIF_PKT);
1159
1160         sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN
1161                 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI);
1162         ret = mhl3_infoframe_init(&mhl_frm);
1163         if (!ret)
1164                 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf));
1165         sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret);
1166 }
1167
1168 static void sii8620_start_hdmi(struct sii8620 *ctx)
1169 {
1170         sii8620_write_seq_static(ctx,
1171                 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL
1172                         | BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
1173                 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE
1174                         | BIT_VID_OVRRD_M1080P_OVRRD);
1175         sii8620_set_format(ctx);
1176
1177         if (!sii8620_is_mhl3(ctx)) {
1178                 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1179                         MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED);
1180                 sii8620_set_auto_zone(ctx);
1181         } else {
1182                 static const struct {
1183                         int max_clk;
1184                         u8 zone;
1185                         u8 link_rate;
1186                         u8 rrp_decode;
1187                 } clk_spec[] = {
1188                         { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS,
1189                           MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 },
1190                         { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS,
1191                           MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 },
1192                         { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS,
1193                           MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 },
1194                 };
1195                 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN;
1196                 int clk = ctx->pixel_clock * (ctx->use_packed_pixel ? 2 : 3);
1197                 int i;
1198
1199                 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i)
1200                         if (clk < clk_spec[i].max_clk)
1201                                 break;
1202
1203                 if (100 * clk >= 98 * clk_spec[i].max_clk)
1204                         p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN;
1205
1206                 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel);
1207                 sii8620_burst_send(ctx);
1208                 sii8620_write_seq(ctx,
1209                         REG_MHL_DP_CTL0, 0xf0,
1210                         REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone);
1211                 sii8620_setbits(ctx, REG_M3_P0CTRL,
1212                         BIT_M3_P0CTRL_MHL3_P0_PORT_EN
1213                         | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl);
1214                 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE,
1215                         clk_spec[i].rrp_decode);
1216                 sii8620_write_seq_static(ctx,
1217                         REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1218                                 | BIT_M3_CTRL_H2M_SWRST,
1219                         REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1220                 );
1221                 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL),
1222                         clk_spec[i].link_rate);
1223         }
1224
1225         sii8620_set_infoframes(ctx);
1226 }
1227
1228 static void sii8620_start_video(struct sii8620 *ctx)
1229 {
1230         if (!sii8620_is_mhl3(ctx))
1231                 sii8620_stop_video(ctx);
1232
1233         switch (ctx->sink_type) {
1234         case SINK_HDMI:
1235                 sii8620_start_hdmi(ctx);
1236                 break;
1237         case SINK_DVI:
1238         default:
1239                 break;
1240         }
1241 }
1242
1243 static void sii8620_disable_hpd(struct sii8620 *ctx)
1244 {
1245         sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0);
1246         sii8620_write_seq_static(ctx,
1247                 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN,
1248                 REG_INTR8_MASK, 0
1249         );
1250 }
1251
1252 static void sii8620_enable_hpd(struct sii8620 *ctx)
1253 {
1254         sii8620_setbits(ctx, REG_TMDS_CSTAT_P3,
1255                         BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS
1256                         | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0);
1257         sii8620_write_seq_static(ctx,
1258                 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN
1259                         | BIT_HPD_CTRL_HPD_HIGH,
1260         );
1261 }
1262
1263 static void sii8620_mhl_discover(struct sii8620 *ctx)
1264 {
1265         sii8620_write_seq_static(ctx,
1266                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1267                         | BIT_DISC_CTRL9_DISC_PULSE_PROCEED,
1268                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K),
1269                 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT
1270                         | BIT_MHL_EST_INT
1271                         | BIT_NOT_MHL_EST_INT
1272                         | BIT_CBUS_MHL3_DISCON_INT
1273                         | BIT_CBUS_MHL12_DISCON_INT
1274                         | BIT_RGND_READY_INT,
1275                 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1276                         | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1277                         | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1278                 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1279                         | BIT_MHL_DP_CTL0_TX_OE_OVR,
1280                 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1281                 REG_MHL_DP_CTL1, 0xA2,
1282                 REG_MHL_DP_CTL2, 0x03,
1283                 REG_MHL_DP_CTL3, 0x35,
1284                 REG_MHL_DP_CTL5, 0x02,
1285                 REG_MHL_DP_CTL6, 0x02,
1286                 REG_MHL_DP_CTL7, 0x03,
1287                 REG_COC_CTLC, 0xFF,
1288                 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1289                         | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC,
1290                 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE
1291                         | BIT_COC_CALIBRATION_DONE,
1292                 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD
1293                         | BIT_CBUS_CMD_ABORT,
1294                 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE
1295                         | BIT_CBUS_HPD_CHG
1296                         | BIT_CBUS_MSC_MR_WRITE_STAT
1297                         | BIT_CBUS_MSC_MR_MSC_MSG
1298                         | BIT_CBUS_MSC_MR_WRITE_BURST
1299                         | BIT_CBUS_MSC_MR_SET_INT
1300                         | BIT_CBUS_MSC_MT_DONE_NACK
1301         );
1302 }
1303
1304 static void sii8620_peer_specific_init(struct sii8620 *ctx)
1305 {
1306         if (sii8620_is_mhl3(ctx))
1307                 sii8620_write_seq_static(ctx,
1308                         REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD,
1309                         REG_EMSCINTRMASK1,
1310                                 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR
1311                 );
1312         else
1313                 sii8620_write_seq_static(ctx,
1314                         REG_HDCP2X_INTR0_MASK, 0x00,
1315                         REG_EMSCINTRMASK1, 0x00,
1316                         REG_HDCP2X_INTR0, 0xFF,
1317                         REG_INTR1, 0xFF,
1318                         REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
1319                                 | BIT_SYS_CTRL1_TX_CTRL_HDMI
1320                 );
1321 }
1322
1323 #define SII8620_MHL_VERSION                     0x32
1324 #define SII8620_SCRATCHPAD_SIZE                 16
1325 #define SII8620_INT_STAT_SIZE                   0x33
1326
1327 static void sii8620_set_dev_cap(struct sii8620 *ctx)
1328 {
1329         static const u8 devcap[MHL_DCAP_SIZE] = {
1330                 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION,
1331                 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
1332                 [MHL_DCAP_ADOPTER_ID_H] = 0x01,
1333                 [MHL_DCAP_ADOPTER_ID_L] = 0x41,
1334                 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444
1335                         | MHL_DCAP_VID_LINK_PPIXEL
1336                         | MHL_DCAP_VID_LINK_16BPP,
1337                 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH,
1338                 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS,
1339                 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI,
1340                 [MHL_DCAP_BANDWIDTH] = 0x0f,
1341                 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT
1342                         | MHL_DCAP_FEATURE_RAP_SUPPORT
1343                         | MHL_DCAP_FEATURE_SP_SUPPORT,
1344                 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE,
1345                 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE,
1346         };
1347         static const u8 xdcap[MHL_XDC_SIZE] = {
1348                 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075
1349                         | MHL_XDC_ECBUS_S_8BIT,
1350                 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150
1351                         | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600,
1352                 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST,
1353                 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE,
1354         };
1355
1356         sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap));
1357         sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap));
1358 }
1359
1360 static void sii8620_mhl_init(struct sii8620 *ctx)
1361 {
1362         sii8620_write_seq_static(ctx,
1363                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1364                 REG_CBUS_MSC_COMPAT_CTRL,
1365                         BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN,
1366         );
1367
1368         sii8620_peer_specific_init(ctx);
1369
1370         sii8620_disable_hpd(ctx);
1371
1372         sii8620_write_seq_static(ctx,
1373                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
1374                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1375                         | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1376                 REG_TMDS0_CCTRL1, 0x90,
1377                 REG_TMDS_CLK_EN, 0x01,
1378                 REG_TMDS_CH_EN, 0x11,
1379                 REG_BGR_BIAS, 0x87,
1380                 REG_ALICE0_ZONE_CTRL, 0xE8,
1381                 REG_ALICE0_MODE_CTRL, 0x04,
1382         );
1383         sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0);
1384         sii8620_write_seq_static(ctx,
1385                 REG_TPI_HW_OPT3, 0x76,
1386                 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE,
1387                 REG_TPI_DTD_B2, 79,
1388         );
1389         sii8620_set_dev_cap(ctx);
1390         sii8620_write_seq_static(ctx,
1391                 REG_MDT_XMIT_TIMEOUT, 100,
1392                 REG_MDT_XMIT_CTRL, 0x03,
1393                 REG_MDT_XFIFO_STAT, 0x00,
1394                 REG_MDT_RCV_TIMEOUT, 100,
1395                 REG_CBUS_LINK_CTRL_8, 0x1D,
1396         );
1397
1398         sii8620_start_gen2_write_burst(ctx);
1399         sii8620_write_seq_static(ctx,
1400                 REG_BIST_CTRL, 0x00,
1401                 REG_COC_CTL1, 0x10,
1402                 REG_COC_CTL2, 0x18,
1403                 REG_COC_CTLF, 0x07,
1404                 REG_COC_CTL11, 0xF8,
1405                 REG_COC_CTL17, 0x61,
1406                 REG_COC_CTL18, 0x46,
1407                 REG_COC_CTL19, 0x15,
1408                 REG_COC_CTL1A, 0x01,
1409                 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN,
1410                 REG_MHL_COC_CTL4, 0x2D,
1411                 REG_MHL_COC_CTL5, 0xF9,
1412                 REG_MSC_HEARTBEAT_CTRL, 0x27,
1413         );
1414         sii8620_disable_gen2_write_burst(ctx);
1415
1416         sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION);
1417         sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY),
1418                               MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP
1419                               | MHL_DST_CONN_POW_STAT);
1420         sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG);
1421 }
1422
1423 static void sii8620_emsc_enable(struct sii8620 *ctx)
1424 {
1425         u8 reg;
1426
1427         sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN
1428                                          | BIT_GENCTL_CLR_EMSC_RFIFO
1429                                          | BIT_GENCTL_CLR_EMSC_XFIFO, ~0);
1430         sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO
1431                                          | BIT_GENCTL_CLR_EMSC_XFIFO, 0);
1432         sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0);
1433         reg = sii8620_readb(ctx, REG_EMSCINTR);
1434         sii8620_write(ctx, REG_EMSCINTR, reg);
1435         sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD);
1436 }
1437
1438 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state)
1439 {
1440         int i;
1441
1442         for (i = 0; i < 10; ++i) {
1443                 u8 s = sii8620_readb(ctx, REG_COC_STAT_0);
1444
1445                 if ((s & MSK_COC_STAT_0_FSM_STATE) == state)
1446                         return 0;
1447                 if (!(s & BIT_COC_STAT_0_PLL_LOCKED))
1448                         return -EBUSY;
1449                 usleep_range(4000, 6000);
1450         }
1451         return -ETIMEDOUT;
1452 }
1453
1454 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
1455 {
1456         int ret;
1457
1458         if (ctx->mode == mode)
1459                 return;
1460
1461         switch (mode) {
1462         case CM_MHL1:
1463                 sii8620_write_seq_static(ctx,
1464                         REG_CBUS_MSC_COMPAT_CTRL, 0x02,
1465                         REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE,
1466                         REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1467                                 | BIT_DPD_OSC_EN,
1468                         REG_COC_INTR_MASK, 0
1469                 );
1470                 ctx->mode = mode;
1471                 break;
1472         case CM_MHL3:
1473                 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
1474                 ctx->mode = mode;
1475                 return;
1476         case CM_ECBUS_S:
1477                 sii8620_emsc_enable(ctx);
1478                 sii8620_write_seq_static(ctx,
1479                         REG_TTXSPINUMS, 4,
1480                         REG_TRXSPINUMS, 4,
1481                         REG_TTXHSICNUMS, 0x14,
1482                         REG_TRXHSICNUMS, 0x14,
1483                         REG_TTXTOTNUMS, 0x18,
1484                         REG_TRXTOTNUMS, 0x18,
1485                         REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST
1486                                       | BIT_PWD_SRST_CBUS_RST_SW_EN,
1487                         REG_MHL_COC_CTL1, 0xbd,
1488                         REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN,
1489                         REG_COC_CTLB, 0x01,
1490                         REG_COC_CTL0, 0x5c,
1491                         REG_COC_CTL14, 0x03,
1492                         REG_COC_CTL15, 0x80,
1493                         REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN
1494                                          | BIT_MHL_DP_CTL6_DP_TAP1_EN
1495                                          | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN,
1496                         REG_MHL_DP_CTL8, 0x03
1497                 );
1498                 ret = sii8620_wait_for_fsm_state(ctx, 0x03);
1499                 sii8620_write_seq_static(ctx,
1500                         REG_COC_CTL14, 0x00,
1501                         REG_COC_CTL15, 0x80
1502                 );
1503                 if (!ret)
1504                         sii8620_write(ctx, REG_CBUS3_CNVT, 0x85);
1505                 else
1506                         sii8620_disconnect(ctx);
1507                 return;
1508         case CM_DISCONNECTED:
1509                 ctx->mode = mode;
1510                 break;
1511         default:
1512                 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode);
1513                 break;
1514         }
1515
1516         sii8620_set_auto_zone(ctx);
1517
1518         if (mode != CM_MHL1)
1519                 return;
1520
1521         sii8620_write_seq_static(ctx,
1522                 REG_MHL_DP_CTL0, 0xBC,
1523                 REG_MHL_DP_CTL1, 0xBB,
1524                 REG_MHL_DP_CTL3, 0x48,
1525                 REG_MHL_DP_CTL5, 0x39,
1526                 REG_MHL_DP_CTL2, 0x2A,
1527                 REG_MHL_DP_CTL6, 0x2A,
1528                 REG_MHL_DP_CTL7, 0x08
1529         );
1530 }
1531
1532 static void sii8620_disconnect(struct sii8620 *ctx)
1533 {
1534         sii8620_disable_gen2_write_burst(ctx);
1535         sii8620_stop_video(ctx);
1536         msleep(100);
1537         sii8620_cbus_reset(ctx);
1538         sii8620_set_mode(ctx, CM_DISCONNECTED);
1539         sii8620_write_seq_static(ctx,
1540                 REG_TX_ZONE_CTL1, 0,
1541                 REG_MHL_PLL_CTL0, 0x07,
1542                 REG_COC_CTL0, 0x40,
1543                 REG_CBUS3_CNVT, 0x84,
1544                 REG_COC_CTL14, 0x00,
1545                 REG_COC_CTL0, 0x40,
1546                 REG_HRXCTRL3, 0x07,
1547                 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1548                         | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1549                         | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1550                 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1551                         | BIT_MHL_DP_CTL0_TX_OE_OVR,
1552                 REG_MHL_DP_CTL1, 0xBB,
1553                 REG_MHL_DP_CTL3, 0x48,
1554                 REG_MHL_DP_CTL5, 0x3F,
1555                 REG_MHL_DP_CTL2, 0x2F,
1556                 REG_MHL_DP_CTL6, 0x2A,
1557                 REG_MHL_DP_CTL7, 0x03
1558         );
1559         sii8620_disable_hpd(ctx);
1560         sii8620_write_seq_static(ctx,
1561                 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1562                 REG_MHL_COC_CTL1, 0x07,
1563                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1564                 REG_DISC_CTRL8, 0x00,
1565                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1566                         | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1567                 REG_INT_CTRL, 0x00,
1568                 REG_MSC_HEARTBEAT_CTRL, 0x27,
1569                 REG_DISC_CTRL1, 0x25,
1570                 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT,
1571                 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT,
1572                 REG_MDT_INT_1, 0xff,
1573                 REG_MDT_INT_1_MASK, 0x00,
1574                 REG_MDT_INT_0, 0xff,
1575                 REG_MDT_INT_0_MASK, 0x00,
1576                 REG_COC_INTR, 0xff,
1577                 REG_COC_INTR_MASK, 0x00,
1578                 REG_TRXINTH, 0xff,
1579                 REG_TRXINTMH, 0x00,
1580                 REG_CBUS_INT_0, 0xff,
1581                 REG_CBUS_INT_0_MASK, 0x00,
1582                 REG_CBUS_INT_1, 0xff,
1583                 REG_CBUS_INT_1_MASK, 0x00,
1584                 REG_EMSCINTR, 0xff,
1585                 REG_EMSCINTRMASK, 0x00,
1586                 REG_EMSCINTR1, 0xff,
1587                 REG_EMSCINTRMASK1, 0x00,
1588                 REG_INTR8, 0xff,
1589                 REG_INTR8_MASK, 0x00,
1590                 REG_TPI_INTR_ST0, 0xff,
1591                 REG_TPI_INTR_EN, 0x00,
1592                 REG_HDCP2X_INTR0, 0xff,
1593                 REG_HDCP2X_INTR0_MASK, 0x00,
1594                 REG_INTR9, 0xff,
1595                 REG_INTR9_MASK, 0x00,
1596                 REG_INTR3, 0xff,
1597                 REG_INTR3_MASK, 0x00,
1598                 REG_INTR5, 0xff,
1599                 REG_INTR5_MASK, 0x00,
1600                 REG_INTR2, 0xff,
1601                 REG_INTR2_MASK, 0x00,
1602         );
1603         memset(ctx->stat, 0, sizeof(ctx->stat));
1604         memset(ctx->xstat, 0, sizeof(ctx->xstat));
1605         memset(ctx->devcap, 0, sizeof(ctx->devcap));
1606         memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap));
1607         ctx->cbus_status = 0;
1608         ctx->sink_type = SINK_NONE;
1609         kfree(ctx->edid);
1610         ctx->edid = NULL;
1611         sii8620_mt_cleanup(ctx);
1612 }
1613
1614 static void sii8620_mhl_disconnected(struct sii8620 *ctx)
1615 {
1616         sii8620_write_seq_static(ctx,
1617                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1618                 REG_CBUS_MSC_COMPAT_CTRL,
1619                         BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
1620         );
1621         sii8620_disconnect(ctx);
1622 }
1623
1624 static void sii8620_irq_disc(struct sii8620 *ctx)
1625 {
1626         u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0);
1627
1628         if (stat & VAL_CBUS_MHL_DISCON)
1629                 sii8620_mhl_disconnected(ctx);
1630
1631         if (stat & BIT_RGND_READY_INT) {
1632                 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2);
1633
1634                 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) {
1635                         sii8620_mhl_discover(ctx);
1636                 } else {
1637                         sii8620_write_seq_static(ctx,
1638                                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1639                                         | BIT_DISC_CTRL9_NOMHL_EST
1640                                         | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1641                                 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT
1642                                         | BIT_CBUS_MHL3_DISCON_INT
1643                                         | BIT_CBUS_MHL12_DISCON_INT
1644                                         | BIT_NOT_MHL_EST_INT
1645                         );
1646                 }
1647         }
1648         if (stat & BIT_MHL_EST_INT)
1649                 sii8620_mhl_init(ctx);
1650
1651         sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat);
1652 }
1653
1654 static void sii8620_read_burst(struct sii8620 *ctx)
1655 {
1656         u8 buf[17];
1657
1658         sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf));
1659         sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN |
1660                       BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN |
1661                       BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR);
1662         sii8620_readb(ctx, REG_MDT_RFIFO_STAT);
1663 }
1664
1665 static void sii8620_irq_g2wb(struct sii8620 *ctx)
1666 {
1667         u8 stat = sii8620_readb(ctx, REG_MDT_INT_0);
1668
1669         if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE)
1670                 if (sii8620_is_mhl3(ctx))
1671                         sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
1672                                 MHL_INT_RC_FEAT_COMPLETE);
1673
1674         if (stat & BIT_MDT_RFIFO_DATA_RDY)
1675                 sii8620_read_burst(ctx);
1676
1677         if (stat & BIT_MDT_XFIFO_EMPTY)
1678                 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0);
1679
1680         sii8620_write(ctx, REG_MDT_INT_0, stat);
1681 }
1682
1683 static void sii8620_status_dcap_ready(struct sii8620 *ctx)
1684 {
1685         enum sii8620_mode mode;
1686
1687         mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1;
1688         if (mode > ctx->mode)
1689                 sii8620_set_mode(ctx, mode);
1690         sii8620_peer_specific_init(ctx);
1691         sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
1692                       | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
1693 }
1694
1695 static void sii8620_status_changed_path(struct sii8620 *ctx)
1696 {
1697         if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) {
1698                 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1699                                       MHL_DST_LM_CLK_MODE_NORMAL
1700                                       | MHL_DST_LM_PATH_ENABLED);
1701                 if (!sii8620_is_mhl3(ctx))
1702                         sii8620_mt_read_devcap(ctx, false);
1703                 sii8620_mt_set_cont(ctx, sii8620_sink_detected);
1704         } else {
1705                 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1706                                       MHL_DST_LM_CLK_MODE_NORMAL);
1707         }
1708 }
1709
1710 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
1711 {
1712         u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE];
1713
1714         sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE);
1715         sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE);
1716
1717         sii8620_update_array(ctx->stat, st, MHL_DST_SIZE);
1718         sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE);
1719
1720         if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY)
1721                 sii8620_status_dcap_ready(ctx);
1722
1723         if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1724                 sii8620_status_changed_path(ctx);
1725 }
1726
1727 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret)
1728 {
1729         if (ret < 0)
1730                 return;
1731
1732         sii8620_set_mode(ctx, CM_ECBUS_S);
1733 }
1734
1735 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret)
1736 {
1737         if (ret < 0)
1738                 return;
1739
1740         sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
1741                               MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
1742         sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
1743         sii8620_mt_set_cont(ctx, sii8620_ecbus_up);
1744 }
1745
1746 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d,
1747         enum mhl_burst_id id)
1748 {
1749         sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT);
1750         d->num_entries = 1;
1751         d->burst_id[0] = cpu_to_be16(id);
1752 }
1753
1754 static void sii8620_send_features(struct sii8620 *ctx)
1755 {
1756         u8 buf[16];
1757
1758         sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN
1759                 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN);
1760         sii8620_mhl_burst_emsc_support_set((void *)buf,
1761                 MHL_BURST_ID_HID_PAYLOAD);
1762         sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf));
1763 }
1764
1765 static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
1766 {
1767         u8 ints[MHL_INT_SIZE];
1768
1769         sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1770         sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1771
1772         if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) {
1773                 switch (ctx->mode) {
1774                 case CM_MHL3:
1775                         sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS);
1776                         sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed);
1777                         break;
1778                 case CM_ECBUS_S:
1779                         sii8620_mt_read_devcap(ctx, true);
1780                         break;
1781                 default:
1782                         break;
1783                 }
1784         }
1785         if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ)
1786                 sii8620_send_features(ctx);
1787         if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE)
1788                 sii8620_edid_read(ctx, 0);
1789 }
1790
1791 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx)
1792 {
1793         struct device *dev = ctx->dev;
1794
1795         if (list_empty(&ctx->mt_queue)) {
1796                 dev_err(dev, "unexpected MSC MT response\n");
1797                 return NULL;
1798         }
1799
1800         return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
1801 }
1802
1803 static void sii8620_msc_mt_done(struct sii8620 *ctx)
1804 {
1805         struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1806
1807         if (!msg)
1808                 return;
1809
1810         msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0);
1811         ctx->mt_state = MT_STATE_DONE;
1812 }
1813
1814 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
1815 {
1816         struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1817         u8 buf[2];
1818
1819         if (!msg)
1820                 return;
1821
1822         sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
1823
1824         switch (buf[0]) {
1825         case MHL_MSC_MSG_RAPK:
1826                 msg->ret = buf[1];
1827                 ctx->mt_state = MT_STATE_DONE;
1828                 break;
1829         default:
1830                 dev_err(ctx->dev, "%s message type %d,%d not supported",
1831                         __func__, buf[0], buf[1]);
1832         }
1833 }
1834
1835 static void sii8620_irq_msc(struct sii8620 *ctx)
1836 {
1837         u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0);
1838
1839         if (stat & ~BIT_CBUS_HPD_CHG)
1840                 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG);
1841
1842         if (stat & BIT_CBUS_HPD_CHG) {
1843                 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS);
1844
1845                 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) {
1846                         sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG);
1847                 } else {
1848                         stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1849                         cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1850                 }
1851                 ctx->cbus_status = cbus_stat;
1852         }
1853
1854         if (stat & BIT_CBUS_MSC_MR_WRITE_STAT)
1855                 sii8620_msc_mr_write_stat(ctx);
1856
1857         if (stat & BIT_CBUS_MSC_MR_SET_INT)
1858                 sii8620_msc_mr_set_int(ctx);
1859
1860         if (stat & BIT_CBUS_MSC_MT_DONE)
1861                 sii8620_msc_mt_done(ctx);
1862
1863         if (stat & BIT_CBUS_MSC_MR_MSC_MSG)
1864                 sii8620_msc_mr_msc_msg(ctx);
1865 }
1866
1867 static void sii8620_irq_coc(struct sii8620 *ctx)
1868 {
1869         u8 stat = sii8620_readb(ctx, REG_COC_INTR);
1870
1871         if (stat & BIT_COC_CALIBRATION_DONE) {
1872                 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0);
1873
1874                 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE;
1875                 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) {
1876                         sii8620_write_seq_static(ctx,
1877                                 REG_COC_CTLB, 0,
1878                                 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA
1879                                               | BIT_TDM_INTR_SYNC_WAIT
1880                         );
1881                 }
1882         }
1883
1884         sii8620_write(ctx, REG_COC_INTR, stat);
1885 }
1886
1887 static void sii8620_irq_merr(struct sii8620 *ctx)
1888 {
1889         u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1);
1890
1891         sii8620_write(ctx, REG_CBUS_INT_1, stat);
1892 }
1893
1894 static void sii8620_irq_edid(struct sii8620 *ctx)
1895 {
1896         u8 stat = sii8620_readb(ctx, REG_INTR9);
1897
1898         sii8620_write(ctx, REG_INTR9, stat);
1899
1900         if (stat & BIT_INTR9_DEVCAP_DONE)
1901                 ctx->mt_state = MT_STATE_DONE;
1902 }
1903
1904 static void sii8620_scdt_high(struct sii8620 *ctx)
1905 {
1906         sii8620_write_seq_static(ctx,
1907                 REG_INTR8_MASK, BIT_CEA_NEW_AVI | BIT_CEA_NEW_VSI,
1908                 REG_TPI_SC, BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI,
1909         );
1910 }
1911
1912 static void sii8620_irq_scdt(struct sii8620 *ctx)
1913 {
1914         u8 stat = sii8620_readb(ctx, REG_INTR5);
1915
1916         if (stat & BIT_INTR_SCDT_CHANGE) {
1917                 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3);
1918
1919                 if (cstat & BIT_TMDS_CSTAT_P3_SCDT)
1920                         sii8620_scdt_high(ctx);
1921         }
1922
1923         sii8620_write(ctx, REG_INTR5, stat);
1924 }
1925
1926 static void sii8620_new_vsi(struct sii8620 *ctx)
1927 {
1928         u8 vsif[11];
1929
1930         sii8620_write(ctx, REG_RX_HDMI_CTRL2,
1931                       VAL_RX_HDMI_CTRL2_DEFVAL |
1932                       BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI);
1933         sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, vsif,
1934                          ARRAY_SIZE(vsif));
1935 }
1936
1937 static void sii8620_new_avi(struct sii8620 *ctx)
1938 {
1939         sii8620_write(ctx, REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL);
1940         sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, ctx->avif,
1941                          ARRAY_SIZE(ctx->avif));
1942 }
1943
1944 static void sii8620_irq_infr(struct sii8620 *ctx)
1945 {
1946         u8 stat = sii8620_readb(ctx, REG_INTR8)
1947                 & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI);
1948
1949         sii8620_write(ctx, REG_INTR8, stat);
1950
1951         if (stat & BIT_CEA_NEW_VSI)
1952                 sii8620_new_vsi(ctx);
1953
1954         if (stat & BIT_CEA_NEW_AVI)
1955                 sii8620_new_avi(ctx);
1956
1957         if (stat & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI))
1958                 sii8620_start_video(ctx);
1959 }
1960
1961 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret)
1962 {
1963         if (ret < 0)
1964                 return;
1965
1966         sii8620_mt_read_devcap(ctx, false);
1967 }
1968
1969 static void sii8620_irq_tdm(struct sii8620 *ctx)
1970 {
1971         u8 stat = sii8620_readb(ctx, REG_TRXINTH);
1972         u8 tdm = sii8620_readb(ctx, REG_TRXSTA2);
1973
1974         if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) {
1975                 ctx->mode = CM_ECBUS_S;
1976                 ctx->burst.rx_ack = 0;
1977                 ctx->burst.r_size = SII8620_BURST_BUF_LEN;
1978                 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
1979                 sii8620_mt_read_devcap(ctx, true);
1980                 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap);
1981         } else {
1982                 sii8620_write_seq_static(ctx,
1983                         REG_MHL_PLL_CTL2, 0,
1984                         REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN
1985                 );
1986         }
1987
1988         sii8620_write(ctx, REG_TRXINTH, stat);
1989 }
1990
1991 static void sii8620_irq_block(struct sii8620 *ctx)
1992 {
1993         u8 stat = sii8620_readb(ctx, REG_EMSCINTR);
1994
1995         if (stat & BIT_EMSCINTR_SPI_DVLD) {
1996                 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT);
1997
1998                 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE)
1999                         sii8620_burst_receive(ctx);
2000         }
2001
2002         sii8620_write(ctx, REG_EMSCINTR, stat);
2003 }
2004
2005 static void sii8620_irq_ddc(struct sii8620 *ctx)
2006 {
2007         u8 stat = sii8620_readb(ctx, REG_INTR3);
2008
2009         if (stat & BIT_DDC_CMD_DONE) {
2010                 sii8620_write(ctx, REG_INTR3_MASK, 0);
2011                 if (sii8620_is_mhl3(ctx))
2012                         sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
2013                                            MHL_INT_RC_FEAT_REQ);
2014                 else
2015                         sii8620_edid_read(ctx, 0);
2016         }
2017         sii8620_write(ctx, REG_INTR3, stat);
2018 }
2019
2020 /* endian agnostic, non-volatile version of test_bit */
2021 static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
2022 {
2023         return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE));
2024 }
2025
2026 static irqreturn_t sii8620_irq_thread(int irq, void *data)
2027 {
2028         static const struct {
2029                 int bit;
2030                 void (*handler)(struct sii8620 *ctx);
2031         } irq_vec[] = {
2032                 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
2033                 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
2034                 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
2035                 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm },
2036                 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
2037                 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
2038                 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
2039                 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
2040                 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc },
2041                 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
2042                 { BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr },
2043         };
2044         struct sii8620 *ctx = data;
2045         u8 stats[LEN_FAST_INTR_STAT];
2046         int i, ret;
2047
2048         mutex_lock(&ctx->lock);
2049
2050         sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats));
2051         for (i = 0; i < ARRAY_SIZE(irq_vec); ++i)
2052                 if (sii8620_test_bit(irq_vec[i].bit, stats))
2053                         irq_vec[i].handler(ctx);
2054
2055         sii8620_burst_rx_all(ctx);
2056         sii8620_mt_work(ctx);
2057         sii8620_burst_send(ctx);
2058
2059         ret = sii8620_clear_error(ctx);
2060         if (ret) {
2061                 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret);
2062                 sii8620_mhl_disconnected(ctx);
2063         }
2064         mutex_unlock(&ctx->lock);
2065
2066         return IRQ_HANDLED;
2067 }
2068
2069 static void sii8620_cable_in(struct sii8620 *ctx)
2070 {
2071         struct device *dev = ctx->dev;
2072         u8 ver[5];
2073         int ret;
2074
2075         ret = sii8620_hw_on(ctx);
2076         if (ret) {
2077                 dev_err(dev, "Error powering on, %d.\n", ret);
2078                 return;
2079         }
2080         sii8620_hw_reset(ctx);
2081
2082         sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver));
2083         ret = sii8620_clear_error(ctx);
2084         if (ret) {
2085                 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2086                 return;
2087         }
2088
2089         dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0],
2090                  ver[3], ver[2], ver[4]);
2091
2092         sii8620_write(ctx, REG_DPD,
2093                       BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN);
2094
2095         sii8620_xtal_set_rate(ctx);
2096         sii8620_disconnect(ctx);
2097
2098         sii8620_write_seq_static(ctx,
2099                 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG
2100                         | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734,
2101                 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM,
2102                 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN,
2103         );
2104
2105         ret = sii8620_clear_error(ctx);
2106         if (ret) {
2107                 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2108                 return;
2109         }
2110
2111         enable_irq(to_i2c_client(ctx->dev)->irq);
2112 }
2113
2114 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
2115 {
2116         return container_of(bridge, struct sii8620, bridge);
2117 }
2118
2119 static bool sii8620_mode_fixup(struct drm_bridge *bridge,
2120                                const struct drm_display_mode *mode,
2121                                struct drm_display_mode *adjusted_mode)
2122 {
2123         struct sii8620 *ctx = bridge_to_sii8620(bridge);
2124         int max_lclk;
2125         bool ret = true;
2126
2127         mutex_lock(&ctx->lock);
2128
2129         max_lclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK : MHL1_MAX_LCLK;
2130         if (max_lclk > 3 * adjusted_mode->clock) {
2131                 ctx->use_packed_pixel = 0;
2132                 goto end;
2133         }
2134         if ((ctx->devcap[MHL_DCAP_VID_LINK_MODE] & MHL_DCAP_VID_LINK_PPIXEL) &&
2135             max_lclk > 2 * adjusted_mode->clock) {
2136                 ctx->use_packed_pixel = 1;
2137                 goto end;
2138         }
2139         ret = false;
2140 end:
2141         if (ret) {
2142                 u8 vic = drm_match_cea_mode(adjusted_mode);
2143
2144                 if (!vic) {
2145                         union hdmi_infoframe frm;
2146                         u8 mhl_vic[] = { 0, 95, 94, 93, 98 };
2147
2148                         drm_hdmi_vendor_infoframe_from_display_mode(
2149                                 &frm.vendor.hdmi, adjusted_mode);
2150                         vic = frm.vendor.hdmi.vic;
2151                         if (vic >= ARRAY_SIZE(mhl_vic))
2152                                 vic = 0;
2153                         vic = mhl_vic[vic];
2154                 }
2155                 ctx->video_code = vic;
2156                 ctx->pixel_clock = adjusted_mode->clock;
2157         }
2158         mutex_unlock(&ctx->lock);
2159         return ret;
2160 }
2161
2162 static const struct drm_bridge_funcs sii8620_bridge_funcs = {
2163         .mode_fixup = sii8620_mode_fixup,
2164 };
2165
2166 static int sii8620_probe(struct i2c_client *client,
2167                          const struct i2c_device_id *id)
2168 {
2169         struct device *dev = &client->dev;
2170         struct sii8620 *ctx;
2171         int ret;
2172
2173         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2174         if (!ctx)
2175                 return -ENOMEM;
2176
2177         ctx->dev = dev;
2178         mutex_init(&ctx->lock);
2179         INIT_LIST_HEAD(&ctx->mt_queue);
2180
2181         ctx->clk_xtal = devm_clk_get(dev, "xtal");
2182         if (IS_ERR(ctx->clk_xtal)) {
2183                 dev_err(dev, "failed to get xtal clock from DT\n");
2184                 return PTR_ERR(ctx->clk_xtal);
2185         }
2186
2187         if (!client->irq) {
2188                 dev_err(dev, "no irq provided\n");
2189                 return -EINVAL;
2190         }
2191         irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
2192         ret = devm_request_threaded_irq(dev, client->irq, NULL,
2193                                         sii8620_irq_thread,
2194                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2195                                         "sii8620", ctx);
2196         if (ret < 0) {
2197                 dev_err(dev, "failed to install IRQ handler\n");
2198                 return ret;
2199         }
2200
2201         ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
2202         if (IS_ERR(ctx->gpio_reset)) {
2203                 dev_err(dev, "failed to get reset gpio from DT\n");
2204                 return PTR_ERR(ctx->gpio_reset);
2205         }
2206
2207         ctx->supplies[0].supply = "cvcc10";
2208         ctx->supplies[1].supply = "iovcc18";
2209         ret = devm_regulator_bulk_get(dev, 2, ctx->supplies);
2210         if (ret)
2211                 return ret;
2212
2213         i2c_set_clientdata(client, ctx);
2214
2215         ctx->bridge.funcs = &sii8620_bridge_funcs;
2216         ctx->bridge.of_node = dev->of_node;
2217         drm_bridge_add(&ctx->bridge);
2218
2219         sii8620_cable_in(ctx);
2220
2221         return 0;
2222 }
2223
2224 static int sii8620_remove(struct i2c_client *client)
2225 {
2226         struct sii8620 *ctx = i2c_get_clientdata(client);
2227
2228         disable_irq(to_i2c_client(ctx->dev)->irq);
2229         drm_bridge_remove(&ctx->bridge);
2230         sii8620_hw_off(ctx);
2231
2232         return 0;
2233 }
2234
2235 static const struct of_device_id sii8620_dt_match[] = {
2236         { .compatible = "sil,sii8620" },
2237         { },
2238 };
2239 MODULE_DEVICE_TABLE(of, sii8620_dt_match);
2240
2241 static const struct i2c_device_id sii8620_id[] = {
2242         { "sii8620", 0 },
2243         { },
2244 };
2245
2246 MODULE_DEVICE_TABLE(i2c, sii8620_id);
2247 static struct i2c_driver sii8620_driver = {
2248         .driver = {
2249                 .name   = "sii8620",
2250                 .of_match_table = of_match_ptr(sii8620_dt_match),
2251         },
2252         .probe          = sii8620_probe,
2253         .remove         = sii8620_remove,
2254         .id_table = sii8620_id,
2255 };
2256
2257 module_i2c_driver(sii8620_driver);
2258 MODULE_LICENSE("GPL v2");