drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/irq.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <drm/drm_of.h>
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_encoder_slave.h>
  31 #include <drm/bridge/dw_hdmi.h>
  32
  33 #include <uapi/linux/media-bus-format.h>
  34 #include <uapi/linux/videodev2.h>
  35
  36 #include "dw-hdmi.h"
  37 #include "dw-hdmi-audio.h"
  38 #include "dw-hdmi-cec.h"
  39
  40 #include <media/cec-notifier.h>
  41
  42 #define DDC_CI_ADDR             0x37
  43 #define DDC_SEGMENT_ADDR        0x30
  44
  45 #define HDMI_EDID_LEN           512
  46
  47 enum hdmi_datamap {
  48         RGB444_8B = 0x01,
  49         RGB444_10B = 0x03,
  50         RGB444_12B = 0x05,
  51         RGB444_16B = 0x07,
  52         YCbCr444_8B = 0x09,
  53         YCbCr444_10B = 0x0B,
  54         YCbCr444_12B = 0x0D,
  55         YCbCr444_16B = 0x0F,
  56         YCbCr422_8B = 0x16,
  57         YCbCr422_10B = 0x14,
  58         YCbCr422_12B = 0x12,
  59 };
  60
  61 static const u16 csc_coeff_default[3][4] = {
  62         { 0x2000, 0x0000, 0x0000, 0x0000 },
  63         { 0x0000, 0x2000, 0x0000, 0x0000 },
  64         { 0x0000, 0x0000, 0x2000, 0x0000 }
  65 };
  66
  67 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  68         { 0x2000, 0x6926, 0x74fd, 0x010e },
  69         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  70         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  71 };
  72
  73 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  74         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  75         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  76         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  77 };
  78
  79 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  80         { 0x2591, 0x1322, 0x074b, 0x0000 },
  81         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  82         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  83 };
  84
  85 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  86         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  87         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  88         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  89 };
  90
  91 struct hdmi_vmode {
  92         bool mdataenablepolarity;
  93
  94         unsigned int mpixelclock;
  95         unsigned int mpixelrepetitioninput;
  96         unsigned int mpixelrepetitionoutput;
  97 };
  98
  99 struct hdmi_data_info {
 100         unsigned int enc_in_bus_format;
 101         unsigned int enc_out_bus_format;
 102         unsigned int enc_in_encoding;
 103         unsigned int enc_out_encoding;
 104         unsigned int pix_repet_factor;
 105         unsigned int hdcp_enable;
 106         struct hdmi_vmode video_mode;
 107 };
 108
 109 struct dw_hdmi_i2c {
 110         struct i2c_adapter      adap;
 111
 112         struct mutex            lock;   /* used to serialize data transfers */
 113         struct completion       cmp;
 114         u8                      stat;
 115
 116         u8                      slave_reg;
 117         bool                    is_regaddr;
 118         bool                    is_segment;
 119 };
 120
 121 struct dw_hdmi_phy_data {
 122         enum dw_hdmi_phy_type type;
 123         const char *name;
 124         unsigned int gen;
 125         bool has_svsret;
 126         int (*configure)(struct dw_hdmi *hdmi,
 127                          const struct dw_hdmi_plat_data *pdata,
 128                          unsigned long mpixelclock);
 129 };
 130
 131 struct dw_hdmi {
 132         struct drm_connector connector;
 133         struct drm_bridge bridge;
 134
 135         unsigned int version;
 136
 137         struct platform_device *audio;
 138         struct platform_device *cec;
 139         struct device *dev;
 140         struct clk *isfr_clk;
 141         struct clk *iahb_clk;
 142         struct clk *cec_clk;
 143         struct dw_hdmi_i2c *i2c;
 144
 145         struct hdmi_data_info hdmi_data;
 146         const struct dw_hdmi_plat_data *plat_data;
 147
 148         int vic;
 149
 150         u8 edid[HDMI_EDID_LEN];
 151
 152         struct {
 153                 const struct dw_hdmi_phy_ops *ops;
 154                 const char *name;
 155                 void *data;
 156                 bool enabled;
 157         } phy;
 158
 159         struct drm_display_mode previous_mode;
 160
 161         struct i2c_adapter *ddc;
 162         void __iomem *regs;
 163         bool sink_is_hdmi;
 164         bool sink_has_audio;
 165
 166         struct mutex mutex;             /* for state below and previous_mode */
 167         enum drm_connector_force force; /* mutex-protected force state */
 168         bool disabled;                  /* DRM has disabled our bridge */
 169         bool bridge_is_on;              /* indicates the bridge is on */
 170         bool rxsense;                   /* rxsense state */
 171         u8 phy_mask;                    /* desired phy int mask settings */
 172         u8 mc_clkdis;                   /* clock disable register */
 173
 174         spinlock_t audio_lock;
 175         struct mutex audio_mutex;
 176         unsigned int sample_rate;
 177         unsigned int audio_cts;
 178         unsigned int audio_n;
 179         bool audio_enable;
 180
 181         unsigned int reg_shift;
 182         struct regmap *regm;
 183         void (*enable_audio)(struct dw_hdmi *hdmi);
 184         void (*disable_audio)(struct dw_hdmi *hdmi);
 185
 186         struct cec_notifier *cec_notifier;
 187 };
 188
 189 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 190         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 191          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 192
 193 #define HDMI_PHY_RX_SENSE \
 194         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 195          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 196
 197 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 198 {
 199         regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
 200 }
 201
 202 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 203 {
 204         unsigned int val = 0;
 205
 206         regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
 207
 208         return val;
 209 }
 210
 211 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 212 {
 213         regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
 214 }
 215
 216 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 217                              u8 shift, u8 mask)
 218 {
 219         hdmi_modb(hdmi, data << shift, mask, reg);
 220 }
 221
 222 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 223 {
 224         /* Software reset */
 225         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 226
 227         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
 228         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 229
 230         /* Set done, not acknowledged and arbitration interrupt polarities */
 231         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 232         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 233                     HDMI_I2CM_CTLINT);
 234
 235         /* Clear DONE and ERROR interrupts */
 236         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 237                     HDMI_IH_I2CM_STAT0);
 238
 239         /* Mute DONE and ERROR interrupts */
 240         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 241                     HDMI_IH_MUTE_I2CM_STAT0);
 242 }
 243
 244 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 245                             unsigned char *buf, unsigned int length)
 246 {
 247         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 248         int stat;
 249
 250         if (!i2c->is_regaddr) {
 251                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 252                 i2c->slave_reg = 0x00;
 253                 i2c->is_regaddr = true;
 254         }
 255
 256         while (length--) {
 257                 reinit_completion(&i2c->cmp);
 258
 259                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 260                 if (i2c->is_segment)
 261                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 262                                     HDMI_I2CM_OPERATION);
 263                 else
 264                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 265                                     HDMI_I2CM_OPERATION);
 266
 267                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 268                 if (!stat)
 269                         return -EAGAIN;
 270
 271                 /* Check for error condition on the bus */
 272                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 273                         return -EIO;
 274
 275                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 276         }
 277         i2c->is_segment = false;
 278
 279         return 0;
 280 }
 281
 282 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 283                              unsigned char *buf, unsigned int length)
 284 {
 285         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 286         int stat;
 287
 288         if (!i2c->is_regaddr) {
 289                 /* Use the first write byte as register address */
 290                 i2c->slave_reg = buf[0];
 291                 length--;
 292                 buf++;
 293                 i2c->is_regaddr = true;
 294         }
 295
 296         while (length--) {
 297                 reinit_completion(&i2c->cmp);
 298
 299                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 300                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 301                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 302                             HDMI_I2CM_OPERATION);
 303
 304                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 305                 if (!stat)
 306                         return -EAGAIN;
 307
 308                 /* Check for error condition on the bus */
 309                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 310                         return -EIO;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 317                             struct i2c_msg *msgs, int num)
 318 {
 319         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 320         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 321         u8 addr = msgs[0].addr;
 322         int i, ret = 0;
 323
 324         if (addr == DDC_CI_ADDR)
 325                 /*
 326                  * The internal I2C controller does not support the multi-byte
 327                  * read and write operations needed for DDC/CI.
 328                  * TOFIX: Blacklist the DDC/CI address until we filter out
 329                  * unsupported I2C operations.
 330                  */
 331                 return -EOPNOTSUPP;
 332
 333         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 334
 335         for (i = 0; i < num; i++) {
 336                 if (msgs[i].len == 0) {
 337                         dev_dbg(hdmi->dev,
 338                                 "unsupported transfer %d/%d, no data\n",
 339                                 i + 1, num);
 340                         return -EOPNOTSUPP;
 341                 }
 342         }
 343
 344         mutex_lock(&i2c->lock);
 345
 346         /* Unmute DONE and ERROR interrupts */
 347         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 348
 349         /* Set slave device address taken from the first I2C message */
 350         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 351
 352         /* Set slave device register address on transfer */
 353         i2c->is_regaddr = false;
 354
 355         /* Set segment pointer for I2C extended read mode operation */
 356         i2c->is_segment = false;
 357
 358         for (i = 0; i < num; i++) {
 359                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 360                         i + 1, num, msgs[i].len, msgs[i].flags);
 361                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 362                         i2c->is_segment = true;
 363                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 364                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 365                 } else {
 366                         if (msgs[i].flags & I2C_M_RD)
 367                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 368                                                        msgs[i].len);
 369                         else
 370                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 371                                                         msgs[i].len);
 372                 }
 373                 if (ret < 0)
 374                         break;
 375         }
 376
 377         if (!ret)
 378                 ret = num;
 379
 380         /* Mute DONE and ERROR interrupts */
 381         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 382                     HDMI_IH_MUTE_I2CM_STAT0);
 383
 384         mutex_unlock(&i2c->lock);
 385
 386         return ret;
 387 }
 388
 389 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 390 {
 391         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 392 }
 393
 394 static const struct i2c_algorithm dw_hdmi_algorithm = {
 395         .master_xfer    = dw_hdmi_i2c_xfer,
 396         .functionality  = dw_hdmi_i2c_func,
 397 };
 398
 399 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 400 {
 401         struct i2c_adapter *adap;
 402         struct dw_hdmi_i2c *i2c;
 403         int ret;
 404
 405         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 406         if (!i2c)
 407                 return ERR_PTR(-ENOMEM);
 408
 409         mutex_init(&i2c->lock);
 410         init_completion(&i2c->cmp);
 411
 412         adap = &i2c->adap;
 413         adap->class = I2C_CLASS_DDC;
 414         adap->owner = THIS_MODULE;
 415         adap->dev.parent = hdmi->dev;
 416         adap->algo = &dw_hdmi_algorithm;
 417         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 418         i2c_set_adapdata(adap, hdmi);
 419
 420         ret = i2c_add_adapter(adap);
 421         if (ret) {
 422                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 423                 devm_kfree(hdmi->dev, i2c);
 424                 return ERR_PTR(ret);
 425         }
 426
 427         hdmi->i2c = i2c;
 428
 429         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 430
 431         return adap;
 432 }
 433
 434 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 435                            unsigned int n)
 436 {
 437         /* Must be set/cleared first */
 438         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 439
 440         /* nshift factor = 0 */
 441         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 442
 443         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 444                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 445         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 446         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 447
 448         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 449         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 450         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 451 }
 452
 453 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 454 {
 455         unsigned int n = (128 * freq) / 1000;
 456         unsigned int mult = 1;
 457
 458         while (freq > 48000) {
 459                 mult *= 2;
 460                 freq /= 2;
 461         }
 462
 463         switch (freq) {
 464         case 32000:
 465                 if (pixel_clk == 25175000)
 466                         n = 4576;
 467                 else if (pixel_clk == 27027000)
 468                         n = 4096;
 469                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 470                         n = 11648;
 471                 else
 472                         n = 4096;
 473                 n *= mult;
 474                 break;
 475
 476         case 44100:
 477                 if (pixel_clk == 25175000)
 478                         n = 7007;
 479                 else if (pixel_clk == 74176000)
 480                         n = 17836;
 481                 else if (pixel_clk == 148352000)
 482                         n = 8918;
 483                 else
 484                         n = 6272;
 485                 n *= mult;
 486                 break;
 487
 488         case 48000:
 489                 if (pixel_clk == 25175000)
 490                         n = 6864;
 491                 else if (pixel_clk == 27027000)
 492                         n = 6144;
 493                 else if (pixel_clk == 74176000)
 494                         n = 11648;
 495                 else if (pixel_clk == 148352000)
 496                         n = 5824;
 497                 else
 498                         n = 6144;
 499                 n *= mult;
 500                 break;
 501
 502         default:
 503                 break;
 504         }
 505
 506         return n;
 507 }
 508
 509 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 510         unsigned long pixel_clk, unsigned int sample_rate)
 511 {
 512         unsigned long ftdms = pixel_clk;
 513         unsigned int n, cts;
 514         u64 tmp;
 515
 516         n = hdmi_compute_n(sample_rate, pixel_clk);
 517
 518         /*
 519          * Compute the CTS value from the N value.  Note that CTS and N
 520          * can be up to 20 bits in total, so we need 64-bit math.  Also
 521          * note that our TDMS clock is not fully accurate; it is accurate
 522          * to kHz.  This can introduce an unnecessary remainder in the
 523          * calculation below, so we don't try to warn about that.
 524          */
 525         tmp = (u64)ftdms * n;
 526         do_div(tmp, 128 * sample_rate);
 527         cts = tmp;
 528
 529         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 530                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 531                 n, cts);
 532
 533         spin_lock_irq(&hdmi->audio_lock);
 534         hdmi->audio_n = n;
 535         hdmi->audio_cts = cts;
 536         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 537         spin_unlock_irq(&hdmi->audio_lock);
 538 }
 539
 540 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 541 {
 542         mutex_lock(&hdmi->audio_mutex);
 543         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 544         mutex_unlock(&hdmi->audio_mutex);
 545 }
 546
 547 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 548 {
 549         mutex_lock(&hdmi->audio_mutex);
 550         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 551                                  hdmi->sample_rate);
 552         mutex_unlock(&hdmi->audio_mutex);
 553 }
 554
 555 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 556 {
 557         mutex_lock(&hdmi->audio_mutex);
 558         hdmi->sample_rate = rate;
 559         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 560                                  hdmi->sample_rate);
 561         mutex_unlock(&hdmi->audio_mutex);
 562 }
 563 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 564
 565 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
 566 {
 567         if (enable)
 568                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 569         else
 570                 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 571         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
 572 }
 573
 574 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 575 {
 576         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 577 }
 578
 579 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
 580 {
 581         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 582 }
 583
 584 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
 585 {
 586         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 587         hdmi_enable_audio_clk(hdmi, true);
 588 }
 589
 590 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
 591 {
 592         hdmi_enable_audio_clk(hdmi, false);
 593 }
 594
 595 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 596 {
 597         unsigned long flags;
 598
 599         spin_lock_irqsave(&hdmi->audio_lock, flags);
 600         hdmi->audio_enable = true;
 601         if (hdmi->enable_audio)
 602                 hdmi->enable_audio(hdmi);
 603         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 604 }
 605 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 606
 607 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 608 {
 609         unsigned long flags;
 610
 611         spin_lock_irqsave(&hdmi->audio_lock, flags);
 612         hdmi->audio_enable = false;
 613         if (hdmi->disable_audio)
 614                 hdmi->disable_audio(hdmi);
 615         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 616 }
 617 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 618
 619 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
 620 {
 621         switch (bus_format) {
 622         case MEDIA_BUS_FMT_RGB888_1X24:
 623         case MEDIA_BUS_FMT_RGB101010_1X30:
 624         case MEDIA_BUS_FMT_RGB121212_1X36:
 625         case MEDIA_BUS_FMT_RGB161616_1X48:
 626                 return true;
 627
 628         default:
 629                 return false;
 630         }
 631 }
 632
 633 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
 634 {
 635         switch (bus_format) {
 636         case MEDIA_BUS_FMT_YUV8_1X24:
 637         case MEDIA_BUS_FMT_YUV10_1X30:
 638         case MEDIA_BUS_FMT_YUV12_1X36:
 639         case MEDIA_BUS_FMT_YUV16_1X48:
 640                 return true;
 641
 642         default:
 643                 return false;
 644         }
 645 }
 646
 647 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
 648 {
 649         switch (bus_format) {
 650         case MEDIA_BUS_FMT_UYVY8_1X16:
 651         case MEDIA_BUS_FMT_UYVY10_1X20:
 652         case MEDIA_BUS_FMT_UYVY12_1X24:
 653                 return true;
 654
 655         default:
 656                 return false;
 657         }
 658 }
 659
 660 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
 661 {
 662         switch (bus_format) {
 663         case MEDIA_BUS_FMT_RGB888_1X24:
 664         case MEDIA_BUS_FMT_YUV8_1X24:
 665         case MEDIA_BUS_FMT_UYVY8_1X16:
 666         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 667                 return 8;
 668
 669         case MEDIA_BUS_FMT_RGB101010_1X30:
 670         case MEDIA_BUS_FMT_YUV10_1X30:
 671         case MEDIA_BUS_FMT_UYVY10_1X20:
 672         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 673                 return 10;
 674
 675         case MEDIA_BUS_FMT_RGB121212_1X36:
 676         case MEDIA_BUS_FMT_YUV12_1X36:
 677         case MEDIA_BUS_FMT_UYVY12_1X24:
 678         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 679                 return 12;
 680
 681         case MEDIA_BUS_FMT_RGB161616_1X48:
 682         case MEDIA_BUS_FMT_YUV16_1X48:
 683         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 684                 return 16;
 685
 686         default:
 687                 return 0;
 688         }
 689 }
 690
 691 /*
 692  * this submodule is responsible for the video data synchronization.
 693  * for example, for RGB 4:4:4 input, the data map is defined as
 694  *                      pin{47~40} <==> R[7:0]
 695  *                      pin{31~24} <==> G[7:0]
 696  *                      pin{15~8}  <==> B[7:0]
 697  */
 698 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 699 {
 700         int color_format = 0;
 701         u8 val;
 702
 703         switch (hdmi->hdmi_data.enc_in_bus_format) {
 704         case MEDIA_BUS_FMT_RGB888_1X24:
 705                 color_format = 0x01;
 706                 break;
 707         case MEDIA_BUS_FMT_RGB101010_1X30:
 708                 color_format = 0x03;
 709                 break;
 710         case MEDIA_BUS_FMT_RGB121212_1X36:
 711                 color_format = 0x05;
 712                 break;
 713         case MEDIA_BUS_FMT_RGB161616_1X48:
 714                 color_format = 0x07;
 715                 break;
 716
 717         case MEDIA_BUS_FMT_YUV8_1X24:
 718         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 719                 color_format = 0x09;
 720                 break;
 721         case MEDIA_BUS_FMT_YUV10_1X30:
 722         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 723                 color_format = 0x0B;
 724                 break;
 725         case MEDIA_BUS_FMT_YUV12_1X36:
 726         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 727                 color_format = 0x0D;
 728                 break;
 729         case MEDIA_BUS_FMT_YUV16_1X48:
 730         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 731                 color_format = 0x0F;
 732                 break;
 733
 734         case MEDIA_BUS_FMT_UYVY8_1X16:
 735                 color_format = 0x16;
 736                 break;
 737         case MEDIA_BUS_FMT_UYVY10_1X20:
 738                 color_format = 0x14;
 739                 break;
 740         case MEDIA_BUS_FMT_UYVY12_1X24:
 741                 color_format = 0x12;
 742                 break;
 743
 744         default:
 745                 return;
 746         }
 747
 748         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 749                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 750                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 751         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 752
 753         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 754         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 755                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 756                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 757         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 758         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 759         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 760         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 761         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 762         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 763         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 764 }
 765
 766 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 767 {
 768         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
 769 }
 770
 771 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 772 {
 773         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
 774                 return 0;
 775
 776         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
 777             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
 778                 return 1;
 779
 780         return 0;
 781 }
 782
 783 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 784 {
 785         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
 786                 return 0;
 787
 788         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 789             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
 790                 return 1;
 791
 792         return 0;
 793 }
 794
 795 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 796 {
 797         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 798         unsigned i;
 799         u32 csc_scale = 1;
 800
 801         if (is_color_space_conversion(hdmi)) {
 802                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
 803                         if (hdmi->hdmi_data.enc_out_encoding ==
 804                                                 V4L2_YCBCR_ENC_601)
 805                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 806                         else
 807                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 808                 } else if (hdmi_bus_fmt_is_rgb(
 809                                         hdmi->hdmi_data.enc_in_bus_format)) {
 810                         if (hdmi->hdmi_data.enc_out_encoding ==
 811                                                 V4L2_YCBCR_ENC_601)
 812                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 813                         else
 814                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 815                         csc_scale = 0;
 816                 }
 817         }
 818
 819         /* The CSC registers are sequential, alternating MSB then LSB */
 820         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 821                 u16 coeff_a = (*csc_coeff)[0][i];
 822                 u16 coeff_b = (*csc_coeff)[1][i];
 823                 u16 coeff_c = (*csc_coeff)[2][i];
 824
 825                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 826                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 827                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 828                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 829                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 830                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 831         }
 832
 833         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 834                   HDMI_CSC_SCALE);
 835 }
 836
 837 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 838 {
 839         int color_depth = 0;
 840         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 841         int decimation = 0;
 842
 843         /* YCC422 interpolation to 444 mode */
 844         if (is_color_space_interpolation(hdmi))
 845                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 846         else if (is_color_space_decimation(hdmi))
 847                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 848
 849         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
 850         case 8:
 851                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 852                 break;
 853         case 10:
 854                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 855                 break;
 856         case 12:
 857                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 858                 break;
 859         case 16:
 860                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 861                 break;
 862
 863         default:
 864                 return;
 865         }
 866
 867         /* Configure the CSC registers */
 868         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 869         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 870                   HDMI_CSC_SCALE);
 871
 872         dw_hdmi_update_csc_coeffs(hdmi);
 873 }
 874
 875 /*
 876  * HDMI video packetizer is used to packetize the data.
 877  * for example, if input is YCC422 mode or repeater is used,
 878  * data should be repacked this module can be bypassed.
 879  */
 880 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 881 {
 882         unsigned int color_depth = 0;
 883         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 884         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 885         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 886         u8 val, vp_conf;
 887
 888         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 889             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
 890                 switch (hdmi_bus_fmt_color_depth(
 891                                         hdmi->hdmi_data.enc_out_bus_format)) {
 892                 case 8:
 893                         color_depth = 4;
 894                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 895                         break;
 896                 case 10:
 897                         color_depth = 5;
 898                         break;
 899                 case 12:
 900                         color_depth = 6;
 901                         break;
 902                 case 16:
 903                         color_depth = 7;
 904                         break;
 905                 default:
 906                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 907                 }
 908         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
 909                 switch (hdmi_bus_fmt_color_depth(
 910                                         hdmi->hdmi_data.enc_out_bus_format)) {
 911                 case 0:
 912                 case 8:
 913                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 914                         break;
 915                 case 10:
 916                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 917                         break;
 918                 case 12:
 919                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 920                         break;
 921
 922                 default:
 923                         return;
 924                 }
 925                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 926         } else {
 927                 return;
 928         }
 929
 930         /* set the packetizer registers */
 931         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 932                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 933                 ((hdmi_data->pix_repet_factor <<
 934                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 935                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 936         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 937
 938         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 939                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 940
 941         /* Data from pixel repeater block */
 942         if (hdmi_data->pix_repet_factor > 1) {
 943                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 944                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 945         } else { /* data from packetizer block */
 946                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 947                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 948         }
 949
 950         hdmi_modb(hdmi, vp_conf,
 951                   HDMI_VP_CONF_PR_EN_MASK |
 952                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 953
 954         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 955                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 956
 957         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 958
 959         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 960                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 961                           HDMI_VP_CONF_PP_EN_ENABLE |
 962                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 963         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 964                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 965                           HDMI_VP_CONF_PP_EN_DISABLE |
 966                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 967         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 968                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 969                           HDMI_VP_CONF_PP_EN_DISABLE |
 970                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 971         } else {
 972                 return;
 973         }
 974
 975         hdmi_modb(hdmi, vp_conf,
 976                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 977                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 978
 979         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 980                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 981                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 982                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 983
 984         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 985                   HDMI_VP_CONF);
 986 }
 987
 988 /* -----------------------------------------------------------------------------
 989  * Synopsys PHY Handling
 990  */
 991
 992 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 993                                        unsigned char bit)
 994 {
 995         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 996                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 997 }
 998
 999 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1000 {
1001         u32 val;
1002
1003         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1004                 if (msec-- == 0)
1005                         return false;
1006                 udelay(1000);
1007         }
1008         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1009
1010         return true;
1011 }
1012
1013 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1014                            unsigned char addr)
1015 {
1016         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1017         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1018         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1019                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1020         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1021                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1022         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1023                     HDMI_PHY_I2CM_OPERATION_ADDR);
1024         hdmi_phy_wait_i2c_done(hdmi, 1000);
1025 }
1026 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1027
1028 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1029 {
1030         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1031                          HDMI_PHY_CONF0_PDZ_OFFSET,
1032                          HDMI_PHY_CONF0_PDZ_MASK);
1033 }
1034
1035 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1036 {
1037         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1038                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1039                          HDMI_PHY_CONF0_ENTMDS_MASK);
1040 }
1041
1042 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1043 {
1044         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1045                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1046                          HDMI_PHY_CONF0_SVSRET_MASK);
1047 }
1048
1049 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1050 {
1051         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1052                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1053                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1054 }
1055 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1056
1057 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1058 {
1059         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1060                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1061                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1062 }
1063 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1064
1065 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1066 {
1067         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1068                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1069                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1070 }
1071
1072 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1073 {
1074         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1075                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1076                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1077 }
1078
1079 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1080 {
1081         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1082         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1083         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1084 }
1085 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1086
1087 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1088 {
1089         hdmi_phy_test_clear(hdmi, 1);
1090         hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1091         hdmi_phy_test_clear(hdmi, 0);
1092 }
1093 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1094
1095 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1096 {
1097         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1098         unsigned int i;
1099         u16 val;
1100
1101         if (phy->gen == 1) {
1102                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1103                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1104                 return;
1105         }
1106
1107         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1108
1109         /*
1110          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1111          * to low power mode.
1112          */
1113         for (i = 0; i < 5; ++i) {
1114                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1115                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1116                         break;
1117
1118                 usleep_range(1000, 2000);
1119         }
1120
1121         if (val & HDMI_PHY_TX_PHY_LOCK)
1122                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1123         else
1124                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1125
1126         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1127 }
1128
1129 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1130 {
1131         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1132         unsigned int i;
1133         u8 val;
1134
1135         if (phy->gen == 1) {
1136                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1137
1138                 /* Toggle TMDS enable. */
1139                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1140                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1141                 return 0;
1142         }
1143
1144         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1145         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1146
1147         /* Wait for PHY PLL lock */
1148         for (i = 0; i < 5; ++i) {
1149                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1150                 if (val)
1151                         break;
1152
1153                 usleep_range(1000, 2000);
1154         }
1155
1156         if (!val) {
1157                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1158                 return -ETIMEDOUT;
1159         }
1160
1161         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1162         return 0;
1163 }
1164
1165 /*
1166  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1167  * information the DWC MHL PHY has the same register layout and is thus also
1168  * supported by this function.
1169  */
1170 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1171                 const struct dw_hdmi_plat_data *pdata,
1172                 unsigned long mpixelclock)
1173 {
1174         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1175         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1176         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1177
1178         /* PLL/MPLL Cfg - always match on final entry */
1179         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1180                 if (mpixelclock <= mpll_config->mpixelclock)
1181                         break;
1182
1183         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1184                 if (mpixelclock <= curr_ctrl->mpixelclock)
1185                         break;
1186
1187         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1188                 if (mpixelclock <= phy_config->mpixelclock)
1189                         break;
1190
1191         if (mpll_config->mpixelclock == ~0UL ||
1192             curr_ctrl->mpixelclock == ~0UL ||
1193             phy_config->mpixelclock == ~0UL)
1194                 return -EINVAL;
1195
1196         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1197                               HDMI_3D_TX_PHY_CPCE_CTRL);
1198         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1199                               HDMI_3D_TX_PHY_GMPCTRL);
1200         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1201                               HDMI_3D_TX_PHY_CURRCTRL);
1202
1203         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1204         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1205                               HDMI_3D_TX_PHY_MSM_CTRL);
1206
1207         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1208         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1209                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1210         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1211                               HDMI_3D_TX_PHY_VLEVCTRL);
1212
1213         /* Override and disable clock termination. */
1214         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1215                               HDMI_3D_TX_PHY_CKCALCTRL);
1216
1217         return 0;
1218 }
1219
1220 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1221 {
1222         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1223         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1224         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1225         int ret;
1226
1227         dw_hdmi_phy_power_off(hdmi);
1228
1229         /* Leave low power consumption mode by asserting SVSRET. */
1230         if (phy->has_svsret)
1231                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1232
1233         dw_hdmi_phy_reset(hdmi);
1234
1235         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1236
1237         dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1238
1239         /* Write to the PHY as configured by the platform */
1240         if (pdata->configure_phy)
1241                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1242         else
1243                 ret = phy->configure(hdmi, pdata, mpixelclock);
1244         if (ret) {
1245                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1246                         mpixelclock);
1247                 return ret;
1248         }
1249
1250         return dw_hdmi_phy_power_on(hdmi);
1251 }
1252
1253 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1254                             struct drm_display_mode *mode)
1255 {
1256         int i, ret;
1257
1258         /* HDMI Phy spec says to do the phy initialization sequence twice */
1259         for (i = 0; i < 2; i++) {
1260                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1261                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1262
1263                 ret = hdmi_phy_configure(hdmi);
1264                 if (ret)
1265                         return ret;
1266         }
1267
1268         return 0;
1269 }
1270
1271 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1272 {
1273         dw_hdmi_phy_power_off(hdmi);
1274 }
1275
1276 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1277                                                void *data)
1278 {
1279         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1280                 connector_status_connected : connector_status_disconnected;
1281 }
1282 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1283
1284 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1285                             bool force, bool disabled, bool rxsense)
1286 {
1287         u8 old_mask = hdmi->phy_mask;
1288
1289         if (force || disabled || !rxsense)
1290                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1291         else
1292                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1293
1294         if (old_mask != hdmi->phy_mask)
1295                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1296 }
1297 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1298
1299 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1300 {
1301         /*
1302          * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1303          * any pending interrupt.
1304          */
1305         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1306         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1307                     HDMI_IH_PHY_STAT0);
1308
1309         /* Enable cable hot plug irq. */
1310         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1311
1312         /* Clear and unmute interrupts. */
1313         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1314                     HDMI_IH_PHY_STAT0);
1315         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1316                     HDMI_IH_MUTE_PHY_STAT0);
1317 }
1318 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1319
1320 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1321         .init = dw_hdmi_phy_init,
1322         .disable = dw_hdmi_phy_disable,
1323         .read_hpd = dw_hdmi_phy_read_hpd,
1324         .update_hpd = dw_hdmi_phy_update_hpd,
1325         .setup_hpd = dw_hdmi_phy_setup_hpd,
1326 };
1327
1328 /* -----------------------------------------------------------------------------
1329  * HDMI TX Setup
1330  */
1331
1332 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1333 {
1334         u8 de;
1335
1336         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1337                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1338         else
1339                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1340
1341         /* disable rx detect */
1342         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1343                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1344
1345         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1346
1347         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1348                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1349 }
1350
1351 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1352 {
1353         struct hdmi_avi_infoframe frame;
1354         u8 val;
1355
1356         /* Initialise info frame from DRM mode */
1357         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1358
1359         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1360                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1361         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1362                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1363         else
1364                 frame.colorspace = HDMI_COLORSPACE_RGB;
1365
1366         /* Set up colorimetry */
1367         if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1368                 switch (hdmi->hdmi_data.enc_out_encoding) {
1369                 case V4L2_YCBCR_ENC_601:
1370                         if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1371                                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1372                         else
1373                                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1374                         frame.extended_colorimetry =
1375                                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1376                         break;
1377                 case V4L2_YCBCR_ENC_709:
1378                         if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1379                                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1380                         else
1381                                 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1382                         frame.extended_colorimetry =
1383                                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1384                         break;
1385                 default: /* Carries no data */
1386                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1387                         frame.extended_colorimetry =
1388                                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1389                         break;
1390                 }
1391         } else {
1392                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1393                 frame.extended_colorimetry =
1394                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1395         }
1396
1397         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1398
1399         /*
1400          * The Designware IP uses a different byte format from standard
1401          * AVI info frames, though generally the bits are in the correct
1402          * bytes.
1403          */
1404
1405         /*
1406          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1407          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1408          * bit 6 rather than 4.
1409          */
1410         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1411         if (frame.active_aspect & 15)
1412                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1413         if (frame.top_bar || frame.bottom_bar)
1414                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1415         if (frame.left_bar || frame.right_bar)
1416                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1417         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1418
1419         /* AVI data byte 2 differences: none */
1420         val = ((frame.colorimetry & 0x3) << 6) |
1421               ((frame.picture_aspect & 0x3) << 4) |
1422               (frame.active_aspect & 0xf);
1423         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1424
1425         /* AVI data byte 3 differences: none */
1426         val = ((frame.extended_colorimetry & 0x7) << 4) |
1427               ((frame.quantization_range & 0x3) << 2) |
1428               (frame.nups & 0x3);
1429         if (frame.itc)
1430                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1431         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1432
1433         /* AVI data byte 4 differences: none */
1434         val = frame.video_code & 0x7f;
1435         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1436
1437         /* AVI Data Byte 5- set up input and output pixel repetition */
1438         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1439                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1440                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1441                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1442                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1443                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1444         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1445
1446         /*
1447          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1448          * ycc range in bits 2,3 rather than 6,7
1449          */
1450         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1451               (frame.content_type & 0x3);
1452         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1453
1454         /* AVI Data Bytes 6-13 */
1455         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1456         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1457         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1458         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1459         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1460         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1461         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1462         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1463 }
1464
1465 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1466                                                  struct drm_display_mode *mode)
1467 {
1468         struct hdmi_vendor_infoframe frame;
1469         u8 buffer[10];
1470         ssize_t err;
1471
1472         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1473                                                           &hdmi->connector,
1474                                                           mode);
1475         if (err < 0)
1476                 /*
1477                  * Going into that statement does not means vendor infoframe
1478                  * fails. It just informed us that vendor infoframe is not
1479                  * needed for the selected mode. Only 4k or stereoscopic 3D
1480                  * mode requires vendor infoframe. So just simply return.
1481                  */
1482                 return;
1483
1484         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1485         if (err < 0) {
1486                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1487                         err);
1488                 return;
1489         }
1490         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1491                         HDMI_FC_DATAUTO0_VSD_MASK);
1492
1493         /* Set the length of HDMI vendor specific InfoFrame payload */
1494         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1495
1496         /* Set 24bit IEEE Registration Identifier */
1497         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1498         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1499         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1500
1501         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1502         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1503         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1504
1505         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1506                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1507
1508         /* Packet frame interpolation */
1509         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1510
1511         /* Auto packets per frame and line spacing */
1512         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1513
1514         /* Configures the Frame Composer On RDRB mode */
1515         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1516                         HDMI_FC_DATAUTO0_VSD_MASK);
1517 }
1518
1519 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1520                              const struct drm_display_mode *mode)
1521 {
1522         u8 inv_val;
1523         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1524         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1525         unsigned int vdisplay;
1526
1527         vmode->mpixelclock = mode->clock * 1000;
1528
1529         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1530
1531         /* Set up HDMI_FC_INVIDCONF */
1532         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1533                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1534                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1535
1536         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1537                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1538                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1539
1540         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1541                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1542                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1543
1544         inv_val |= (vmode->mdataenablepolarity ?
1545                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1546                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1547
1548         if (hdmi->vic == 39)
1549                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1550         else
1551                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1552                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1553                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1554
1555         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1556                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1557                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1558
1559         inv_val |= hdmi->sink_is_hdmi ?
1560                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1561                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1562
1563         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1564
1565         vdisplay = mode->vdisplay;
1566         vblank = mode->vtotal - mode->vdisplay;
1567         v_de_vs = mode->vsync_start - mode->vdisplay;
1568         vsync_len = mode->vsync_end - mode->vsync_start;
1569
1570         /*
1571          * When we're setting an interlaced mode, we need
1572          * to adjust the vertical timing to suit.
1573          */
1574         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1575                 vdisplay /= 2;
1576                 vblank /= 2;
1577                 v_de_vs /= 2;
1578                 vsync_len /= 2;
1579         }
1580
1581         /* Set up horizontal active pixel width */
1582         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1583         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1584
1585         /* Set up vertical active lines */
1586         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1587         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1588
1589         /* Set up horizontal blanking pixel region width */
1590         hblank = mode->htotal - mode->hdisplay;
1591         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1592         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1593
1594         /* Set up vertical blanking pixel region width */
1595         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1596
1597         /* Set up HSYNC active edge delay width (in pixel clks) */
1598         h_de_hs = mode->hsync_start - mode->hdisplay;
1599         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1600         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1601
1602         /* Set up VSYNC active edge delay (in lines) */
1603         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1604
1605         /* Set up HSYNC active pulse width (in pixel clks) */
1606         hsync_len = mode->hsync_end - mode->hsync_start;
1607         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1608         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1609
1610         /* Set up VSYNC active edge delay (in lines) */
1611         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1612 }
1613
1614 /* HDMI Initialization Step B.4 */
1615 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1616 {
1617         /* control period minimum duration */
1618         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1619         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1620         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1621
1622         /* Set to fill TMDS data channels */
1623         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1624         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1625         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1626
1627         /* Enable pixel clock and tmds data path */
1628         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1629                            HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1630                            HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1631                            HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1632                            HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1633         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1634         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1635
1636         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1637         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1638
1639         /* Enable csc path */
1640         if (is_color_space_conversion(hdmi)) {
1641                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1642                 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1643         }
1644
1645         /* Enable color space conversion if needed */
1646         if (is_color_space_conversion(hdmi))
1647                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1648                             HDMI_MC_FLOWCTRL);
1649         else
1650                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1651                             HDMI_MC_FLOWCTRL);
1652 }
1653
1654 /* Workaround to clear the overflow condition */
1655 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1656 {
1657         unsigned int count;
1658         unsigned int i;
1659         u8 val;
1660
1661         /*
1662          * Under some circumstances the Frame Composer arithmetic unit can miss
1663          * an FC register write due to being busy processing the previous one.
1664          * The issue can be worked around by issuing a TMDS software reset and
1665          * then write one of the FC registers several times.
1666          *
1667          * The number of iterations matters and depends on the HDMI TX revision
1668          * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
1669          * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
1670          * as needing the workaround, with 4 iterations for v1.30a and 1
1671          * iteration for others.
1672          * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1673          * the workaround with a single iteration.
1674          */
1675
1676         switch (hdmi->version) {
1677         case 0x130a:
1678                 count = 4;
1679                 break;
1680         case 0x131a:
1681         case 0x132a:
1682         case 0x201a:
1683                 count = 1;
1684                 break;
1685         default:
1686                 return;
1687         }
1688
1689         /* TMDS software reset */
1690         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1691
1692         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1693         for (i = 0; i < count; i++)
1694                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1695 }
1696
1697 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1698 {
1699         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1700                     HDMI_IH_MUTE_FC_STAT2);
1701 }
1702
1703 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1704 {
1705         int ret;
1706
1707         hdmi_disable_overflow_interrupts(hdmi);
1708
1709         hdmi->vic = drm_match_cea_mode(mode);
1710
1711         if (!hdmi->vic) {
1712                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1713         } else {
1714                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1715         }
1716
1717         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1718             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1719             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1720             (hdmi->vic == 17) || (hdmi->vic == 18))
1721                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1722         else
1723                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1724
1725         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1726         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1727
1728         /* TOFIX: Get input format from plat data or fallback to RGB888 */
1729         if (hdmi->plat_data->input_bus_format)
1730                 hdmi->hdmi_data.enc_in_bus_format =
1731                         hdmi->plat_data->input_bus_format;
1732         else
1733                 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1734
1735         /* TOFIX: Get input encoding from plat data or fallback to none */
1736         if (hdmi->plat_data->input_bus_encoding)
1737                 hdmi->hdmi_data.enc_in_encoding =
1738                         hdmi->plat_data->input_bus_encoding;
1739         else
1740                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1741
1742         /* TOFIX: Default to RGB888 output format */
1743         hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1744
1745         hdmi->hdmi_data.pix_repet_factor = 0;
1746         hdmi->hdmi_data.hdcp_enable = 0;
1747         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1748
1749         /* HDMI Initialization Step B.1 */
1750         hdmi_av_composer(hdmi, mode);
1751
1752         /* HDMI Initializateion Step B.2 */
1753         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1754         if (ret)
1755                 return ret;
1756         hdmi->phy.enabled = true;
1757
1758         /* HDMI Initialization Step B.3 */
1759         dw_hdmi_enable_video_path(hdmi);
1760
1761         if (hdmi->sink_has_audio) {
1762                 dev_dbg(hdmi->dev, "sink has audio support\n");
1763
1764                 /* HDMI Initialization Step E - Configure audio */
1765                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1766                 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
1767         }
1768
1769         /* not for DVI mode */
1770         if (hdmi->sink_is_hdmi) {
1771                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1772
1773                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1774                 hdmi_config_AVI(hdmi, mode);
1775                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1776         } else {
1777                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1778         }
1779
1780         hdmi_video_packetize(hdmi);
1781         hdmi_video_csc(hdmi);
1782         hdmi_video_sample(hdmi);
1783         hdmi_tx_hdcp_config(hdmi);
1784
1785         dw_hdmi_clear_overflow(hdmi);
1786
1787         return 0;
1788 }
1789
1790 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
1791 {
1792         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1793                     HDMI_PHY_I2CM_INT_ADDR);
1794
1795         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1796                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1797                     HDMI_PHY_I2CM_CTLINT_ADDR);
1798 }
1799
1800 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1801 {
1802         u8 ih_mute;
1803
1804         /*
1805          * Boot up defaults are:
1806          * HDMI_IH_MUTE   = 0x03 (disabled)
1807          * HDMI_IH_MUTE_* = 0x00 (enabled)
1808          *
1809          * Disable top level interrupt bits in HDMI block
1810          */
1811         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1812                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1813                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1814
1815         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1816
1817         /* by default mask all interrupts */
1818         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1819         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1820         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1821         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1822         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1823         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1824         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1825         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1826         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1827         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1828         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1829         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1830         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1831         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1832
1833         /* Disable interrupts in the IH_MUTE_* registers */
1834         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1835         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1836         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1837         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1838         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1839         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1840         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1841         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1842         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1843         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1844
1845         /* Enable top level interrupt bits in HDMI block */
1846         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1847                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1848         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1849 }
1850
1851 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1852 {
1853         hdmi->bridge_is_on = true;
1854         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1855 }
1856
1857 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1858 {
1859         if (hdmi->phy.enabled) {
1860                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1861                 hdmi->phy.enabled = false;
1862         }
1863
1864         hdmi->bridge_is_on = false;
1865 }
1866
1867 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1868 {
1869         int force = hdmi->force;
1870
1871         if (hdmi->disabled) {
1872                 force = DRM_FORCE_OFF;
1873         } else if (force == DRM_FORCE_UNSPECIFIED) {
1874                 if (hdmi->rxsense)
1875                         force = DRM_FORCE_ON;
1876                 else
1877                         force = DRM_FORCE_OFF;
1878         }
1879
1880         if (force == DRM_FORCE_OFF) {
1881                 if (hdmi->bridge_is_on)
1882                         dw_hdmi_poweroff(hdmi);
1883         } else {
1884                 if (!hdmi->bridge_is_on)
1885                         dw_hdmi_poweron(hdmi);
1886         }
1887 }
1888
1889 /*
1890  * Adjust the detection of RXSENSE according to whether we have a forced
1891  * connection mode enabled, or whether we have been disabled.  There is
1892  * no point processing RXSENSE interrupts if we have a forced connection
1893  * state, or DRM has us disabled.
1894  *
1895  * We also disable rxsense interrupts when we think we're disconnected
1896  * to avoid floating TDMS signals giving false rxsense interrupts.
1897  *
1898  * Note: we still need to listen for HPD interrupts even when DRM has us
1899  * disabled so that we can detect a connect event.
1900  */
1901 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1902 {
1903         if (hdmi->phy.ops->update_hpd)
1904                 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
1905                                           hdmi->force, hdmi->disabled,
1906                                           hdmi->rxsense);
1907 }
1908
1909 static enum drm_connector_status
1910 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1911 {
1912         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1913                                              connector);
1914
1915         mutex_lock(&hdmi->mutex);
1916         hdmi->force = DRM_FORCE_UNSPECIFIED;
1917         dw_hdmi_update_power(hdmi);
1918         dw_hdmi_update_phy_mask(hdmi);
1919         mutex_unlock(&hdmi->mutex);
1920
1921         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1922 }
1923
1924 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1925 {
1926         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1927                                              connector);
1928         struct edid *edid;
1929         int ret = 0;
1930
1931         if (!hdmi->ddc)
1932                 return 0;
1933
1934         edid = drm_get_edid(connector, hdmi->ddc);
1935         if (edid) {
1936                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1937                         edid->width_cm, edid->height_cm);
1938
1939                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1940                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1941                 drm_connector_update_edid_property(connector, edid);
1942                 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
1943                 ret = drm_add_edid_modes(connector, edid);
1944                 kfree(edid);
1945         } else {
1946                 dev_dbg(hdmi->dev, "failed to get edid\n");
1947         }
1948
1949         return ret;
1950 }
1951
1952 static void dw_hdmi_connector_force(struct drm_connector *connector)
1953 {
1954         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1955                                              connector);
1956
1957         mutex_lock(&hdmi->mutex);
1958         hdmi->force = connector->force;
1959         dw_hdmi_update_power(hdmi);
1960         dw_hdmi_update_phy_mask(hdmi);
1961         mutex_unlock(&hdmi->mutex);
1962 }
1963
1964 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1965         .fill_modes = drm_helper_probe_single_connector_modes,
1966         .detect = dw_hdmi_connector_detect,
1967         .destroy = drm_connector_cleanup,
1968         .force = dw_hdmi_connector_force,
1969         .reset = drm_atomic_helper_connector_reset,
1970         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1971         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1972 };
1973
1974 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1975         .get_modes = dw_hdmi_connector_get_modes,
1976         .best_encoder = drm_atomic_helper_best_encoder,
1977 };
1978
1979 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1980 {
1981         struct dw_hdmi *hdmi = bridge->driver_private;
1982         struct drm_encoder *encoder = bridge->encoder;
1983         struct drm_connector *connector = &hdmi->connector;
1984
1985         connector->interlace_allowed = 1;
1986         connector->polled = DRM_CONNECTOR_POLL_HPD;
1987
1988         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1989
1990         drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1991                            DRM_MODE_CONNECTOR_HDMIA);
1992
1993         drm_connector_attach_encoder(connector, encoder);
1994
1995         return 0;
1996 }
1997
1998 static enum drm_mode_status
1999 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2000                           const struct drm_display_mode *mode)
2001 {
2002         struct dw_hdmi *hdmi = bridge->driver_private;
2003         struct drm_connector *connector = &hdmi->connector;
2004         enum drm_mode_status mode_status = MODE_OK;
2005
2006         /* We don't support double-clocked modes */
2007         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2008                 return MODE_BAD;
2009
2010         if (hdmi->plat_data->mode_valid)
2011                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2012
2013         return mode_status;
2014 }
2015
2016 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2017                                     struct drm_display_mode *orig_mode,
2018                                     struct drm_display_mode *mode)
2019 {
2020         struct dw_hdmi *hdmi = bridge->driver_private;
2021
2022         mutex_lock(&hdmi->mutex);
2023
2024         /* Store the display mode for plugin/DKMS poweron events */
2025         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2026
2027         mutex_unlock(&hdmi->mutex);
2028 }
2029
2030 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2031 {
2032         struct dw_hdmi *hdmi = bridge->driver_private;
2033
2034         mutex_lock(&hdmi->mutex);
2035         hdmi->disabled = true;
2036         dw_hdmi_update_power(hdmi);
2037         dw_hdmi_update_phy_mask(hdmi);
2038         mutex_unlock(&hdmi->mutex);
2039 }
2040
2041 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2042 {
2043         struct dw_hdmi *hdmi = bridge->driver_private;
2044
2045         mutex_lock(&hdmi->mutex);
2046         hdmi->disabled = false;
2047         dw_hdmi_update_power(hdmi);
2048         dw_hdmi_update_phy_mask(hdmi);
2049         mutex_unlock(&hdmi->mutex);
2050 }
2051
2052 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2053         .attach = dw_hdmi_bridge_attach,
2054         .enable = dw_hdmi_bridge_enable,
2055         .disable = dw_hdmi_bridge_disable,
2056         .mode_set = dw_hdmi_bridge_mode_set,
2057         .mode_valid = dw_hdmi_bridge_mode_valid,
2058 };
2059
2060 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2061 {
2062         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2063         unsigned int stat;
2064
2065         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2066         if (!stat)
2067                 return IRQ_NONE;
2068
2069         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2070
2071         i2c->stat = stat;
2072
2073         complete(&i2c->cmp);
2074
2075         return IRQ_HANDLED;
2076 }
2077
2078 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2079 {
2080         struct dw_hdmi *hdmi = dev_id;
2081         u8 intr_stat;
2082         irqreturn_t ret = IRQ_NONE;
2083
2084         if (hdmi->i2c)
2085                 ret = dw_hdmi_i2c_irq(hdmi);
2086
2087         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2088         if (intr_stat) {
2089                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2090                 return IRQ_WAKE_THREAD;
2091         }
2092
2093         return ret;
2094 }
2095
2096 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2097 {
2098         mutex_lock(&hdmi->mutex);
2099
2100         if (!hdmi->force) {
2101                 /*
2102                  * If the RX sense status indicates we're disconnected,
2103                  * clear the software rxsense status.
2104                  */
2105                 if (!rx_sense)
2106                         hdmi->rxsense = false;
2107
2108                 /*
2109                  * Only set the software rxsense status when both
2110                  * rxsense and hpd indicates we're connected.
2111                  * This avoids what seems to be bad behaviour in
2112                  * at least iMX6S versions of the phy.
2113                  */
2114                 if (hpd)
2115                         hdmi->rxsense = true;
2116
2117                 dw_hdmi_update_power(hdmi);
2118                 dw_hdmi_update_phy_mask(hdmi);
2119         }
2120         mutex_unlock(&hdmi->mutex);
2121 }
2122 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2123
2124 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2125 {
2126         struct dw_hdmi *hdmi = dev_id;
2127         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2128
2129         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2130         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2131         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2132
2133         phy_pol_mask = 0;
2134         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2135                 phy_pol_mask |= HDMI_PHY_HPD;
2136         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2137                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2138         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2139                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2140         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2141                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2142         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2143                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2144
2145         if (phy_pol_mask)
2146                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2147
2148         /*
2149          * RX sense tells us whether the TDMS transmitters are detecting
2150          * load - in other words, there's something listening on the
2151          * other end of the link.  Use this to decide whether we should
2152          * power on the phy as HPD may be toggled by the sink to merely
2153          * ask the source to re-read the EDID.
2154          */
2155         if (intr_stat &
2156             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2157                 dw_hdmi_setup_rx_sense(hdmi,
2158                                        phy_stat & HDMI_PHY_HPD,
2159                                        phy_stat & HDMI_PHY_RX_SENSE);
2160
2161                 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2162                         cec_notifier_set_phys_addr(hdmi->cec_notifier,
2163                                                    CEC_PHYS_ADDR_INVALID);
2164         }
2165
2166         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2167                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2168                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2169                 if (hdmi->bridge.dev)
2170                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
2171         }
2172
2173         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2174         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2175                     HDMI_IH_MUTE_PHY_STAT0);
2176
2177         return IRQ_HANDLED;
2178 }
2179
2180 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2181         {
2182                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2183                 .name = "DWC HDMI TX PHY",
2184                 .gen = 1,
2185         }, {
2186                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2187                 .name = "DWC MHL PHY + HEAC PHY",
2188                 .gen = 2,
2189                 .has_svsret = true,
2190                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2191         }, {
2192                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2193                 .name = "DWC MHL PHY",
2194                 .gen = 2,
2195                 .has_svsret = true,
2196                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2197         }, {
2198                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2199                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2200                 .gen = 2,
2201                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2202         }, {
2203                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2204                 .name = "DWC HDMI 3D TX PHY",
2205                 .gen = 2,
2206                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2207         }, {
2208                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2209                 .name = "DWC HDMI 2.0 TX PHY",
2210                 .gen = 2,
2211                 .has_svsret = true,
2212                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2213         }, {
2214                 .type = DW_HDMI_PHY_VENDOR_PHY,
2215                 .name = "Vendor PHY",
2216         }
2217 };
2218
2219 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2220 {
2221         unsigned int i;
2222         u8 phy_type;
2223
2224         phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2225
2226         if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2227                 /* Vendor PHYs require support from the glue layer. */
2228                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2229                         dev_err(hdmi->dev,
2230                                 "Vendor HDMI PHY not supported by glue layer\n");
2231                         return -ENODEV;
2232                 }
2233
2234                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2235                 hdmi->phy.data = hdmi->plat_data->phy_data;
2236                 hdmi->phy.name = hdmi->plat_data->phy_name;
2237                 return 0;
2238         }
2239
2240         /* Synopsys PHYs are handled internally. */
2241         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2242                 if (dw_hdmi_phys[i].type == phy_type) {
2243                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2244                         hdmi->phy.name = dw_hdmi_phys[i].name;
2245                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2246
2247                         if (!dw_hdmi_phys[i].configure &&
2248                             !hdmi->plat_data->configure_phy) {
2249                                 dev_err(hdmi->dev, "%s requires platform support\n",
2250                                         hdmi->phy.name);
2251                                 return -ENODEV;
2252                         }
2253
2254                         return 0;
2255                 }
2256         }
2257
2258         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2259         return -ENODEV;
2260 }
2261
2262 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2263 {
2264         mutex_lock(&hdmi->mutex);
2265         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2266         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2267         mutex_unlock(&hdmi->mutex);
2268 }
2269
2270 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2271 {
2272         mutex_lock(&hdmi->mutex);
2273         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2274         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2275         mutex_unlock(&hdmi->mutex);
2276 }
2277
2278 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2279         .write = hdmi_writeb,
2280         .read = hdmi_readb,
2281         .enable = dw_hdmi_cec_enable,
2282         .disable = dw_hdmi_cec_disable,
2283 };
2284
2285 static const struct regmap_config hdmi_regmap_8bit_config = {
2286         .reg_bits       = 32,
2287         .val_bits       = 8,
2288         .reg_stride     = 1,
2289         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2290 };
2291
2292 static const struct regmap_config hdmi_regmap_32bit_config = {
2293         .reg_bits       = 32,
2294         .val_bits       = 32,
2295         .reg_stride     = 4,
2296         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2297 };
2298
2299 static struct dw_hdmi *
2300 __dw_hdmi_probe(struct platform_device *pdev,
2301                 const struct dw_hdmi_plat_data *plat_data)
2302 {
2303         struct device *dev = &pdev->dev;
2304         struct device_node *np = dev->of_node;
2305         struct platform_device_info pdevinfo;
2306         struct device_node *ddc_node;
2307         struct dw_hdmi_cec_data cec;
2308         struct dw_hdmi *hdmi;
2309         struct resource *iores = NULL;
2310         int irq;
2311         int ret;
2312         u32 val = 1;
2313         u8 prod_id0;
2314         u8 prod_id1;
2315         u8 config0;
2316         u8 config3;
2317
2318         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2319         if (!hdmi)
2320                 return ERR_PTR(-ENOMEM);
2321
2322         hdmi->plat_data = plat_data;
2323         hdmi->dev = dev;
2324         hdmi->sample_rate = 48000;
2325         hdmi->disabled = true;
2326         hdmi->rxsense = true;
2327         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2328         hdmi->mc_clkdis = 0x7f;
2329
2330         mutex_init(&hdmi->mutex);
2331         mutex_init(&hdmi->audio_mutex);
2332         spin_lock_init(&hdmi->audio_lock);
2333
2334         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2335         if (ddc_node) {
2336                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2337                 of_node_put(ddc_node);
2338                 if (!hdmi->ddc) {
2339                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2340                         return ERR_PTR(-EPROBE_DEFER);
2341                 }
2342
2343         } else {
2344                 dev_dbg(hdmi->dev, "no ddc property found\n");
2345         }
2346
2347         if (!plat_data->regm) {
2348                 const struct regmap_config *reg_config;
2349
2350                 of_property_read_u32(np, "reg-io-width", &val);
2351                 switch (val) {
2352                 case 4:
2353                         reg_config = &hdmi_regmap_32bit_config;
2354                         hdmi->reg_shift = 2;
2355                         break;
2356                 case 1:
2357                         reg_config = &hdmi_regmap_8bit_config;
2358                         break;
2359                 default:
2360                         dev_err(dev, "reg-io-width must be 1 or 4\n");
2361                         return ERR_PTR(-EINVAL);
2362                 }
2363
2364                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2365                 hdmi->regs = devm_ioremap_resource(dev, iores);
2366                 if (IS_ERR(hdmi->regs)) {
2367                         ret = PTR_ERR(hdmi->regs);
2368                         goto err_res;
2369                 }
2370
2371                 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2372                 if (IS_ERR(hdmi->regm)) {
2373                         dev_err(dev, "Failed to configure regmap\n");
2374                         ret = PTR_ERR(hdmi->regm);
2375                         goto err_res;
2376                 }
2377         } else {
2378                 hdmi->regm = plat_data->regm;
2379         }
2380
2381         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2382         if (IS_ERR(hdmi->isfr_clk)) {
2383                 ret = PTR_ERR(hdmi->isfr_clk);
2384                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2385                 goto err_res;
2386         }
2387
2388         ret = clk_prepare_enable(hdmi->isfr_clk);
2389         if (ret) {
2390                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2391                 goto err_res;
2392         }
2393
2394         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2395         if (IS_ERR(hdmi->iahb_clk)) {
2396                 ret = PTR_ERR(hdmi->iahb_clk);
2397                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2398                 goto err_isfr;
2399         }
2400
2401         ret = clk_prepare_enable(hdmi->iahb_clk);
2402         if (ret) {
2403                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2404                 goto err_isfr;
2405         }
2406
2407         hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2408         if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2409                 hdmi->cec_clk = NULL;
2410         } else if (IS_ERR(hdmi->cec_clk)) {
2411                 ret = PTR_ERR(hdmi->cec_clk);
2412                 if (ret != -EPROBE_DEFER)
2413                         dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2414                                 ret);
2415
2416                 hdmi->cec_clk = NULL;
2417                 goto err_iahb;
2418         } else {
2419                 ret = clk_prepare_enable(hdmi->cec_clk);
2420                 if (ret) {
2421                         dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2422                                 ret);
2423                         goto err_iahb;
2424                 }
2425         }
2426
2427         /* Product and revision IDs */
2428         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2429                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2430         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2431         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2432
2433         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2434             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2435                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2436                         hdmi->version, prod_id0, prod_id1);
2437                 ret = -ENODEV;
2438                 goto err_iahb;
2439         }
2440
2441         ret = dw_hdmi_detect_phy(hdmi);
2442         if (ret < 0)
2443                 goto err_iahb;
2444
2445         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2446                  hdmi->version >> 12, hdmi->version & 0xfff,
2447                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2448                  hdmi->phy.name);
2449
2450         initialize_hdmi_ih_mutes(hdmi);
2451
2452         irq = platform_get_irq(pdev, 0);
2453         if (irq < 0) {
2454                 ret = irq;
2455                 goto err_iahb;
2456         }
2457
2458         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2459                                         dw_hdmi_irq, IRQF_SHARED,
2460                                         dev_name(dev), hdmi);
2461         if (ret)
2462                 goto err_iahb;
2463
2464         hdmi->cec_notifier = cec_notifier_get(dev);
2465         if (!hdmi->cec_notifier) {
2466                 ret = -ENOMEM;
2467                 goto err_iahb;
2468         }
2469
2470         /*
2471          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2472          * N and cts values before enabling phy
2473          */
2474         hdmi_init_clk_regenerator(hdmi);
2475
2476         /* If DDC bus is not specified, try to register HDMI I2C bus */
2477         if (!hdmi->ddc) {
2478                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2479                 if (IS_ERR(hdmi->ddc))
2480                         hdmi->ddc = NULL;
2481         }
2482
2483         hdmi->bridge.driver_private = hdmi;
2484         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2485 #ifdef CONFIG_OF
2486         hdmi->bridge.of_node = pdev->dev.of_node;
2487 #endif
2488
2489         dw_hdmi_setup_i2c(hdmi);
2490         if (hdmi->phy.ops->setup_hpd)
2491                 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2492
2493         memset(&pdevinfo, 0, sizeof(pdevinfo));
2494         pdevinfo.parent = dev;
2495         pdevinfo.id = PLATFORM_DEVID_AUTO;
2496
2497         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2498         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2499
2500         if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2501                 struct dw_hdmi_audio_data audio;
2502
2503                 audio.phys = iores->start;
2504                 audio.base = hdmi->regs;
2505                 audio.irq = irq;
2506                 audio.hdmi = hdmi;
2507                 audio.eld = hdmi->connector.eld;
2508                 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2509                 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2510
2511                 pdevinfo.name = "dw-hdmi-ahb-audio";
2512                 pdevinfo.data = &audio;
2513                 pdevinfo.size_data = sizeof(audio);
2514                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2515                 hdmi->audio = platform_device_register_full(&pdevinfo);
2516         } else if (config0 & HDMI_CONFIG0_I2S) {
2517                 struct dw_hdmi_i2s_audio_data audio;
2518
2519                 audio.hdmi      = hdmi;
2520                 audio.write     = hdmi_writeb;
2521                 audio.read      = hdmi_readb;
2522                 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2523                 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2524
2525                 pdevinfo.name = "dw-hdmi-i2s-audio";
2526                 pdevinfo.data = &audio;
2527                 pdevinfo.size_data = sizeof(audio);
2528                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2529                 hdmi->audio = platform_device_register_full(&pdevinfo);
2530         }
2531
2532         if (config0 & HDMI_CONFIG0_CEC) {
2533                 cec.hdmi = hdmi;
2534                 cec.ops = &dw_hdmi_cec_ops;
2535                 cec.irq = irq;
2536
2537                 pdevinfo.name = "dw-hdmi-cec";
2538                 pdevinfo.data = &cec;
2539                 pdevinfo.size_data = sizeof(cec);
2540                 pdevinfo.dma_mask = 0;
2541
2542                 hdmi->cec = platform_device_register_full(&pdevinfo);
2543         }
2544
2545         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2546         if (hdmi->i2c)
2547                 dw_hdmi_i2c_init(hdmi);
2548
2549         return hdmi;
2550
2551 err_iahb:
2552         if (hdmi->i2c) {
2553                 i2c_del_adapter(&hdmi->i2c->adap);
2554                 hdmi->ddc = NULL;
2555         }
2556
2557         if (hdmi->cec_notifier)
2558                 cec_notifier_put(hdmi->cec_notifier);
2559
2560         clk_disable_unprepare(hdmi->iahb_clk);
2561         if (hdmi->cec_clk)
2562                 clk_disable_unprepare(hdmi->cec_clk);
2563 err_isfr:
2564         clk_disable_unprepare(hdmi->isfr_clk);
2565 err_res:
2566         i2c_put_adapter(hdmi->ddc);
2567
2568         return ERR_PTR(ret);
2569 }
2570
2571 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2572 {
2573         if (hdmi->audio && !IS_ERR(hdmi->audio))
2574                 platform_device_unregister(hdmi->audio);
2575         if (!IS_ERR(hdmi->cec))
2576                 platform_device_unregister(hdmi->cec);
2577
2578         /* Disable all interrupts */
2579         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2580
2581         if (hdmi->cec_notifier)
2582                 cec_notifier_put(hdmi->cec_notifier);
2583
2584         clk_disable_unprepare(hdmi->iahb_clk);
2585         clk_disable_unprepare(hdmi->isfr_clk);
2586         if (hdmi->cec_clk)
2587                 clk_disable_unprepare(hdmi->cec_clk);
2588
2589         if (hdmi->i2c)
2590                 i2c_del_adapter(&hdmi->i2c->adap);
2591         else
2592                 i2c_put_adapter(hdmi->ddc);
2593 }
2594
2595 /* -----------------------------------------------------------------------------
2596  * Probe/remove API, used from platforms based on the DRM bridge API.
2597  */
2598 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2599                               const struct dw_hdmi_plat_data *plat_data)
2600 {
2601         struct dw_hdmi *hdmi;
2602
2603         hdmi = __dw_hdmi_probe(pdev, plat_data);
2604         if (IS_ERR(hdmi))
2605                 return hdmi;
2606
2607         drm_bridge_add(&hdmi->bridge);
2608
2609         return hdmi;
2610 }
2611 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2612
2613 void dw_hdmi_remove(struct dw_hdmi *hdmi)
2614 {
2615         drm_bridge_remove(&hdmi->bridge);
2616
2617         __dw_hdmi_remove(hdmi);
2618 }
2619 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2620
2621 /* -----------------------------------------------------------------------------
2622  * Bind/unbind API, used from platforms based on the component framework.
2623  */
2624 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2625                              struct drm_encoder *encoder,
2626                              const struct dw_hdmi_plat_data *plat_data)
2627 {
2628         struct dw_hdmi *hdmi;
2629         int ret;
2630
2631         hdmi = __dw_hdmi_probe(pdev, plat_data);
2632         if (IS_ERR(hdmi))
2633                 return hdmi;
2634
2635         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2636         if (ret) {
2637                 dw_hdmi_remove(hdmi);
2638                 DRM_ERROR("Failed to initialize bridge with drm\n");
2639                 return ERR_PTR(ret);
2640         }
2641
2642         return hdmi;
2643 }
2644 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2645
2646 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
2647 {
2648         __dw_hdmi_remove(hdmi);
2649 }
2650 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2651
2652 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2653 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2654 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2655 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2656 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2657 MODULE_LICENSE("GPL");
2658 MODULE_ALIAS("platform:dw-hdmi");