drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/irq.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <drm/drm_of.h>
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_encoder_slave.h>
  31 #include <drm/bridge/dw_hdmi.h>
  32
  33 #include <uapi/linux/media-bus-format.h>
  34 #include <uapi/linux/videodev2.h>
  35
  36 #include "dw-hdmi.h"
  37 #include "dw-hdmi-audio.h"
  38 #include "dw-hdmi-cec.h"
  39
  40 #include <media/cec-notifier.h>
  41
  42 #define DDC_CI_ADDR             0x37
  43 #define DDC_SEGMENT_ADDR        0x30
  44
  45 #define HDMI_EDID_LEN           512
  46
  47 enum hdmi_datamap {
  48         RGB444_8B = 0x01,
  49         RGB444_10B = 0x03,
  50         RGB444_12B = 0x05,
  51         RGB444_16B = 0x07,
  52         YCbCr444_8B = 0x09,
  53         YCbCr444_10B = 0x0B,
  54         YCbCr444_12B = 0x0D,
  55         YCbCr444_16B = 0x0F,
  56         YCbCr422_8B = 0x16,
  57         YCbCr422_10B = 0x14,
  58         YCbCr422_12B = 0x12,
  59 };
  60
  61 static const u16 csc_coeff_default[3][4] = {
  62         { 0x2000, 0x0000, 0x0000, 0x0000 },
  63         { 0x0000, 0x2000, 0x0000, 0x0000 },
  64         { 0x0000, 0x0000, 0x2000, 0x0000 }
  65 };
  66
  67 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  68         { 0x2000, 0x6926, 0x74fd, 0x010e },
  69         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  70         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  71 };
  72
  73 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  74         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  75         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  76         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  77 };
  78
  79 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  80         { 0x2591, 0x1322, 0x074b, 0x0000 },
  81         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  82         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  83 };
  84
  85 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  86         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  87         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  88         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  89 };
  90
  91 struct hdmi_vmode {
  92         bool mdataenablepolarity;
  93
  94         unsigned int mpixelclock;
  95         unsigned int mpixelrepetitioninput;
  96         unsigned int mpixelrepetitionoutput;
  97 };
  98
  99 struct hdmi_data_info {
 100         unsigned int enc_in_bus_format;
 101         unsigned int enc_out_bus_format;
 102         unsigned int enc_in_encoding;
 103         unsigned int enc_out_encoding;
 104         unsigned int pix_repet_factor;
 105         unsigned int hdcp_enable;
 106         struct hdmi_vmode video_mode;
 107 };
 108
 109 struct dw_hdmi_i2c {
 110         struct i2c_adapter      adap;
 111
 112         struct mutex            lock;   /* used to serialize data transfers */
 113         struct completion       cmp;
 114         u8                      stat;
 115
 116         u8                      slave_reg;
 117         bool                    is_regaddr;
 118         bool                    is_segment;
 119 };
 120
 121 struct dw_hdmi_phy_data {
 122         enum dw_hdmi_phy_type type;
 123         const char *name;
 124         unsigned int gen;
 125         bool has_svsret;
 126         int (*configure)(struct dw_hdmi *hdmi,
 127                          const struct dw_hdmi_plat_data *pdata,
 128                          unsigned long mpixelclock);
 129 };
 130
 131 struct dw_hdmi {
 132         struct drm_connector connector;
 133         struct drm_bridge bridge;
 134
 135         unsigned int version;
 136
 137         struct platform_device *audio;
 138         struct platform_device *cec;
 139         struct device *dev;
 140         struct clk *isfr_clk;
 141         struct clk *iahb_clk;
 142         struct dw_hdmi_i2c *i2c;
 143
 144         struct hdmi_data_info hdmi_data;
 145         const struct dw_hdmi_plat_data *plat_data;
 146
 147         int vic;
 148
 149         u8 edid[HDMI_EDID_LEN];
 150         bool cable_plugin;
 151
 152         struct {
 153                 const struct dw_hdmi_phy_ops *ops;
 154                 const char *name;
 155                 void *data;
 156                 bool enabled;
 157         } phy;
 158
 159         struct drm_display_mode previous_mode;
 160
 161         struct i2c_adapter *ddc;
 162         void __iomem *regs;
 163         bool sink_is_hdmi;
 164         bool sink_has_audio;
 165
 166         struct mutex mutex;             /* for state below and previous_mode */
 167         enum drm_connector_force force; /* mutex-protected force state */
 168         bool disabled;                  /* DRM has disabled our bridge */
 169         bool bridge_is_on;              /* indicates the bridge is on */
 170         bool rxsense;                   /* rxsense state */
 171         u8 phy_mask;                    /* desired phy int mask settings */
 172         u8 mc_clkdis;                   /* clock disable register */
 173
 174         spinlock_t audio_lock;
 175         struct mutex audio_mutex;
 176         unsigned int sample_rate;
 177         unsigned int audio_cts;
 178         unsigned int audio_n;
 179         bool audio_enable;
 180
 181         unsigned int reg_shift;
 182         struct regmap *regm;
 183         void (*enable_audio)(struct dw_hdmi *hdmi);
 184         void (*disable_audio)(struct dw_hdmi *hdmi);
 185
 186         struct cec_notifier *cec_notifier;
 187 };
 188
 189 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 190         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 191          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 192
 193 #define HDMI_PHY_RX_SENSE \
 194         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 195          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 196
 197 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 198 {
 199         regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
 200 }
 201
 202 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 203 {
 204         unsigned int val = 0;
 205
 206         regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
 207
 208         return val;
 209 }
 210
 211 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 212 {
 213         regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
 214 }
 215
 216 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 217                              u8 shift, u8 mask)
 218 {
 219         hdmi_modb(hdmi, data << shift, mask, reg);
 220 }
 221
 222 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 223 {
 224         /* Software reset */
 225         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 226
 227         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
 228         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 229
 230         /* Set done, not acknowledged and arbitration interrupt polarities */
 231         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 232         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 233                     HDMI_I2CM_CTLINT);
 234
 235         /* Clear DONE and ERROR interrupts */
 236         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 237                     HDMI_IH_I2CM_STAT0);
 238
 239         /* Mute DONE and ERROR interrupts */
 240         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 241                     HDMI_IH_MUTE_I2CM_STAT0);
 242 }
 243
 244 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 245                             unsigned char *buf, unsigned int length)
 246 {
 247         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 248         int stat;
 249
 250         if (!i2c->is_regaddr) {
 251                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 252                 i2c->slave_reg = 0x00;
 253                 i2c->is_regaddr = true;
 254         }
 255
 256         while (length--) {
 257                 reinit_completion(&i2c->cmp);
 258
 259                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 260                 if (i2c->is_segment)
 261                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 262                                     HDMI_I2CM_OPERATION);
 263                 else
 264                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 265                                     HDMI_I2CM_OPERATION);
 266
 267                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 268                 if (!stat)
 269                         return -EAGAIN;
 270
 271                 /* Check for error condition on the bus */
 272                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 273                         return -EIO;
 274
 275                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 276         }
 277         i2c->is_segment = false;
 278
 279         return 0;
 280 }
 281
 282 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 283                              unsigned char *buf, unsigned int length)
 284 {
 285         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 286         int stat;
 287
 288         if (!i2c->is_regaddr) {
 289                 /* Use the first write byte as register address */
 290                 i2c->slave_reg = buf[0];
 291                 length--;
 292                 buf++;
 293                 i2c->is_regaddr = true;
 294         }
 295
 296         while (length--) {
 297                 reinit_completion(&i2c->cmp);
 298
 299                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 300                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 301                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 302                             HDMI_I2CM_OPERATION);
 303
 304                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 305                 if (!stat)
 306                         return -EAGAIN;
 307
 308                 /* Check for error condition on the bus */
 309                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 310                         return -EIO;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 317                             struct i2c_msg *msgs, int num)
 318 {
 319         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 320         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 321         u8 addr = msgs[0].addr;
 322         int i, ret = 0;
 323
 324         if (addr == DDC_CI_ADDR)
 325                 /*
 326                  * The internal I2C controller does not support the multi-byte
 327                  * read and write operations needed for DDC/CI.
 328                  * TOFIX: Blacklist the DDC/CI address until we filter out
 329                  * unsupported I2C operations.
 330                  */
 331                 return -EOPNOTSUPP;
 332
 333         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 334
 335         for (i = 0; i < num; i++) {
 336                 if (msgs[i].len == 0) {
 337                         dev_dbg(hdmi->dev,
 338                                 "unsupported transfer %d/%d, no data\n",
 339                                 i + 1, num);
 340                         return -EOPNOTSUPP;
 341                 }
 342         }
 343
 344         mutex_lock(&i2c->lock);
 345
 346         /* Unmute DONE and ERROR interrupts */
 347         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 348
 349         /* Set slave device address taken from the first I2C message */
 350         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 351
 352         /* Set slave device register address on transfer */
 353         i2c->is_regaddr = false;
 354
 355         /* Set segment pointer for I2C extended read mode operation */
 356         i2c->is_segment = false;
 357
 358         for (i = 0; i < num; i++) {
 359                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 360                         i + 1, num, msgs[i].len, msgs[i].flags);
 361                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 362                         i2c->is_segment = true;
 363                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 364                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 365                 } else {
 366                         if (msgs[i].flags & I2C_M_RD)
 367                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 368                                                        msgs[i].len);
 369                         else
 370                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 371                                                         msgs[i].len);
 372                 }
 373                 if (ret < 0)
 374                         break;
 375         }
 376
 377         if (!ret)
 378                 ret = num;
 379
 380         /* Mute DONE and ERROR interrupts */
 381         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 382                     HDMI_IH_MUTE_I2CM_STAT0);
 383
 384         mutex_unlock(&i2c->lock);
 385
 386         return ret;
 387 }
 388
 389 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 390 {
 391         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 392 }
 393
 394 static const struct i2c_algorithm dw_hdmi_algorithm = {
 395         .master_xfer    = dw_hdmi_i2c_xfer,
 396         .functionality  = dw_hdmi_i2c_func,
 397 };
 398
 399 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 400 {
 401         struct i2c_adapter *adap;
 402         struct dw_hdmi_i2c *i2c;
 403         int ret;
 404
 405         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 406         if (!i2c)
 407                 return ERR_PTR(-ENOMEM);
 408
 409         mutex_init(&i2c->lock);
 410         init_completion(&i2c->cmp);
 411
 412         adap = &i2c->adap;
 413         adap->class = I2C_CLASS_DDC;
 414         adap->owner = THIS_MODULE;
 415         adap->dev.parent = hdmi->dev;
 416         adap->algo = &dw_hdmi_algorithm;
 417         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 418         i2c_set_adapdata(adap, hdmi);
 419
 420         ret = i2c_add_adapter(adap);
 421         if (ret) {
 422                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 423                 devm_kfree(hdmi->dev, i2c);
 424                 return ERR_PTR(ret);
 425         }
 426
 427         hdmi->i2c = i2c;
 428
 429         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 430
 431         return adap;
 432 }
 433
 434 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 435                            unsigned int n)
 436 {
 437         /* Must be set/cleared first */
 438         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 439
 440         /* nshift factor = 0 */
 441         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 442
 443         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 444                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 445         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 446         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 447
 448         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 449         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 450         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 451 }
 452
 453 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 454 {
 455         unsigned int n = (128 * freq) / 1000;
 456         unsigned int mult = 1;
 457
 458         while (freq > 48000) {
 459                 mult *= 2;
 460                 freq /= 2;
 461         }
 462
 463         switch (freq) {
 464         case 32000:
 465                 if (pixel_clk == 25175000)
 466                         n = 4576;
 467                 else if (pixel_clk == 27027000)
 468                         n = 4096;
 469                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 470                         n = 11648;
 471                 else
 472                         n = 4096;
 473                 n *= mult;
 474                 break;
 475
 476         case 44100:
 477                 if (pixel_clk == 25175000)
 478                         n = 7007;
 479                 else if (pixel_clk == 74176000)
 480                         n = 17836;
 481                 else if (pixel_clk == 148352000)
 482                         n = 8918;
 483                 else
 484                         n = 6272;
 485                 n *= mult;
 486                 break;
 487
 488         case 48000:
 489                 if (pixel_clk == 25175000)
 490                         n = 6864;
 491                 else if (pixel_clk == 27027000)
 492                         n = 6144;
 493                 else if (pixel_clk == 74176000)
 494                         n = 11648;
 495                 else if (pixel_clk == 148352000)
 496                         n = 5824;
 497                 else
 498                         n = 6144;
 499                 n *= mult;
 500                 break;
 501
 502         default:
 503                 break;
 504         }
 505
 506         return n;
 507 }
 508
 509 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 510         unsigned long pixel_clk, unsigned int sample_rate)
 511 {
 512         unsigned long ftdms = pixel_clk;
 513         unsigned int n, cts;
 514         u64 tmp;
 515
 516         n = hdmi_compute_n(sample_rate, pixel_clk);
 517
 518         /*
 519          * Compute the CTS value from the N value.  Note that CTS and N
 520          * can be up to 20 bits in total, so we need 64-bit math.  Also
 521          * note that our TDMS clock is not fully accurate; it is accurate
 522          * to kHz.  This can introduce an unnecessary remainder in the
 523          * calculation below, so we don't try to warn about that.
 524          */
 525         tmp = (u64)ftdms * n;
 526         do_div(tmp, 128 * sample_rate);
 527         cts = tmp;
 528
 529         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 530                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 531                 n, cts);
 532
 533         spin_lock_irq(&hdmi->audio_lock);
 534         hdmi->audio_n = n;
 535         hdmi->audio_cts = cts;
 536         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 537         spin_unlock_irq(&hdmi->audio_lock);
 538 }
 539
 540 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 541 {
 542         mutex_lock(&hdmi->audio_mutex);
 543         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 544         mutex_unlock(&hdmi->audio_mutex);
 545 }
 546
 547 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 548 {
 549         mutex_lock(&hdmi->audio_mutex);
 550         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 551                                  hdmi->sample_rate);
 552         mutex_unlock(&hdmi->audio_mutex);
 553 }
 554
 555 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 556 {
 557         mutex_lock(&hdmi->audio_mutex);
 558         hdmi->sample_rate = rate;
 559         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 560                                  hdmi->sample_rate);
 561         mutex_unlock(&hdmi->audio_mutex);
 562 }
 563 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 564
 565 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
 566 {
 567         if (enable)
 568                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 569         else
 570                 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 571         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
 572 }
 573
 574 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 575 {
 576         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 577 }
 578
 579 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
 580 {
 581         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 582 }
 583
 584 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
 585 {
 586         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 587         hdmi_enable_audio_clk(hdmi, true);
 588 }
 589
 590 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
 591 {
 592         hdmi_enable_audio_clk(hdmi, false);
 593 }
 594
 595 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 596 {
 597         unsigned long flags;
 598
 599         spin_lock_irqsave(&hdmi->audio_lock, flags);
 600         hdmi->audio_enable = true;
 601         if (hdmi->enable_audio)
 602                 hdmi->enable_audio(hdmi);
 603         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 604 }
 605 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 606
 607 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 608 {
 609         unsigned long flags;
 610
 611         spin_lock_irqsave(&hdmi->audio_lock, flags);
 612         hdmi->audio_enable = false;
 613         if (hdmi->disable_audio)
 614                 hdmi->disable_audio(hdmi);
 615         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 616 }
 617 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 618
 619 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
 620 {
 621         switch (bus_format) {
 622         case MEDIA_BUS_FMT_RGB888_1X24:
 623         case MEDIA_BUS_FMT_RGB101010_1X30:
 624         case MEDIA_BUS_FMT_RGB121212_1X36:
 625         case MEDIA_BUS_FMT_RGB161616_1X48:
 626                 return true;
 627
 628         default:
 629                 return false;
 630         }
 631 }
 632
 633 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
 634 {
 635         switch (bus_format) {
 636         case MEDIA_BUS_FMT_YUV8_1X24:
 637         case MEDIA_BUS_FMT_YUV10_1X30:
 638         case MEDIA_BUS_FMT_YUV12_1X36:
 639         case MEDIA_BUS_FMT_YUV16_1X48:
 640                 return true;
 641
 642         default:
 643                 return false;
 644         }
 645 }
 646
 647 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
 648 {
 649         switch (bus_format) {
 650         case MEDIA_BUS_FMT_UYVY8_1X16:
 651         case MEDIA_BUS_FMT_UYVY10_1X20:
 652         case MEDIA_BUS_FMT_UYVY12_1X24:
 653                 return true;
 654
 655         default:
 656                 return false;
 657         }
 658 }
 659
 660 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
 661 {
 662         switch (bus_format) {
 663         case MEDIA_BUS_FMT_RGB888_1X24:
 664         case MEDIA_BUS_FMT_YUV8_1X24:
 665         case MEDIA_BUS_FMT_UYVY8_1X16:
 666         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 667                 return 8;
 668
 669         case MEDIA_BUS_FMT_RGB101010_1X30:
 670         case MEDIA_BUS_FMT_YUV10_1X30:
 671         case MEDIA_BUS_FMT_UYVY10_1X20:
 672         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 673                 return 10;
 674
 675         case MEDIA_BUS_FMT_RGB121212_1X36:
 676         case MEDIA_BUS_FMT_YUV12_1X36:
 677         case MEDIA_BUS_FMT_UYVY12_1X24:
 678         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 679                 return 12;
 680
 681         case MEDIA_BUS_FMT_RGB161616_1X48:
 682         case MEDIA_BUS_FMT_YUV16_1X48:
 683         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 684                 return 16;
 685
 686         default:
 687                 return 0;
 688         }
 689 }
 690
 691 /*
 692  * this submodule is responsible for the video data synchronization.
 693  * for example, for RGB 4:4:4 input, the data map is defined as
 694  *                      pin{47~40} <==> R[7:0]
 695  *                      pin{31~24} <==> G[7:0]
 696  *                      pin{15~8}  <==> B[7:0]
 697  */
 698 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 699 {
 700         int color_format = 0;
 701         u8 val;
 702
 703         switch (hdmi->hdmi_data.enc_in_bus_format) {
 704         case MEDIA_BUS_FMT_RGB888_1X24:
 705                 color_format = 0x01;
 706                 break;
 707         case MEDIA_BUS_FMT_RGB101010_1X30:
 708                 color_format = 0x03;
 709                 break;
 710         case MEDIA_BUS_FMT_RGB121212_1X36:
 711                 color_format = 0x05;
 712                 break;
 713         case MEDIA_BUS_FMT_RGB161616_1X48:
 714                 color_format = 0x07;
 715                 break;
 716
 717         case MEDIA_BUS_FMT_YUV8_1X24:
 718         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 719                 color_format = 0x09;
 720                 break;
 721         case MEDIA_BUS_FMT_YUV10_1X30:
 722         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 723                 color_format = 0x0B;
 724                 break;
 725         case MEDIA_BUS_FMT_YUV12_1X36:
 726         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 727                 color_format = 0x0D;
 728                 break;
 729         case MEDIA_BUS_FMT_YUV16_1X48:
 730         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 731                 color_format = 0x0F;
 732                 break;
 733
 734         case MEDIA_BUS_FMT_UYVY8_1X16:
 735                 color_format = 0x16;
 736                 break;
 737         case MEDIA_BUS_FMT_UYVY10_1X20:
 738                 color_format = 0x14;
 739                 break;
 740         case MEDIA_BUS_FMT_UYVY12_1X24:
 741                 color_format = 0x12;
 742                 break;
 743
 744         default:
 745                 return;
 746         }
 747
 748         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 749                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 750                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 751         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 752
 753         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 754         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 755                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 756                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 757         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 758         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 759         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 760         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 761         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 762         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 763         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 764 }
 765
 766 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 767 {
 768         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
 769 }
 770
 771 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 772 {
 773         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
 774                 return 0;
 775
 776         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
 777             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
 778                 return 1;
 779
 780         return 0;
 781 }
 782
 783 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 784 {
 785         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
 786                 return 0;
 787
 788         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 789             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
 790                 return 1;
 791
 792         return 0;
 793 }
 794
 795 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 796 {
 797         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 798         unsigned i;
 799         u32 csc_scale = 1;
 800
 801         if (is_color_space_conversion(hdmi)) {
 802                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
 803                         if (hdmi->hdmi_data.enc_out_encoding ==
 804                                                 V4L2_YCBCR_ENC_601)
 805                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 806                         else
 807                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 808                 } else if (hdmi_bus_fmt_is_rgb(
 809                                         hdmi->hdmi_data.enc_in_bus_format)) {
 810                         if (hdmi->hdmi_data.enc_out_encoding ==
 811                                                 V4L2_YCBCR_ENC_601)
 812                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 813                         else
 814                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 815                         csc_scale = 0;
 816                 }
 817         }
 818
 819         /* The CSC registers are sequential, alternating MSB then LSB */
 820         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 821                 u16 coeff_a = (*csc_coeff)[0][i];
 822                 u16 coeff_b = (*csc_coeff)[1][i];
 823                 u16 coeff_c = (*csc_coeff)[2][i];
 824
 825                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 826                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 827                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 828                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 829                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 830                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 831         }
 832
 833         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 834                   HDMI_CSC_SCALE);
 835 }
 836
 837 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 838 {
 839         int color_depth = 0;
 840         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 841         int decimation = 0;
 842
 843         /* YCC422 interpolation to 444 mode */
 844         if (is_color_space_interpolation(hdmi))
 845                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 846         else if (is_color_space_decimation(hdmi))
 847                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 848
 849         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
 850         case 8:
 851                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 852                 break;
 853         case 10:
 854                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 855                 break;
 856         case 12:
 857                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 858                 break;
 859         case 16:
 860                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 861                 break;
 862
 863         default:
 864                 return;
 865         }
 866
 867         /* Configure the CSC registers */
 868         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 869         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 870                   HDMI_CSC_SCALE);
 871
 872         dw_hdmi_update_csc_coeffs(hdmi);
 873 }
 874
 875 /*
 876  * HDMI video packetizer is used to packetize the data.
 877  * for example, if input is YCC422 mode or repeater is used,
 878  * data should be repacked this module can be bypassed.
 879  */
 880 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 881 {
 882         unsigned int color_depth = 0;
 883         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 884         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 885         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 886         u8 val, vp_conf;
 887
 888         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 889             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
 890                 switch (hdmi_bus_fmt_color_depth(
 891                                         hdmi->hdmi_data.enc_out_bus_format)) {
 892                 case 8:
 893                         color_depth = 4;
 894                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 895                         break;
 896                 case 10:
 897                         color_depth = 5;
 898                         break;
 899                 case 12:
 900                         color_depth = 6;
 901                         break;
 902                 case 16:
 903                         color_depth = 7;
 904                         break;
 905                 default:
 906                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 907                 }
 908         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
 909                 switch (hdmi_bus_fmt_color_depth(
 910                                         hdmi->hdmi_data.enc_out_bus_format)) {
 911                 case 0:
 912                 case 8:
 913                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 914                         break;
 915                 case 10:
 916                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 917                         break;
 918                 case 12:
 919                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 920                         break;
 921
 922                 default:
 923                         return;
 924                 }
 925                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 926         } else {
 927                 return;
 928         }
 929
 930         /* set the packetizer registers */
 931         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 932                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 933                 ((hdmi_data->pix_repet_factor <<
 934                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 935                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 936         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 937
 938         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 939                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 940
 941         /* Data from pixel repeater block */
 942         if (hdmi_data->pix_repet_factor > 1) {
 943                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 944                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 945         } else { /* data from packetizer block */
 946                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 947                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 948         }
 949
 950         hdmi_modb(hdmi, vp_conf,
 951                   HDMI_VP_CONF_PR_EN_MASK |
 952                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 953
 954         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 955                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 956
 957         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 958
 959         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 960                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 961                           HDMI_VP_CONF_PP_EN_ENABLE |
 962                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 963         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 964                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 965                           HDMI_VP_CONF_PP_EN_DISABLE |
 966                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 967         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 968                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 969                           HDMI_VP_CONF_PP_EN_DISABLE |
 970                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 971         } else {
 972                 return;
 973         }
 974
 975         hdmi_modb(hdmi, vp_conf,
 976                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 977                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 978
 979         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 980                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 981                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 982                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 983
 984         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 985                   HDMI_VP_CONF);
 986 }
 987
 988 /* -----------------------------------------------------------------------------
 989  * Synopsys PHY Handling
 990  */
 991
 992 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 993                                        unsigned char bit)
 994 {
 995         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 996                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 997 }
 998
 999 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1000 {
1001         u32 val;
1002
1003         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1004                 if (msec-- == 0)
1005                         return false;
1006                 udelay(1000);
1007         }
1008         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1009
1010         return true;
1011 }
1012
1013 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1014                            unsigned char addr)
1015 {
1016         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1017         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1018         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1019                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1020         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1021                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1022         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1023                     HDMI_PHY_I2CM_OPERATION_ADDR);
1024         hdmi_phy_wait_i2c_done(hdmi, 1000);
1025 }
1026 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1027
1028 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1029 {
1030         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1031                          HDMI_PHY_CONF0_PDZ_OFFSET,
1032                          HDMI_PHY_CONF0_PDZ_MASK);
1033 }
1034
1035 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1036 {
1037         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1038                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1039                          HDMI_PHY_CONF0_ENTMDS_MASK);
1040 }
1041
1042 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1043 {
1044         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1045                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1046                          HDMI_PHY_CONF0_SVSRET_MASK);
1047 }
1048
1049 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1050 {
1051         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1052                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1053                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1054 }
1055
1056 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1057 {
1058         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1059                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1060                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1061 }
1062
1063 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1064 {
1065         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1066                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1067                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1068 }
1069
1070 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1071 {
1072         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1073                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1074                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1075 }
1076
1077 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1078 {
1079         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1080         unsigned int i;
1081         u16 val;
1082
1083         if (phy->gen == 1) {
1084                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1085                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1086                 return;
1087         }
1088
1089         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1090
1091         /*
1092          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1093          * to low power mode.
1094          */
1095         for (i = 0; i < 5; ++i) {
1096                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1097                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1098                         break;
1099
1100                 usleep_range(1000, 2000);
1101         }
1102
1103         if (val & HDMI_PHY_TX_PHY_LOCK)
1104                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1105         else
1106                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1107
1108         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1109 }
1110
1111 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1112 {
1113         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1114         unsigned int i;
1115         u8 val;
1116
1117         if (phy->gen == 1) {
1118                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1119
1120                 /* Toggle TMDS enable. */
1121                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1122                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1123                 return 0;
1124         }
1125
1126         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1127         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1128
1129         /* Wait for PHY PLL lock */
1130         for (i = 0; i < 5; ++i) {
1131                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1132                 if (val)
1133                         break;
1134
1135                 usleep_range(1000, 2000);
1136         }
1137
1138         if (!val) {
1139                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1140                 return -ETIMEDOUT;
1141         }
1142
1143         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1144         return 0;
1145 }
1146
1147 /*
1148  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1149  * information the DWC MHL PHY has the same register layout and is thus also
1150  * supported by this function.
1151  */
1152 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1153                 const struct dw_hdmi_plat_data *pdata,
1154                 unsigned long mpixelclock)
1155 {
1156         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1157         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1158         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1159
1160         /* PLL/MPLL Cfg - always match on final entry */
1161         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1162                 if (mpixelclock <= mpll_config->mpixelclock)
1163                         break;
1164
1165         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1166                 if (mpixelclock <= curr_ctrl->mpixelclock)
1167                         break;
1168
1169         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1170                 if (mpixelclock <= phy_config->mpixelclock)
1171                         break;
1172
1173         if (mpll_config->mpixelclock == ~0UL ||
1174             curr_ctrl->mpixelclock == ~0UL ||
1175             phy_config->mpixelclock == ~0UL)
1176                 return -EINVAL;
1177
1178         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1179                               HDMI_3D_TX_PHY_CPCE_CTRL);
1180         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1181                               HDMI_3D_TX_PHY_GMPCTRL);
1182         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1183                               HDMI_3D_TX_PHY_CURRCTRL);
1184
1185         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1186         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1187                               HDMI_3D_TX_PHY_MSM_CTRL);
1188
1189         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1190         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1191                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1192         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1193                               HDMI_3D_TX_PHY_VLEVCTRL);
1194
1195         /* Override and disable clock termination. */
1196         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1197                               HDMI_3D_TX_PHY_CKCALCTRL);
1198
1199         return 0;
1200 }
1201
1202 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1203 {
1204         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1205         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1206         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1207         int ret;
1208
1209         dw_hdmi_phy_power_off(hdmi);
1210
1211         /* Leave low power consumption mode by asserting SVSRET. */
1212         if (phy->has_svsret)
1213                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1214
1215         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1216         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1217         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1218
1219         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1220
1221         hdmi_phy_test_clear(hdmi, 1);
1222         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1223                     HDMI_PHY_I2CM_SLAVE_ADDR);
1224         hdmi_phy_test_clear(hdmi, 0);
1225
1226         /* Write to the PHY as configured by the platform */
1227         if (pdata->configure_phy)
1228                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1229         else
1230                 ret = phy->configure(hdmi, pdata, mpixelclock);
1231         if (ret) {
1232                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1233                         mpixelclock);
1234                 return ret;
1235         }
1236
1237         return dw_hdmi_phy_power_on(hdmi);
1238 }
1239
1240 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1241                             struct drm_display_mode *mode)
1242 {
1243         int i, ret;
1244
1245         /* HDMI Phy spec says to do the phy initialization sequence twice */
1246         for (i = 0; i < 2; i++) {
1247                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1248                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1249
1250                 ret = hdmi_phy_configure(hdmi);
1251                 if (ret)
1252                         return ret;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1259 {
1260         dw_hdmi_phy_power_off(hdmi);
1261 }
1262
1263 static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1264                                                       void *data)
1265 {
1266         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1267                 connector_status_connected : connector_status_disconnected;
1268 }
1269
1270 static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1271                                    bool force, bool disabled, bool rxsense)
1272 {
1273         u8 old_mask = hdmi->phy_mask;
1274
1275         if (force || disabled || !rxsense)
1276                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1277         else
1278                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1279
1280         if (old_mask != hdmi->phy_mask)
1281                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1282 }
1283
1284 static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1285 {
1286         /*
1287          * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1288          * any pending interrupt.
1289          */
1290         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1291         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1292                     HDMI_IH_PHY_STAT0);
1293
1294         /* Enable cable hot plug irq. */
1295         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1296
1297         /* Clear and unmute interrupts. */
1298         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1299                     HDMI_IH_PHY_STAT0);
1300         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1301                     HDMI_IH_MUTE_PHY_STAT0);
1302 }
1303
1304 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1305         .init = dw_hdmi_phy_init,
1306         .disable = dw_hdmi_phy_disable,
1307         .read_hpd = dw_hdmi_phy_read_hpd,
1308         .update_hpd = dw_hdmi_phy_update_hpd,
1309         .setup_hpd = dw_hdmi_phy_setup_hpd,
1310 };
1311
1312 /* -----------------------------------------------------------------------------
1313  * HDMI TX Setup
1314  */
1315
1316 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1317 {
1318         u8 de;
1319
1320         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1321                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1322         else
1323                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1324
1325         /* disable rx detect */
1326         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1327                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1328
1329         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1330
1331         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1332                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1333 }
1334
1335 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1336 {
1337         struct hdmi_avi_infoframe frame;
1338         u8 val;
1339
1340         /* Initialise info frame from DRM mode */
1341         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1342
1343         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1344                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1345         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1346                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1347         else
1348                 frame.colorspace = HDMI_COLORSPACE_RGB;
1349
1350         /* Set up colorimetry */
1351         if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1352                 switch (hdmi->hdmi_data.enc_out_encoding) {
1353                 case V4L2_YCBCR_ENC_601:
1354                         if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1355                                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1356                         else
1357                                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1358                         frame.extended_colorimetry =
1359                                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1360                         break;
1361                 case V4L2_YCBCR_ENC_709:
1362                         if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1363                                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1364                         else
1365                                 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1366                         frame.extended_colorimetry =
1367                                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1368                         break;
1369                 default: /* Carries no data */
1370                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1371                         frame.extended_colorimetry =
1372                                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1373                         break;
1374                 }
1375         } else {
1376                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1377                 frame.extended_colorimetry =
1378                         HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1379         }
1380
1381         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1382
1383         /*
1384          * The Designware IP uses a different byte format from standard
1385          * AVI info frames, though generally the bits are in the correct
1386          * bytes.
1387          */
1388
1389         /*
1390          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1391          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1392          * bit 6 rather than 4.
1393          */
1394         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1395         if (frame.active_aspect & 15)
1396                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1397         if (frame.top_bar || frame.bottom_bar)
1398                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1399         if (frame.left_bar || frame.right_bar)
1400                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1401         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1402
1403         /* AVI data byte 2 differences: none */
1404         val = ((frame.colorimetry & 0x3) << 6) |
1405               ((frame.picture_aspect & 0x3) << 4) |
1406               (frame.active_aspect & 0xf);
1407         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1408
1409         /* AVI data byte 3 differences: none */
1410         val = ((frame.extended_colorimetry & 0x7) << 4) |
1411               ((frame.quantization_range & 0x3) << 2) |
1412               (frame.nups & 0x3);
1413         if (frame.itc)
1414                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1415         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1416
1417         /* AVI data byte 4 differences: none */
1418         val = frame.video_code & 0x7f;
1419         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1420
1421         /* AVI Data Byte 5- set up input and output pixel repetition */
1422         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1423                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1424                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1425                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1426                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1427                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1428         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1429
1430         /*
1431          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1432          * ycc range in bits 2,3 rather than 6,7
1433          */
1434         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1435               (frame.content_type & 0x3);
1436         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1437
1438         /* AVI Data Bytes 6-13 */
1439         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1440         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1441         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1442         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1443         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1444         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1445         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1446         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1447 }
1448
1449 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1450                                                  struct drm_display_mode *mode)
1451 {
1452         struct hdmi_vendor_infoframe frame;
1453         u8 buffer[10];
1454         ssize_t err;
1455
1456         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1457         if (err < 0)
1458                 /*
1459                  * Going into that statement does not means vendor infoframe
1460                  * fails. It just informed us that vendor infoframe is not
1461                  * needed for the selected mode. Only 4k or stereoscopic 3D
1462                  * mode requires vendor infoframe. So just simply return.
1463                  */
1464                 return;
1465
1466         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1467         if (err < 0) {
1468                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1469                         err);
1470                 return;
1471         }
1472         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1473                         HDMI_FC_DATAUTO0_VSD_MASK);
1474
1475         /* Set the length of HDMI vendor specific InfoFrame payload */
1476         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1477
1478         /* Set 24bit IEEE Registration Identifier */
1479         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1480         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1481         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1482
1483         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1484         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1485         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1486
1487         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1488                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1489
1490         /* Packet frame interpolation */
1491         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1492
1493         /* Auto packets per frame and line spacing */
1494         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1495
1496         /* Configures the Frame Composer On RDRB mode */
1497         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1498                         HDMI_FC_DATAUTO0_VSD_MASK);
1499 }
1500
1501 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1502                              const struct drm_display_mode *mode)
1503 {
1504         u8 inv_val;
1505         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1506         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1507         unsigned int vdisplay;
1508
1509         vmode->mpixelclock = mode->clock * 1000;
1510
1511         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1512
1513         /* Set up HDMI_FC_INVIDCONF */
1514         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1515                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1516                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1517
1518         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1519                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1520                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1521
1522         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1523                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1524                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1525
1526         inv_val |= (vmode->mdataenablepolarity ?
1527                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1528                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1529
1530         if (hdmi->vic == 39)
1531                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1532         else
1533                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1534                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1535                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1536
1537         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1538                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1539                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1540
1541         inv_val |= hdmi->sink_is_hdmi ?
1542                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1543                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1544
1545         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1546
1547         vdisplay = mode->vdisplay;
1548         vblank = mode->vtotal - mode->vdisplay;
1549         v_de_vs = mode->vsync_start - mode->vdisplay;
1550         vsync_len = mode->vsync_end - mode->vsync_start;
1551
1552         /*
1553          * When we're setting an interlaced mode, we need
1554          * to adjust the vertical timing to suit.
1555          */
1556         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1557                 vdisplay /= 2;
1558                 vblank /= 2;
1559                 v_de_vs /= 2;
1560                 vsync_len /= 2;
1561         }
1562
1563         /* Set up horizontal active pixel width */
1564         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1565         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1566
1567         /* Set up vertical active lines */
1568         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1569         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1570
1571         /* Set up horizontal blanking pixel region width */
1572         hblank = mode->htotal - mode->hdisplay;
1573         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1574         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1575
1576         /* Set up vertical blanking pixel region width */
1577         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1578
1579         /* Set up HSYNC active edge delay width (in pixel clks) */
1580         h_de_hs = mode->hsync_start - mode->hdisplay;
1581         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1582         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1583
1584         /* Set up VSYNC active edge delay (in lines) */
1585         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1586
1587         /* Set up HSYNC active pulse width (in pixel clks) */
1588         hsync_len = mode->hsync_end - mode->hsync_start;
1589         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1590         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1591
1592         /* Set up VSYNC active edge delay (in lines) */
1593         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1594 }
1595
1596 /* HDMI Initialization Step B.4 */
1597 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1598 {
1599         /* control period minimum duration */
1600         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1601         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1602         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1603
1604         /* Set to fill TMDS data channels */
1605         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1606         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1607         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1608
1609         /* Enable pixel clock and tmds data path */
1610         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1611                            HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1612                            HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1613                            HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1614                            HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1615         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1616         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1617
1618         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1619         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1620
1621         /* Enable csc path */
1622         if (is_color_space_conversion(hdmi)) {
1623                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1624                 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1625         }
1626
1627         /* Enable color space conversion if needed */
1628         if (is_color_space_conversion(hdmi))
1629                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1630                             HDMI_MC_FLOWCTRL);
1631         else
1632                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1633                             HDMI_MC_FLOWCTRL);
1634 }
1635
1636 /* Workaround to clear the overflow condition */
1637 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1638 {
1639         unsigned int count;
1640         unsigned int i;
1641         u8 val;
1642
1643         /*
1644          * Under some circumstances the Frame Composer arithmetic unit can miss
1645          * an FC register write due to being busy processing the previous one.
1646          * The issue can be worked around by issuing a TMDS software reset and
1647          * then write one of the FC registers several times.
1648          *
1649          * The number of iterations matters and depends on the HDMI TX revision
1650          * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1651          * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1652          * 4 and 1 iterations respectively.
1653          * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1654          * the workaround with a single iteration.
1655          */
1656
1657         switch (hdmi->version) {
1658         case 0x130a:
1659                 count = 4;
1660                 break;
1661         case 0x131a:
1662         case 0x201a:
1663                 count = 1;
1664                 break;
1665         default:
1666                 return;
1667         }
1668
1669         /* TMDS software reset */
1670         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1671
1672         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1673         for (i = 0; i < count; i++)
1674                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1675 }
1676
1677 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1678 {
1679         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1680         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1681 }
1682
1683 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1684 {
1685         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1686                     HDMI_IH_MUTE_FC_STAT2);
1687 }
1688
1689 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1690 {
1691         int ret;
1692
1693         hdmi_disable_overflow_interrupts(hdmi);
1694
1695         hdmi->vic = drm_match_cea_mode(mode);
1696
1697         if (!hdmi->vic) {
1698                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1699         } else {
1700                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1701         }
1702
1703         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1704             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1705             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1706             (hdmi->vic == 17) || (hdmi->vic == 18))
1707                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1708         else
1709                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1710
1711         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1712         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1713
1714         /* TOFIX: Get input format from plat data or fallback to RGB888 */
1715         if (hdmi->plat_data->input_bus_format)
1716                 hdmi->hdmi_data.enc_in_bus_format =
1717                         hdmi->plat_data->input_bus_format;
1718         else
1719                 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1720
1721         /* TOFIX: Get input encoding from plat data or fallback to none */
1722         if (hdmi->plat_data->input_bus_encoding)
1723                 hdmi->hdmi_data.enc_in_encoding =
1724                         hdmi->plat_data->input_bus_encoding;
1725         else
1726                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1727
1728         /* TOFIX: Default to RGB888 output format */
1729         hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1730
1731         hdmi->hdmi_data.pix_repet_factor = 0;
1732         hdmi->hdmi_data.hdcp_enable = 0;
1733         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1734
1735         /* HDMI Initialization Step B.1 */
1736         hdmi_av_composer(hdmi, mode);
1737
1738         /* HDMI Initializateion Step B.2 */
1739         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1740         if (ret)
1741                 return ret;
1742         hdmi->phy.enabled = true;
1743
1744         /* HDMI Initialization Step B.3 */
1745         dw_hdmi_enable_video_path(hdmi);
1746
1747         if (hdmi->sink_has_audio) {
1748                 dev_dbg(hdmi->dev, "sink has audio support\n");
1749
1750                 /* HDMI Initialization Step E - Configure audio */
1751                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1752                 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
1753         }
1754
1755         /* not for DVI mode */
1756         if (hdmi->sink_is_hdmi) {
1757                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1758
1759                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1760                 hdmi_config_AVI(hdmi, mode);
1761                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1762         } else {
1763                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1764         }
1765
1766         hdmi_video_packetize(hdmi);
1767         hdmi_video_csc(hdmi);
1768         hdmi_video_sample(hdmi);
1769         hdmi_tx_hdcp_config(hdmi);
1770
1771         dw_hdmi_clear_overflow(hdmi);
1772         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1773                 hdmi_enable_overflow_interrupts(hdmi);
1774
1775         return 0;
1776 }
1777
1778 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
1779 {
1780         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1781                     HDMI_PHY_I2CM_INT_ADDR);
1782
1783         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1784                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1785                     HDMI_PHY_I2CM_CTLINT_ADDR);
1786 }
1787
1788 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1789 {
1790         u8 ih_mute;
1791
1792         /*
1793          * Boot up defaults are:
1794          * HDMI_IH_MUTE   = 0x03 (disabled)
1795          * HDMI_IH_MUTE_* = 0x00 (enabled)
1796          *
1797          * Disable top level interrupt bits in HDMI block
1798          */
1799         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1800                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1801                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1802
1803         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1804
1805         /* by default mask all interrupts */
1806         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1807         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1808         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1809         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1810         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1811         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1812         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1813         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1814         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1815         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1816         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1817         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1818         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1819         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1820
1821         /* Disable interrupts in the IH_MUTE_* registers */
1822         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1823         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1824         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1825         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1826         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1827         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1828         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1829         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1830         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1831         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1832
1833         /* Enable top level interrupt bits in HDMI block */
1834         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1835                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1836         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1837 }
1838
1839 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1840 {
1841         hdmi->bridge_is_on = true;
1842         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1843 }
1844
1845 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1846 {
1847         if (hdmi->phy.enabled) {
1848                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1849                 hdmi->phy.enabled = false;
1850         }
1851
1852         hdmi->bridge_is_on = false;
1853 }
1854
1855 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1856 {
1857         int force = hdmi->force;
1858
1859         if (hdmi->disabled) {
1860                 force = DRM_FORCE_OFF;
1861         } else if (force == DRM_FORCE_UNSPECIFIED) {
1862                 if (hdmi->rxsense)
1863                         force = DRM_FORCE_ON;
1864                 else
1865                         force = DRM_FORCE_OFF;
1866         }
1867
1868         if (force == DRM_FORCE_OFF) {
1869                 if (hdmi->bridge_is_on)
1870                         dw_hdmi_poweroff(hdmi);
1871         } else {
1872                 if (!hdmi->bridge_is_on)
1873                         dw_hdmi_poweron(hdmi);
1874         }
1875 }
1876
1877 /*
1878  * Adjust the detection of RXSENSE according to whether we have a forced
1879  * connection mode enabled, or whether we have been disabled.  There is
1880  * no point processing RXSENSE interrupts if we have a forced connection
1881  * state, or DRM has us disabled.
1882  *
1883  * We also disable rxsense interrupts when we think we're disconnected
1884  * to avoid floating TDMS signals giving false rxsense interrupts.
1885  *
1886  * Note: we still need to listen for HPD interrupts even when DRM has us
1887  * disabled so that we can detect a connect event.
1888  */
1889 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1890 {
1891         if (hdmi->phy.ops->update_hpd)
1892                 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
1893                                           hdmi->force, hdmi->disabled,
1894                                           hdmi->rxsense);
1895 }
1896
1897 static enum drm_connector_status
1898 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1899 {
1900         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1901                                              connector);
1902
1903         mutex_lock(&hdmi->mutex);
1904         hdmi->force = DRM_FORCE_UNSPECIFIED;
1905         dw_hdmi_update_power(hdmi);
1906         dw_hdmi_update_phy_mask(hdmi);
1907         mutex_unlock(&hdmi->mutex);
1908
1909         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1910 }
1911
1912 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1913 {
1914         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1915                                              connector);
1916         struct edid *edid;
1917         int ret = 0;
1918
1919         if (!hdmi->ddc)
1920                 return 0;
1921
1922         edid = drm_get_edid(connector, hdmi->ddc);
1923         if (edid) {
1924                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1925                         edid->width_cm, edid->height_cm);
1926
1927                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1928                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1929                 drm_mode_connector_update_edid_property(connector, edid);
1930                 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
1931                 ret = drm_add_edid_modes(connector, edid);
1932                 /* Store the ELD */
1933                 drm_edid_to_eld(connector, edid);
1934                 kfree(edid);
1935         } else {
1936                 dev_dbg(hdmi->dev, "failed to get edid\n");
1937         }
1938
1939         return ret;
1940 }
1941
1942 static void dw_hdmi_connector_force(struct drm_connector *connector)
1943 {
1944         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1945                                              connector);
1946
1947         mutex_lock(&hdmi->mutex);
1948         hdmi->force = connector->force;
1949         dw_hdmi_update_power(hdmi);
1950         dw_hdmi_update_phy_mask(hdmi);
1951         mutex_unlock(&hdmi->mutex);
1952 }
1953
1954 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1955         .fill_modes = drm_helper_probe_single_connector_modes,
1956         .detect = dw_hdmi_connector_detect,
1957         .destroy = drm_connector_cleanup,
1958         .force = dw_hdmi_connector_force,
1959         .reset = drm_atomic_helper_connector_reset,
1960         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1961         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1962 };
1963
1964 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1965         .get_modes = dw_hdmi_connector_get_modes,
1966         .best_encoder = drm_atomic_helper_best_encoder,
1967 };
1968
1969 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1970 {
1971         struct dw_hdmi *hdmi = bridge->driver_private;
1972         struct drm_encoder *encoder = bridge->encoder;
1973         struct drm_connector *connector = &hdmi->connector;
1974
1975         connector->interlace_allowed = 1;
1976         connector->polled = DRM_CONNECTOR_POLL_HPD;
1977
1978         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1979
1980         drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1981                            DRM_MODE_CONNECTOR_HDMIA);
1982
1983         drm_mode_connector_attach_encoder(connector, encoder);
1984
1985         return 0;
1986 }
1987
1988 static enum drm_mode_status
1989 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1990                           const struct drm_display_mode *mode)
1991 {
1992         struct dw_hdmi *hdmi = bridge->driver_private;
1993         struct drm_connector *connector = &hdmi->connector;
1994         enum drm_mode_status mode_status = MODE_OK;
1995
1996         /* We don't support double-clocked modes */
1997         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1998                 return MODE_BAD;
1999
2000         if (hdmi->plat_data->mode_valid)
2001                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2002
2003         return mode_status;
2004 }
2005
2006 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2007                                     struct drm_display_mode *orig_mode,
2008                                     struct drm_display_mode *mode)
2009 {
2010         struct dw_hdmi *hdmi = bridge->driver_private;
2011
2012         mutex_lock(&hdmi->mutex);
2013
2014         /* Store the display mode for plugin/DKMS poweron events */
2015         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2016
2017         mutex_unlock(&hdmi->mutex);
2018 }
2019
2020 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2021 {
2022         struct dw_hdmi *hdmi = bridge->driver_private;
2023
2024         mutex_lock(&hdmi->mutex);
2025         hdmi->disabled = true;
2026         dw_hdmi_update_power(hdmi);
2027         dw_hdmi_update_phy_mask(hdmi);
2028         mutex_unlock(&hdmi->mutex);
2029 }
2030
2031 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2032 {
2033         struct dw_hdmi *hdmi = bridge->driver_private;
2034
2035         mutex_lock(&hdmi->mutex);
2036         hdmi->disabled = false;
2037         dw_hdmi_update_power(hdmi);
2038         dw_hdmi_update_phy_mask(hdmi);
2039         mutex_unlock(&hdmi->mutex);
2040 }
2041
2042 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2043         .attach = dw_hdmi_bridge_attach,
2044         .enable = dw_hdmi_bridge_enable,
2045         .disable = dw_hdmi_bridge_disable,
2046         .mode_set = dw_hdmi_bridge_mode_set,
2047         .mode_valid = dw_hdmi_bridge_mode_valid,
2048 };
2049
2050 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2051 {
2052         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2053         unsigned int stat;
2054
2055         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2056         if (!stat)
2057                 return IRQ_NONE;
2058
2059         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2060
2061         i2c->stat = stat;
2062
2063         complete(&i2c->cmp);
2064
2065         return IRQ_HANDLED;
2066 }
2067
2068 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2069 {
2070         struct dw_hdmi *hdmi = dev_id;
2071         u8 intr_stat;
2072         irqreturn_t ret = IRQ_NONE;
2073
2074         if (hdmi->i2c)
2075                 ret = dw_hdmi_i2c_irq(hdmi);
2076
2077         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2078         if (intr_stat) {
2079                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2080                 return IRQ_WAKE_THREAD;
2081         }
2082
2083         return ret;
2084 }
2085
2086 void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2087 {
2088         mutex_lock(&hdmi->mutex);
2089
2090         if (!hdmi->force) {
2091                 /*
2092                  * If the RX sense status indicates we're disconnected,
2093                  * clear the software rxsense status.
2094                  */
2095                 if (!rx_sense)
2096                         hdmi->rxsense = false;
2097
2098                 /*
2099                  * Only set the software rxsense status when both
2100                  * rxsense and hpd indicates we're connected.
2101                  * This avoids what seems to be bad behaviour in
2102                  * at least iMX6S versions of the phy.
2103                  */
2104                 if (hpd)
2105                         hdmi->rxsense = true;
2106
2107                 dw_hdmi_update_power(hdmi);
2108                 dw_hdmi_update_phy_mask(hdmi);
2109         }
2110         mutex_unlock(&hdmi->mutex);
2111 }
2112
2113 void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense)
2114 {
2115         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2116
2117         __dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense);
2118 }
2119 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2120
2121 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2122 {
2123         struct dw_hdmi *hdmi = dev_id;
2124         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2125
2126         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2127         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2128         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2129
2130         phy_pol_mask = 0;
2131         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2132                 phy_pol_mask |= HDMI_PHY_HPD;
2133         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2134                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2135         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2136                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2137         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2138                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2139         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2140                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2141
2142         if (phy_pol_mask)
2143                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2144
2145         /*
2146          * RX sense tells us whether the TDMS transmitters are detecting
2147          * load - in other words, there's something listening on the
2148          * other end of the link.  Use this to decide whether we should
2149          * power on the phy as HPD may be toggled by the sink to merely
2150          * ask the source to re-read the EDID.
2151          */
2152         if (intr_stat &
2153             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2154                 __dw_hdmi_setup_rx_sense(hdmi,
2155                                          phy_stat & HDMI_PHY_HPD,
2156                                          phy_stat & HDMI_PHY_RX_SENSE);
2157
2158                 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2159                         cec_notifier_set_phys_addr(hdmi->cec_notifier,
2160                                                    CEC_PHYS_ADDR_INVALID);
2161         }
2162
2163         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2164                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2165                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2166                 if (hdmi->bridge.dev)
2167                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
2168         }
2169
2170         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2171         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2172                     HDMI_IH_MUTE_PHY_STAT0);
2173
2174         return IRQ_HANDLED;
2175 }
2176
2177 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2178         {
2179                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2180                 .name = "DWC HDMI TX PHY",
2181                 .gen = 1,
2182         }, {
2183                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2184                 .name = "DWC MHL PHY + HEAC PHY",
2185                 .gen = 2,
2186                 .has_svsret = true,
2187                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2188         }, {
2189                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2190                 .name = "DWC MHL PHY",
2191                 .gen = 2,
2192                 .has_svsret = true,
2193                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2194         }, {
2195                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2196                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2197                 .gen = 2,
2198                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2199         }, {
2200                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2201                 .name = "DWC HDMI 3D TX PHY",
2202                 .gen = 2,
2203                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2204         }, {
2205                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2206                 .name = "DWC HDMI 2.0 TX PHY",
2207                 .gen = 2,
2208                 .has_svsret = true,
2209                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2210         }, {
2211                 .type = DW_HDMI_PHY_VENDOR_PHY,
2212                 .name = "Vendor PHY",
2213         }
2214 };
2215
2216 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2217 {
2218         unsigned int i;
2219         u8 phy_type;
2220
2221         phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2222
2223         if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2224                 /* Vendor PHYs require support from the glue layer. */
2225                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2226                         dev_err(hdmi->dev,
2227                                 "Vendor HDMI PHY not supported by glue layer\n");
2228                         return -ENODEV;
2229                 }
2230
2231                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2232                 hdmi->phy.data = hdmi->plat_data->phy_data;
2233                 hdmi->phy.name = hdmi->plat_data->phy_name;
2234                 return 0;
2235         }
2236
2237         /* Synopsys PHYs are handled internally. */
2238         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2239                 if (dw_hdmi_phys[i].type == phy_type) {
2240                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2241                         hdmi->phy.name = dw_hdmi_phys[i].name;
2242                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2243
2244                         if (!dw_hdmi_phys[i].configure &&
2245                             !hdmi->plat_data->configure_phy) {
2246                                 dev_err(hdmi->dev, "%s requires platform support\n",
2247                                         hdmi->phy.name);
2248                                 return -ENODEV;
2249                         }
2250
2251                         return 0;
2252                 }
2253         }
2254
2255         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2256         return -ENODEV;
2257 }
2258
2259 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2260 {
2261         mutex_lock(&hdmi->mutex);
2262         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2263         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2264         mutex_unlock(&hdmi->mutex);
2265 }
2266
2267 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2268 {
2269         mutex_lock(&hdmi->mutex);
2270         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2271         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2272         mutex_unlock(&hdmi->mutex);
2273 }
2274
2275 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2276         .write = hdmi_writeb,
2277         .read = hdmi_readb,
2278         .enable = dw_hdmi_cec_enable,
2279         .disable = dw_hdmi_cec_disable,
2280 };
2281
2282 static const struct regmap_config hdmi_regmap_8bit_config = {
2283         .reg_bits       = 32,
2284         .val_bits       = 8,
2285         .reg_stride     = 1,
2286         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2287 };
2288
2289 static const struct regmap_config hdmi_regmap_32bit_config = {
2290         .reg_bits       = 32,
2291         .val_bits       = 32,
2292         .reg_stride     = 4,
2293         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2294 };
2295
2296 static struct dw_hdmi *
2297 __dw_hdmi_probe(struct platform_device *pdev,
2298                 const struct dw_hdmi_plat_data *plat_data)
2299 {
2300         struct device *dev = &pdev->dev;
2301         struct device_node *np = dev->of_node;
2302         struct platform_device_info pdevinfo;
2303         struct device_node *ddc_node;
2304         struct dw_hdmi_cec_data cec;
2305         struct dw_hdmi *hdmi;
2306         struct resource *iores = NULL;
2307         int irq;
2308         int ret;
2309         u32 val = 1;
2310         u8 prod_id0;
2311         u8 prod_id1;
2312         u8 config0;
2313         u8 config3;
2314
2315         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2316         if (!hdmi)
2317                 return ERR_PTR(-ENOMEM);
2318
2319         hdmi->plat_data = plat_data;
2320         hdmi->dev = dev;
2321         hdmi->sample_rate = 48000;
2322         hdmi->disabled = true;
2323         hdmi->rxsense = true;
2324         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2325         hdmi->mc_clkdis = 0x7f;
2326
2327         mutex_init(&hdmi->mutex);
2328         mutex_init(&hdmi->audio_mutex);
2329         spin_lock_init(&hdmi->audio_lock);
2330
2331         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2332         if (ddc_node) {
2333                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2334                 of_node_put(ddc_node);
2335                 if (!hdmi->ddc) {
2336                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2337                         return ERR_PTR(-EPROBE_DEFER);
2338                 }
2339
2340         } else {
2341                 dev_dbg(hdmi->dev, "no ddc property found\n");
2342         }
2343
2344         if (!plat_data->regm) {
2345                 const struct regmap_config *reg_config;
2346
2347                 of_property_read_u32(np, "reg-io-width", &val);
2348                 switch (val) {
2349                 case 4:
2350                         reg_config = &hdmi_regmap_32bit_config;
2351                         hdmi->reg_shift = 2;
2352                         break;
2353                 case 1:
2354                         reg_config = &hdmi_regmap_8bit_config;
2355                         break;
2356                 default:
2357                         dev_err(dev, "reg-io-width must be 1 or 4\n");
2358                         return ERR_PTR(-EINVAL);
2359                 }
2360
2361                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2362                 hdmi->regs = devm_ioremap_resource(dev, iores);
2363                 if (IS_ERR(hdmi->regs)) {
2364                         ret = PTR_ERR(hdmi->regs);
2365                         goto err_res;
2366                 }
2367
2368                 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2369                 if (IS_ERR(hdmi->regm)) {
2370                         dev_err(dev, "Failed to configure regmap\n");
2371                         ret = PTR_ERR(hdmi->regm);
2372                         goto err_res;
2373                 }
2374         } else {
2375                 hdmi->regm = plat_data->regm;
2376         }
2377
2378         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2379         if (IS_ERR(hdmi->isfr_clk)) {
2380                 ret = PTR_ERR(hdmi->isfr_clk);
2381                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2382                 goto err_res;
2383         }
2384
2385         ret = clk_prepare_enable(hdmi->isfr_clk);
2386         if (ret) {
2387                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2388                 goto err_res;
2389         }
2390
2391         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2392         if (IS_ERR(hdmi->iahb_clk)) {
2393                 ret = PTR_ERR(hdmi->iahb_clk);
2394                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2395                 goto err_isfr;
2396         }
2397
2398         ret = clk_prepare_enable(hdmi->iahb_clk);
2399         if (ret) {
2400                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2401                 goto err_isfr;
2402         }
2403
2404         /* Product and revision IDs */
2405         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2406                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2407         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2408         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2409
2410         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2411             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2412                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2413                         hdmi->version, prod_id0, prod_id1);
2414                 ret = -ENODEV;
2415                 goto err_iahb;
2416         }
2417
2418         ret = dw_hdmi_detect_phy(hdmi);
2419         if (ret < 0)
2420                 goto err_iahb;
2421
2422         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2423                  hdmi->version >> 12, hdmi->version & 0xfff,
2424                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2425                  hdmi->phy.name);
2426
2427         initialize_hdmi_ih_mutes(hdmi);
2428
2429         irq = platform_get_irq(pdev, 0);
2430         if (irq < 0) {
2431                 ret = irq;
2432                 goto err_iahb;
2433         }
2434
2435         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2436                                         dw_hdmi_irq, IRQF_SHARED,
2437                                         dev_name(dev), hdmi);
2438         if (ret)
2439                 goto err_iahb;
2440
2441         hdmi->cec_notifier = cec_notifier_get(dev);
2442         if (!hdmi->cec_notifier) {
2443                 ret = -ENOMEM;
2444                 goto err_iahb;
2445         }
2446
2447         /*
2448          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2449          * N and cts values before enabling phy
2450          */
2451         hdmi_init_clk_regenerator(hdmi);
2452
2453         /* If DDC bus is not specified, try to register HDMI I2C bus */
2454         if (!hdmi->ddc) {
2455                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2456                 if (IS_ERR(hdmi->ddc))
2457                         hdmi->ddc = NULL;
2458         }
2459
2460         hdmi->bridge.driver_private = hdmi;
2461         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2462 #ifdef CONFIG_OF
2463         hdmi->bridge.of_node = pdev->dev.of_node;
2464 #endif
2465
2466         dw_hdmi_setup_i2c(hdmi);
2467         if (hdmi->phy.ops->setup_hpd)
2468                 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2469
2470         memset(&pdevinfo, 0, sizeof(pdevinfo));
2471         pdevinfo.parent = dev;
2472         pdevinfo.id = PLATFORM_DEVID_AUTO;
2473
2474         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2475         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2476
2477         if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2478                 struct dw_hdmi_audio_data audio;
2479
2480                 audio.phys = iores->start;
2481                 audio.base = hdmi->regs;
2482                 audio.irq = irq;
2483                 audio.hdmi = hdmi;
2484                 audio.eld = hdmi->connector.eld;
2485                 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2486                 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2487
2488                 pdevinfo.name = "dw-hdmi-ahb-audio";
2489                 pdevinfo.data = &audio;
2490                 pdevinfo.size_data = sizeof(audio);
2491                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2492                 hdmi->audio = platform_device_register_full(&pdevinfo);
2493         } else if (config0 & HDMI_CONFIG0_I2S) {
2494                 struct dw_hdmi_i2s_audio_data audio;
2495
2496                 audio.hdmi      = hdmi;
2497                 audio.write     = hdmi_writeb;
2498                 audio.read      = hdmi_readb;
2499                 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2500                 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2501
2502                 pdevinfo.name = "dw-hdmi-i2s-audio";
2503                 pdevinfo.data = &audio;
2504                 pdevinfo.size_data = sizeof(audio);
2505                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2506                 hdmi->audio = platform_device_register_full(&pdevinfo);
2507         }
2508
2509         if (config0 & HDMI_CONFIG0_CEC) {
2510                 cec.hdmi = hdmi;
2511                 cec.ops = &dw_hdmi_cec_ops;
2512                 cec.irq = irq;
2513
2514                 pdevinfo.name = "dw-hdmi-cec";
2515                 pdevinfo.data = &cec;
2516                 pdevinfo.size_data = sizeof(cec);
2517                 pdevinfo.dma_mask = 0;
2518
2519                 hdmi->cec = platform_device_register_full(&pdevinfo);
2520         }
2521
2522         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2523         if (hdmi->i2c)
2524                 dw_hdmi_i2c_init(hdmi);
2525
2526         platform_set_drvdata(pdev, hdmi);
2527
2528         return hdmi;
2529
2530 err_iahb:
2531         if (hdmi->i2c) {
2532                 i2c_del_adapter(&hdmi->i2c->adap);
2533                 hdmi->ddc = NULL;
2534         }
2535
2536         if (hdmi->cec_notifier)
2537                 cec_notifier_put(hdmi->cec_notifier);
2538
2539         clk_disable_unprepare(hdmi->iahb_clk);
2540 err_isfr:
2541         clk_disable_unprepare(hdmi->isfr_clk);
2542 err_res:
2543         i2c_put_adapter(hdmi->ddc);
2544
2545         return ERR_PTR(ret);
2546 }
2547
2548 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2549 {
2550         if (hdmi->audio && !IS_ERR(hdmi->audio))
2551                 platform_device_unregister(hdmi->audio);
2552         if (!IS_ERR(hdmi->cec))
2553                 platform_device_unregister(hdmi->cec);
2554
2555         /* Disable all interrupts */
2556         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2557
2558         if (hdmi->cec_notifier)
2559                 cec_notifier_put(hdmi->cec_notifier);
2560
2561         clk_disable_unprepare(hdmi->iahb_clk);
2562         clk_disable_unprepare(hdmi->isfr_clk);
2563
2564         if (hdmi->i2c)
2565                 i2c_del_adapter(&hdmi->i2c->adap);
2566         else
2567                 i2c_put_adapter(hdmi->ddc);
2568 }
2569
2570 /* -----------------------------------------------------------------------------
2571  * Probe/remove API, used from platforms based on the DRM bridge API.
2572  */
2573 int dw_hdmi_probe(struct platform_device *pdev,
2574                   const struct dw_hdmi_plat_data *plat_data)
2575 {
2576         struct dw_hdmi *hdmi;
2577
2578         hdmi = __dw_hdmi_probe(pdev, plat_data);
2579         if (IS_ERR(hdmi))
2580                 return PTR_ERR(hdmi);
2581
2582         drm_bridge_add(&hdmi->bridge);
2583
2584         return 0;
2585 }
2586 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2587
2588 void dw_hdmi_remove(struct platform_device *pdev)
2589 {
2590         struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
2591
2592         drm_bridge_remove(&hdmi->bridge);
2593
2594         __dw_hdmi_remove(hdmi);
2595 }
2596 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2597
2598 /* -----------------------------------------------------------------------------
2599  * Bind/unbind API, used from platforms based on the component framework.
2600  */
2601 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2602                  const struct dw_hdmi_plat_data *plat_data)
2603 {
2604         struct dw_hdmi *hdmi;
2605         int ret;
2606
2607         hdmi = __dw_hdmi_probe(pdev, plat_data);
2608         if (IS_ERR(hdmi))
2609                 return PTR_ERR(hdmi);
2610
2611         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2612         if (ret) {
2613                 dw_hdmi_remove(pdev);
2614                 DRM_ERROR("Failed to initialize bridge with drm\n");
2615                 return ret;
2616         }
2617
2618         return 0;
2619 }
2620 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2621
2622 void dw_hdmi_unbind(struct device *dev)
2623 {
2624         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2625
2626         __dw_hdmi_remove(hdmi);
2627 }
2628 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2629
2630 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2631 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2632 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2633 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2634 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2635 MODULE_LICENSE("GPL");
2636 MODULE_ALIAS("platform:dw-hdmi");