drivers/gpu/drm/gma500/psb_irq.c

   1 /**************************************************************************
   2  * Copyright (c) 2007, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
  19  * develop this driver.
  20  *
  21  **************************************************************************/
  22 /*
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "psb_drv.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "power.h"
  30 #include "psb_irq.h"
  31 #include "mdfld_output.h"
  32
  33 /*
  34  * inline functions
  35  */
  36
  37 static inline u32
  38 psb_pipestat(int pipe)
  39 {
  40         if (pipe == 0)
  41                 return PIPEASTAT;
  42         if (pipe == 1)
  43                 return PIPEBSTAT;
  44         if (pipe == 2)
  45                 return PIPECSTAT;
  46         BUG();
  47 }
  48
  49 static inline u32
  50 mid_pipe_event(int pipe)
  51 {
  52         if (pipe == 0)
  53                 return _PSB_PIPEA_EVENT_FLAG;
  54         if (pipe == 1)
  55                 return _MDFLD_PIPEB_EVENT_FLAG;
  56         if (pipe == 2)
  57                 return _MDFLD_PIPEC_EVENT_FLAG;
  58         BUG();
  59 }
  60
  61 static inline u32
  62 mid_pipe_vsync(int pipe)
  63 {
  64         if (pipe == 0)
  65                 return _PSB_VSYNC_PIPEA_FLAG;
  66         if (pipe == 1)
  67                 return _PSB_VSYNC_PIPEB_FLAG;
  68         if (pipe == 2)
  69                 return _MDFLD_PIPEC_VBLANK_FLAG;
  70         BUG();
  71 }
  72
  73 static inline u32
  74 mid_pipeconf(int pipe)
  75 {
  76         if (pipe == 0)
  77                 return PIPEACONF;
  78         if (pipe == 1)
  79                 return PIPEBCONF;
  80         if (pipe == 2)
  81                 return PIPECCONF;
  82         BUG();
  83 }
  84
  85 void
  86 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  87 {
  88         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  89                 u32 reg = psb_pipestat(pipe);
  90                 dev_priv->pipestat[pipe] |= mask;
  91                 /* Enable the interrupt, clear any pending status */
  92                 if (gma_power_begin(dev_priv->dev, false)) {
  93                         u32 writeVal = PSB_RVDC32(reg);
  94                         writeVal |= (mask | (mask >> 16));
  95                         PSB_WVDC32(writeVal, reg);
  96                         (void) PSB_RVDC32(reg);
  97                         gma_power_end(dev_priv->dev);
  98                 }
  99         }
 100 }
 101
 102 void
 103 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
 104 {
 105         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 106                 u32 reg = psb_pipestat(pipe);
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 if (gma_power_begin(dev_priv->dev, false)) {
 109                         u32 writeVal = PSB_RVDC32(reg);
 110                         writeVal &= ~mask;
 111                         PSB_WVDC32(writeVal, reg);
 112                         (void) PSB_RVDC32(reg);
 113                         gma_power_end(dev_priv->dev);
 114                 }
 115         }
 116 }
 117
 118 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 119 {
 120         if (gma_power_begin(dev_priv->dev, false)) {
 121                 u32 pipe_event = mid_pipe_event(pipe);
 122                 dev_priv->vdc_irq_mask |= pipe_event;
 123                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 124                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 125                 gma_power_end(dev_priv->dev);
 126         }
 127 }
 128
 129 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 130 {
 131         if (dev_priv->pipestat[pipe] == 0) {
 132                 if (gma_power_begin(dev_priv->dev, false)) {
 133                         u32 pipe_event = mid_pipe_event(pipe);
 134                         dev_priv->vdc_irq_mask &= ~pipe_event;
 135                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 136                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 137                         gma_power_end(dev_priv->dev);
 138                 }
 139         }
 140 }
 141
 142 /**
 143  * Display controller interrupt handler for pipe event.
 144  *
 145  */
 146 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
 147 {
 148         struct drm_psb_private *dev_priv =
 149             (struct drm_psb_private *) dev->dev_private;
 150
 151         uint32_t pipe_stat_val = 0;
 152         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 153         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 154         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 155         uint32_t pipe_clear;
 156         uint32_t i = 0;
 157
 158         spin_lock(&dev_priv->irqmask_lock);
 159
 160         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 161         pipe_stat_val &= pipe_enable | pipe_status;
 162         pipe_stat_val &= pipe_stat_val >> 16;
 163
 164         spin_unlock(&dev_priv->irqmask_lock);
 165
 166         /* Clear the 2nd level interrupt status bits
 167          * Sometimes the bits are very sticky so we repeat until they unstick */
 168         for (i = 0; i < 0xffff; i++) {
 169                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 170                 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
 171
 172                 if (pipe_clear == 0)
 173                         break;
 174         }
 175
 176         if (pipe_clear)
 177                 dev_err(dev->dev,
 178                 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
 179                 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
 180
 181         if (pipe_stat_val & PIPE_VBLANK_STATUS)
 182                 drm_handle_vblank(dev, pipe);
 183
 184         if (pipe_stat_val & PIPE_TE_STATUS)
 185                 drm_handle_vblank(dev, pipe);
 186 }
 187
 188 /*
 189  * Display controller interrupt handler.
 190  */
 191 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 192 {
 193         if (vdc_stat & _PSB_IRQ_ASLE)
 194                 psb_intel_opregion_asle_intr(dev);
 195
 196         if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
 197                 mid_pipe_event_handler(dev, 0);
 198
 199         if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
 200                 mid_pipe_event_handler(dev, 1);
 201 }
 202
 203 /*
 204  * SGX interrupt handler
 205  */
 206 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
 207 {
 208         struct drm_psb_private *dev_priv = dev->dev_private;
 209         u32 val, addr;
 210         int error = false;
 211
 212         if (stat_1 & _PSB_CE_TWOD_COMPLETE)
 213                 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
 214
 215         if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
 216                 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
 217                 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
 218                 if (val) {
 219                         if (val & _PSB_CBI_STAT_PF_N_RW)
 220                                 DRM_ERROR("SGX MMU page fault:");
 221                         else
 222                                 DRM_ERROR("SGX MMU read / write protection fault:");
 223
 224                         if (val & _PSB_CBI_STAT_FAULT_CACHE)
 225                                 DRM_ERROR("\tCache requestor");
 226                         if (val & _PSB_CBI_STAT_FAULT_TA)
 227                                 DRM_ERROR("\tTA requestor");
 228                         if (val & _PSB_CBI_STAT_FAULT_VDM)
 229                                 DRM_ERROR("\tVDM requestor");
 230                         if (val & _PSB_CBI_STAT_FAULT_2D)
 231                                 DRM_ERROR("\t2D requestor");
 232                         if (val & _PSB_CBI_STAT_FAULT_PBE)
 233                                 DRM_ERROR("\tPBE requestor");
 234                         if (val & _PSB_CBI_STAT_FAULT_TSP)
 235                                 DRM_ERROR("\tTSP requestor");
 236                         if (val & _PSB_CBI_STAT_FAULT_ISP)
 237                                 DRM_ERROR("\tISP requestor");
 238                         if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
 239                                 DRM_ERROR("\tUSSEPDS requestor");
 240                         if (val & _PSB_CBI_STAT_FAULT_HOST)
 241                                 DRM_ERROR("\tHost requestor");
 242
 243                         DRM_ERROR("\tMMU failing address is 0x%08x.\n",
 244                                   (unsigned int)addr);
 245                         error = true;
 246                 }
 247         }
 248
 249         /* Clear bits */
 250         PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
 251         PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
 252         PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
 253 }
 254
 255 irqreturn_t psb_irq_handler(int irq, void *arg)
 256 {
 257         struct drm_device *dev = arg;
 258         struct drm_psb_private *dev_priv = dev->dev_private;
 259         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
 260         u32 sgx_stat_1, sgx_stat_2;
 261         int handled = 0;
 262
 263         spin_lock(&dev_priv->irqmask_lock);
 264
 265         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 266
 267         if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
 268                 dsp_int = 1;
 269
 270         /* FIXME: Handle Medfield
 271         if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
 272                 dsp_int = 1;
 273         */
 274
 275         if (vdc_stat & _PSB_IRQ_SGX_FLAG)
 276                 sgx_int = 1;
 277         if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
 278                 hotplug_int = 1;
 279
 280         vdc_stat &= dev_priv->vdc_irq_mask;
 281         spin_unlock(&dev_priv->irqmask_lock);
 282
 283         if (dsp_int && gma_power_is_on(dev)) {
 284                 psb_vdc_interrupt(dev, vdc_stat);
 285                 handled = 1;
 286         }
 287
 288         if (sgx_int) {
 289                 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 290                 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 291                 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
 292                 handled = 1;
 293         }
 294
 295         /* Note: this bit has other meanings on some devices, so we will
 296            need to address that later if it ever matters */
 297         if (hotplug_int && dev_priv->ops->hotplug) {
 298                 handled = dev_priv->ops->hotplug(dev);
 299                 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 300         }
 301
 302         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 303         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 304         rmb();
 305
 306         if (!handled)
 307                 return IRQ_NONE;
 308
 309         return IRQ_HANDLED;
 310 }
 311
 312 void psb_irq_preinstall(struct drm_device *dev)
 313 {
 314         struct drm_psb_private *dev_priv =
 315             (struct drm_psb_private *) dev->dev_private;
 316         unsigned long irqflags;
 317
 318         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 319
 320         if (gma_power_is_on(dev)) {
 321                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 322                 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
 323                 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 324                 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
 325                 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
 326         }
 327         if (dev->vblank[0].enabled)
 328                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 329         if (dev->vblank[1].enabled)
 330                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 331
 332         /* FIXME: Handle Medfield irq mask
 333         if (dev->vblank[1].enabled)
 334                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
 335         if (dev->vblank[2].enabled)
 336                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
 337         */
 338
 339         /* Revisit this area - want per device masks ? */
 340         if (dev_priv->ops->hotplug)
 341                 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
 342         dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
 343
 344         /* This register is safe even if display island is off */
 345         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 346         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 347 }
 348
 349 int psb_irq_postinstall(struct drm_device *dev)
 350 {
 351         struct drm_psb_private *dev_priv = dev->dev_private;
 352         unsigned long irqflags;
 353         unsigned int i;
 354
 355         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 356
 357         /* Enable 2D and MMU fault interrupts */
 358         PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
 359         PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
 360         PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
 361
 362         /* This register is safe even if display island is off */
 363         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 364         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 365
 366         for (i = 0; i < dev->num_crtcs; ++i) {
 367                 if (dev->vblank[i].enabled)
 368                         psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 369                 else
 370                         psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 371         }
 372
 373         if (dev_priv->ops->hotplug_enable)
 374                 dev_priv->ops->hotplug_enable(dev, true);
 375
 376         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 377         return 0;
 378 }
 379
 380 void psb_irq_uninstall(struct drm_device *dev)
 381 {
 382         struct drm_psb_private *dev_priv = dev->dev_private;
 383         unsigned long irqflags;
 384         unsigned int i;
 385
 386         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 387
 388         if (dev_priv->ops->hotplug_enable)
 389                 dev_priv->ops->hotplug_enable(dev, false);
 390
 391         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 392
 393         for (i = 0; i < dev->num_crtcs; ++i) {
 394                 if (dev->vblank[i].enabled)
 395                         psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 396         }
 397
 398         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 399                                   _PSB_IRQ_MSVDX_FLAG |
 400                                   _LNC_IRQ_TOPAZ_FLAG;
 401
 402         /* These two registers are safe even if display island is off */
 403         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 404         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 405
 406         wmb();
 407
 408         /* This register is safe even if display island is off */
 409         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 410         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 411 }
 412
 413 void psb_irq_turn_on_dpst(struct drm_device *dev)
 414 {
 415         struct drm_psb_private *dev_priv =
 416                 (struct drm_psb_private *) dev->dev_private;
 417         u32 hist_reg;
 418         u32 pwm_reg;
 419
 420         if (gma_power_begin(dev, false)) {
 421                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 422                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 423                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 424                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 425
 426                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 427                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 428                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 429                                                 | PWM_PHASEIN_INT_ENABLE,
 430                                                            PWM_CONTROL_LOGIC);
 431                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 432
 433                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 434
 435                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 436                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 437                                                         HISTOGRAM_INT_CONTROL);
 438                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 439                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 440                                                         PWM_CONTROL_LOGIC);
 441
 442                 gma_power_end(dev);
 443         }
 444 }
 445
 446 int psb_irq_enable_dpst(struct drm_device *dev)
 447 {
 448         struct drm_psb_private *dev_priv =
 449                 (struct drm_psb_private *) dev->dev_private;
 450         unsigned long irqflags;
 451
 452         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 453
 454         /* enable DPST */
 455         mid_enable_pipe_event(dev_priv, 0);
 456         psb_irq_turn_on_dpst(dev);
 457
 458         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 459         return 0;
 460 }
 461
 462 void psb_irq_turn_off_dpst(struct drm_device *dev)
 463 {
 464         struct drm_psb_private *dev_priv =
 465             (struct drm_psb_private *) dev->dev_private;
 466         u32 hist_reg;
 467         u32 pwm_reg;
 468
 469         if (gma_power_begin(dev, false)) {
 470                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 471                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 472
 473                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 474
 475                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 476                 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
 477                                                         PWM_CONTROL_LOGIC);
 478                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 479
 480                 gma_power_end(dev);
 481         }
 482 }
 483
 484 int psb_irq_disable_dpst(struct drm_device *dev)
 485 {
 486         struct drm_psb_private *dev_priv =
 487             (struct drm_psb_private *) dev->dev_private;
 488         unsigned long irqflags;
 489
 490         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 491
 492         mid_disable_pipe_event(dev_priv, 0);
 493         psb_irq_turn_off_dpst(dev);
 494
 495         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 496
 497         return 0;
 498 }
 499
 500 /*
 501  * It is used to enable VBLANK interrupt
 502  */
 503 int psb_enable_vblank(struct drm_device *dev, unsigned int pipe)
 504 {
 505         struct drm_psb_private *dev_priv = dev->dev_private;
 506         unsigned long irqflags;
 507         uint32_t reg_val = 0;
 508         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 509
 510         /* Medfield is different - we should perhaps extract out vblank
 511            and blacklight etc ops */
 512         if (IS_MFLD(dev))
 513                 return mdfld_enable_te(dev, pipe);
 514
 515         if (gma_power_begin(dev, false)) {
 516                 reg_val = REG_READ(pipeconf_reg);
 517                 gma_power_end(dev);
 518         }
 519
 520         if (!(reg_val & PIPEACONF_ENABLE))
 521                 return -EINVAL;
 522
 523         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 524
 525         if (pipe == 0)
 526                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 527         else if (pipe == 1)
 528                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 529
 530         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 531         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 532         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 533
 534         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 535
 536         return 0;
 537 }
 538
 539 /*
 540  * It is used to disable VBLANK interrupt
 541  */
 542 void psb_disable_vblank(struct drm_device *dev, unsigned int pipe)
 543 {
 544         struct drm_psb_private *dev_priv = dev->dev_private;
 545         unsigned long irqflags;
 546
 547         if (IS_MFLD(dev))
 548                 mdfld_disable_te(dev, pipe);
 549         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 550
 551         if (pipe == 0)
 552                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
 553         else if (pipe == 1)
 554                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
 555
 556         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 557         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 558         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 559
 560         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 561 }
 562
 563 /*
 564  * It is used to enable TE interrupt
 565  */
 566 int mdfld_enable_te(struct drm_device *dev, int pipe)
 567 {
 568         struct drm_psb_private *dev_priv =
 569                 (struct drm_psb_private *) dev->dev_private;
 570         unsigned long irqflags;
 571         uint32_t reg_val = 0;
 572         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 573
 574         if (gma_power_begin(dev, false)) {
 575                 reg_val = REG_READ(pipeconf_reg);
 576                 gma_power_end(dev);
 577         }
 578
 579         if (!(reg_val & PIPEACONF_ENABLE))
 580                 return -EINVAL;
 581
 582         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 583
 584         mid_enable_pipe_event(dev_priv, pipe);
 585         psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 586
 587         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 588
 589         return 0;
 590 }
 591
 592 /*
 593  * It is used to disable TE interrupt
 594  */
 595 void mdfld_disable_te(struct drm_device *dev, int pipe)
 596 {
 597         struct drm_psb_private *dev_priv =
 598                 (struct drm_psb_private *) dev->dev_private;
 599         unsigned long irqflags;
 600
 601         if (!dev_priv->dsr_enable)
 602                 return;
 603
 604         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 605
 606         mid_disable_pipe_event(dev_priv, pipe);
 607         psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 608
 609         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 610 }
 611
 612 /* Called from drm generic code, passed a 'crtc', which
 613  * we use as a pipe index
 614  */
 615 u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 616 {
 617         uint32_t high_frame = PIPEAFRAMEHIGH;
 618         uint32_t low_frame = PIPEAFRAMEPIXEL;
 619         uint32_t pipeconf_reg = PIPEACONF;
 620         uint32_t reg_val = 0;
 621         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 622
 623         switch (pipe) {
 624         case 0:
 625                 break;
 626         case 1:
 627                 high_frame = PIPEBFRAMEHIGH;
 628                 low_frame = PIPEBFRAMEPIXEL;
 629                 pipeconf_reg = PIPEBCONF;
 630                 break;
 631         case 2:
 632                 high_frame = PIPECFRAMEHIGH;
 633                 low_frame = PIPECFRAMEPIXEL;
 634                 pipeconf_reg = PIPECCONF;
 635                 break;
 636         default:
 637                 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
 638                 return 0;
 639         }
 640
 641         if (!gma_power_begin(dev, false))
 642                 return 0;
 643
 644         reg_val = REG_READ(pipeconf_reg);
 645
 646         if (!(reg_val & PIPEACONF_ENABLE)) {
 647                 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
 648                                                                 pipe);
 649                 goto psb_get_vblank_counter_exit;
 650         }
 651
 652         /*
 653          * High & low register fields aren't synchronized, so make sure
 654          * we get a low value that's stable across two reads of the high
 655          * register.
 656          */
 657         do {
 658                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 659                          PIPE_FRAME_HIGH_SHIFT);
 660                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 661                         PIPE_FRAME_LOW_SHIFT);
 662                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 663                          PIPE_FRAME_HIGH_SHIFT);
 664         } while (high1 != high2);
 665
 666         count = (high1 << 8) | low;
 667
 668 psb_get_vblank_counter_exit:
 669
 670         gma_power_end(dev);
 671
 672         return count;
 673 }
 674