GNU Linux-libre 4.19.264-gnu1
[releases.git] / drivers / gpu / drm / i915 / gvt / display.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
26  *
27  * Contributors:
28  *    Terrence Xu <terrence.xu@intel.com>
29  *    Changbin Du <changbin.du@intel.com>
30  *    Bing Niu <bing.niu@intel.com>
31  *    Zhi Wang <zhi.a.wang@intel.com>
32  *
33  */
34
35 #include "i915_drv.h"
36 #include "gvt.h"
37
38 static int get_edp_pipe(struct intel_vgpu *vgpu)
39 {
40         u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
41         int pipe = -1;
42
43         switch (data & TRANS_DDI_EDP_INPUT_MASK) {
44         case TRANS_DDI_EDP_INPUT_A_ON:
45         case TRANS_DDI_EDP_INPUT_A_ONOFF:
46                 pipe = PIPE_A;
47                 break;
48         case TRANS_DDI_EDP_INPUT_B_ONOFF:
49                 pipe = PIPE_B;
50                 break;
51         case TRANS_DDI_EDP_INPUT_C_ONOFF:
52                 pipe = PIPE_C;
53                 break;
54         }
55         return pipe;
56 }
57
58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59 {
60         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
61
62         if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63                 return 0;
64
65         if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
66                 return 0;
67         return 1;
68 }
69
70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
71 {
72         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
73
74         if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
75                 return -EINVAL;
76
77         if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
78                 return 1;
79
80         if (edp_pipe_is_enabled(vgpu) &&
81                         get_edp_pipe(vgpu) == pipe)
82                 return 1;
83         return 0;
84 }
85
86 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
87         {
88 /* EDID with 1024x768 as its resolution */
89                 /*Header*/
90                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
91                 /* Vendor & Product Identification */
92                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
93                 /* Version & Revision */
94                 0x01, 0x04,
95                 /* Basic Display Parameters & Features */
96                 0xa5, 0x34, 0x20, 0x78, 0x23,
97                 /* Color Characteristics */
98                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
99                 /* Established Timings: maximum resolution is 1024x768 */
100                 0x21, 0x08, 0x00,
101                 /* Standard Timings. All invalid */
102                 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
103                 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
104                 /* 18 Byte Data Blocks 1: invalid */
105                 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
106                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
107                 /* 18 Byte Data Blocks 2: invalid */
108                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
109                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
110                 /* 18 Byte Data Blocks 3: invalid */
111                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
112                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
113                 /* 18 Byte Data Blocks 4: invalid */
114                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
115                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
116                 /* Extension Block Count */
117                 0x00,
118                 /* Checksum */
119                 0xef,
120         },
121         {
122 /* EDID with 1920x1200 as its resolution */
123                 /*Header*/
124                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
125                 /* Vendor & Product Identification */
126                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
127                 /* Version & Revision */
128                 0x01, 0x04,
129                 /* Basic Display Parameters & Features */
130                 0xa5, 0x34, 0x20, 0x78, 0x23,
131                 /* Color Characteristics */
132                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
133                 /* Established Timings: maximum resolution is 1024x768 */
134                 0x21, 0x08, 0x00,
135                 /*
136                  * Standard Timings.
137                  * below new resolutions can be supported:
138                  * 1920x1080, 1280x720, 1280x960, 1280x1024,
139                  * 1440x900, 1600x1200, 1680x1050
140                  */
141                 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
142                 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
143                 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
144                 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
145                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
146                 /* 18 Byte Data Blocks 2: invalid */
147                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
148                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
149                 /* 18 Byte Data Blocks 3: invalid */
150                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
151                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
152                 /* 18 Byte Data Blocks 4: invalid */
153                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
154                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
155                 /* Extension Block Count */
156                 0x00,
157                 /* Checksum */
158                 0x45,
159         },
160 };
161
162 #define DPCD_HEADER_SIZE        0xb
163
164 /* let the virtual display supports DP1.2 */
165 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
166         0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
167 };
168
169 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
170 {
171         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
172         int pipe;
173
174         if (IS_BROXTON(dev_priv)) {
175                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
176                         BXT_DE_PORT_HP_DDIB |
177                         BXT_DE_PORT_HP_DDIC);
178
179                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
180                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
181                                 BXT_DE_PORT_HP_DDIA;
182                 }
183
184                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
185                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
186                                 BXT_DE_PORT_HP_DDIB;
187                 }
188
189                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
190                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
191                                 BXT_DE_PORT_HP_DDIC;
192                 }
193
194                 return;
195         }
196
197         vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
198                         SDE_PORTC_HOTPLUG_CPT |
199                         SDE_PORTD_HOTPLUG_CPT);
200
201         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
202                 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
203                                 SDE_PORTE_HOTPLUG_SPT);
204                 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
205                                 SKL_FUSE_DOWNLOAD_STATUS |
206                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
207                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
208                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
209                 /*
210                  * Only 1 PIPE enabled in current vGPU display and PIPE_A is
211                  *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
212                  *   TRANSCODER_A can be enabled. PORT_x depends on the input of
213                  *   setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
214                  *   so we fixed to DPLL0 here.
215                  * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
216                  */
217                 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
218                         DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
219                 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
220                         DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
221                 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
222                         LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
223                 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
224                 /*
225                  * Golden M/N are calculated based on:
226                  *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
227                  *   DP link clk 1620 MHz and non-constant_n.
228                  * TODO: calculate DP link symbol clk and stream clk m/n.
229                  */
230                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
231                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
232                 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
233                 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
234                 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
235         }
236
237         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
238                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
239                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
240                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
241                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
242                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
243                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
244                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
245                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
246                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
247                         TRANS_DDI_PORT_MASK);
248                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
249                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
250                         (PORT_B << TRANS_DDI_PORT_SHIFT) |
251                         TRANS_DDI_FUNC_ENABLE);
252                 if (IS_BROADWELL(dev_priv)) {
253                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
254                                 ~PORT_CLK_SEL_MASK;
255                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
256                                 PORT_CLK_SEL_LCPLL_810;
257                 }
258                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
259                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
260                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
261         }
262
263         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
264                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
265                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
266                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
267                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
268                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
269                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
270                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
271                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
272                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
273                         TRANS_DDI_PORT_MASK);
274                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
275                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
276                         (PORT_C << TRANS_DDI_PORT_SHIFT) |
277                         TRANS_DDI_FUNC_ENABLE);
278                 if (IS_BROADWELL(dev_priv)) {
279                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
280                                 ~PORT_CLK_SEL_MASK;
281                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
282                                 PORT_CLK_SEL_LCPLL_810;
283                 }
284                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
285                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
286                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
287         }
288
289         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
290                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
291                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
292                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
293                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
294                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
295                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
296                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
297                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
298                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
299                         TRANS_DDI_PORT_MASK);
300                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
301                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
302                         (PORT_D << TRANS_DDI_PORT_SHIFT) |
303                         TRANS_DDI_FUNC_ENABLE);
304                 if (IS_BROADWELL(dev_priv)) {
305                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
306                                 ~PORT_CLK_SEL_MASK;
307                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
308                                 PORT_CLK_SEL_LCPLL_810;
309                 }
310                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
311                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
312                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
313         }
314
315         if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
316                         intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
317                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
318         }
319
320         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
321                 if (IS_BROADWELL(dev_priv))
322                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
323                                 GEN8_PORT_DP_A_HOTPLUG;
324                 else
325                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
326
327                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
328         }
329
330         /* Clear host CRT status, so guest couldn't detect this host CRT. */
331         if (IS_BROADWELL(dev_priv))
332                 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
333
334         /* Disable Primary/Sprite/Cursor plane */
335         for_each_pipe(dev_priv, pipe) {
336                 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
337                 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
338                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
339                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
340         }
341
342         vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
343 }
344
345 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
346 {
347         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
348
349         kfree(port->edid);
350         port->edid = NULL;
351
352         kfree(port->dpcd);
353         port->dpcd = NULL;
354 }
355
356 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
357                                     int type, unsigned int resolution)
358 {
359         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
360
361         if (WARN_ON(resolution >= GVT_EDID_NUM))
362                 return -EINVAL;
363
364         port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
365         if (!port->edid)
366                 return -ENOMEM;
367
368         port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
369         if (!port->dpcd) {
370                 kfree(port->edid);
371                 return -ENOMEM;
372         }
373
374         memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
375                         EDID_SIZE);
376         port->edid->data_valid = true;
377
378         memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
379         port->dpcd->data_valid = true;
380         port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
381         port->type = type;
382
383         emulate_monitor_status_change(vgpu);
384
385         return 0;
386 }
387
388 /**
389  * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
390  * be turned on/off when a virtual pipe is enabled/disabled.
391  * @gvt: a GVT device
392  *
393  * This function is used to turn on/off vblank timer according to currently
394  * enabled/disabled virtual pipes.
395  *
396  */
397 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
398 {
399         struct intel_gvt_irq *irq = &gvt->irq;
400         struct intel_vgpu *vgpu;
401         int pipe, id;
402         int found = false;
403
404         mutex_lock(&gvt->lock);
405         for_each_active_vgpu(gvt, vgpu, id) {
406                 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
407                         if (pipe_is_enabled(vgpu, pipe)) {
408                                 found = true;
409                                 break;
410                         }
411                 }
412                 if (found)
413                         break;
414         }
415
416         /* all the pipes are disabled */
417         if (!found)
418                 hrtimer_cancel(&irq->vblank_timer.timer);
419         else
420                 hrtimer_start(&irq->vblank_timer.timer,
421                         ktime_add_ns(ktime_get(), irq->vblank_timer.period),
422                         HRTIMER_MODE_ABS);
423         mutex_unlock(&gvt->lock);
424 }
425
426 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
427 {
428         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
429         struct intel_vgpu_irq *irq = &vgpu->irq;
430         int vblank_event[] = {
431                 [PIPE_A] = PIPE_A_VBLANK,
432                 [PIPE_B] = PIPE_B_VBLANK,
433                 [PIPE_C] = PIPE_C_VBLANK,
434         };
435         int event;
436
437         if (pipe < PIPE_A || pipe > PIPE_C)
438                 return;
439
440         for_each_set_bit(event, irq->flip_done_event[pipe],
441                         INTEL_GVT_EVENT_MAX) {
442                 clear_bit(event, irq->flip_done_event[pipe]);
443                 if (!pipe_is_enabled(vgpu, pipe))
444                         continue;
445
446                 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
447                 intel_vgpu_trigger_virtual_event(vgpu, event);
448         }
449
450         if (pipe_is_enabled(vgpu, pipe)) {
451                 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
452                 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
453         }
454 }
455
456 static void emulate_vblank(struct intel_vgpu *vgpu)
457 {
458         int pipe;
459
460         mutex_lock(&vgpu->vgpu_lock);
461         for_each_pipe(vgpu->gvt->dev_priv, pipe)
462                 emulate_vblank_on_pipe(vgpu, pipe);
463         mutex_unlock(&vgpu->vgpu_lock);
464 }
465
466 /**
467  * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
468  * @gvt: a GVT device
469  *
470  * This function is used to trigger vblank interrupts for vGPUs on GVT device
471  *
472  */
473 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
474 {
475         struct intel_vgpu *vgpu;
476         int id;
477
478         mutex_lock(&gvt->lock);
479         for_each_active_vgpu(gvt, vgpu, id)
480                 emulate_vblank(vgpu);
481         mutex_unlock(&gvt->lock);
482 }
483
484 /**
485  * intel_vgpu_clean_display - clean vGPU virtual display emulation
486  * @vgpu: a vGPU
487  *
488  * This function is used to clean vGPU virtual display emulation stuffs
489  *
490  */
491 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
492 {
493         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
494
495         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
496                 clean_virtual_dp_monitor(vgpu, PORT_D);
497         else
498                 clean_virtual_dp_monitor(vgpu, PORT_B);
499 }
500
501 /**
502  * intel_vgpu_init_display- initialize vGPU virtual display emulation
503  * @vgpu: a vGPU
504  *
505  * This function is used to initialize vGPU virtual display emulation stuffs
506  *
507  * Returns:
508  * Zero on success, negative error code if failed.
509  *
510  */
511 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
512 {
513         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
514
515         intel_vgpu_init_i2c_edid(vgpu);
516
517         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
518                 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
519                                                 resolution);
520         else
521                 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
522                                                 resolution);
523 }
524
525 /**
526  * intel_vgpu_reset_display- reset vGPU virtual display emulation
527  * @vgpu: a vGPU
528  *
529  * This function is used to reset vGPU virtual display emulation stuffs
530  *
531  */
532 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
533 {
534         emulate_monitor_status_change(vgpu);
535 }