drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .gen = 8, .num_pipes = 3,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .is_valleyview = 1,
 353         .display_mmio_offset = VLV_DISPLAY_BASE,
 354         GEN_CHV_PIPEOFFSETS,
 355         CURSOR_OFFSETS,
 356 };
 357
 358 static const struct intel_device_info intel_skylake_info = {
 359         .is_skylake = 1,
 360         .gen = 9, .num_pipes = 3,
 361         .need_gfx_hws = 1, .has_hotplug = 1,
 362         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 363         .has_llc = 1,
 364         .has_ddi = 1,
 365         .has_fpga_dbg = 1,
 366         .has_fbc = 1,
 367         GEN_DEFAULT_PIPEOFFSETS,
 368         IVB_CURSOR_OFFSETS,
 369 };
 370
 371 static const struct intel_device_info intel_skylake_gt3_info = {
 372         .is_skylake = 1,
 373         .gen = 9, .num_pipes = 3,
 374         .need_gfx_hws = 1, .has_hotplug = 1,
 375         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 376         .has_llc = 1,
 377         .has_ddi = 1,
 378         .has_fpga_dbg = 1,
 379         .has_fbc = 1,
 380         GEN_DEFAULT_PIPEOFFSETS,
 381         IVB_CURSOR_OFFSETS,
 382 };
 383
 384 static const struct intel_device_info intel_broxton_info = {
 385         .is_preliminary = 1,
 386         .gen = 9,
 387         .need_gfx_hws = 1, .has_hotplug = 1,
 388         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 389         .num_pipes = 3,
 390         .has_ddi = 1,
 391         .has_fpga_dbg = 1,
 392         .has_fbc = 1,
 393         GEN_DEFAULT_PIPEOFFSETS,
 394         IVB_CURSOR_OFFSETS,
 395 };
 396
 397 /*
 398  * Make sure any device matches here are from most specific to most
 399  * general.  For example, since the Quanta match is based on the subsystem
 400  * and subvendor IDs, we need it to come before the more general IVB
 401  * PCI ID matches, otherwise we'll use the wrong info struct above.
 402  */
 403 #define INTEL_PCI_IDS \
 404         INTEL_I830_IDS(&intel_i830_info),       \
 405         INTEL_I845G_IDS(&intel_845g_info),      \
 406         INTEL_I85X_IDS(&intel_i85x_info),       \
 407         INTEL_I865G_IDS(&intel_i865g_info),     \
 408         INTEL_I915G_IDS(&intel_i915g_info),     \
 409         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 410         INTEL_I945G_IDS(&intel_i945g_info),     \
 411         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 412         INTEL_I965G_IDS(&intel_i965g_info),     \
 413         INTEL_G33_IDS(&intel_g33_info),         \
 414         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 415         INTEL_GM45_IDS(&intel_gm45_info),       \
 416         INTEL_G45_IDS(&intel_g45_info),         \
 417         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 418         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 419         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 420         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 421         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 422         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 423         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 424         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 425         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 426         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 427         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 428         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 429         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 430         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 431         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 432         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 433         INTEL_CHV_IDS(&intel_cherryview_info),  \
 434         INTEL_SKL_GT1_IDS(&intel_skylake_info), \
 435         INTEL_SKL_GT2_IDS(&intel_skylake_info), \
 436         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),     \
 437         INTEL_BXT_IDS(&intel_broxton_info)
 438
 439 static const struct pci_device_id pciidlist[] = {               /* aka */
 440         INTEL_PCI_IDS,
 441         {0, 0, 0}
 442 };
 443
 444 MODULE_DEVICE_TABLE(pci, pciidlist);
 445
 446 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 447 {
 448         enum intel_pch ret = PCH_NOP;
 449
 450         /*
 451          * In a virtualized passthrough environment we can be in a
 452          * setup where the ISA bridge is not able to be passed through.
 453          * In this case, a south bridge can be emulated and we have to
 454          * make an educated guess as to which PCH is really there.
 455          */
 456
 457         if (IS_GEN5(dev)) {
 458                 ret = PCH_IBX;
 459                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 460         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 461                 ret = PCH_CPT;
 462                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 463         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 464                 ret = PCH_LPT;
 465                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 466         } else if (IS_SKYLAKE(dev)) {
 467                 ret = PCH_SPT;
 468                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 469         }
 470
 471         return ret;
 472 }
 473
 474 void intel_detect_pch(struct drm_device *dev)
 475 {
 476         struct drm_i915_private *dev_priv = dev->dev_private;
 477         struct pci_dev *pch = NULL;
 478
 479         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 480          * (which really amounts to a PCH but no South Display).
 481          */
 482         if (INTEL_INFO(dev)->num_pipes == 0) {
 483                 dev_priv->pch_type = PCH_NOP;
 484                 return;
 485         }
 486
 487         /*
 488          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 489          * make graphics device passthrough work easy for VMM, that only
 490          * need to expose ISA bridge to let driver know the real hardware
 491          * underneath. This is a requirement from virtualization team.
 492          *
 493          * In some virtualized environments (e.g. XEN), there is irrelevant
 494          * ISA bridge in the system. To work reliably, we should scan trhough
 495          * all the ISA bridge devices and check for the first match, instead
 496          * of only checking the first one.
 497          */
 498         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 499                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 500                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 501                         dev_priv->pch_id = id;
 502
 503                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 504                                 dev_priv->pch_type = PCH_IBX;
 505                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 506                                 WARN_ON(!IS_GEN5(dev));
 507                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 508                                 dev_priv->pch_type = PCH_CPT;
 509                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 510                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 511                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 512                                 /* PantherPoint is CPT compatible */
 513                                 dev_priv->pch_type = PCH_CPT;
 514                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 515                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 516                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 517                                 dev_priv->pch_type = PCH_LPT;
 518                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 519                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 520                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 521                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 522                                 dev_priv->pch_type = PCH_LPT;
 523                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 524                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 525                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 526                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 527                                 dev_priv->pch_type = PCH_SPT;
 528                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 529                                 WARN_ON(!IS_SKYLAKE(dev));
 530                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 531                                 dev_priv->pch_type = PCH_SPT;
 532                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 533                                 WARN_ON(!IS_SKYLAKE(dev));
 534                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 535                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 536                                     pch->subsystem_vendor == 0x1af4 &&
 537                                     pch->subsystem_device == 0x1100)) {
 538                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 539                         } else
 540                                 continue;
 541
 542                         break;
 543                 }
 544         }
 545         if (!pch)
 546                 DRM_DEBUG_KMS("No PCH found.\n");
 547
 548         pci_dev_put(pch);
 549 }
 550
 551 bool i915_semaphore_is_enabled(struct drm_device *dev)
 552 {
 553         if (INTEL_INFO(dev)->gen < 6)
 554                 return false;
 555
 556         if (i915.semaphores >= 0)
 557                 return i915.semaphores;
 558
 559         /* TODO: make semaphores and Execlists play nicely together */
 560         if (i915.enable_execlists)
 561                 return false;
 562
 563         /* Until we get further testing... */
 564         if (IS_GEN8(dev))
 565                 return false;
 566
 567 #ifdef CONFIG_INTEL_IOMMU
 568         /* Enable semaphores on SNB when IO remapping is off */
 569         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 570                 return false;
 571 #endif
 572
 573         return true;
 574 }
 575
 576 void i915_firmware_load_error_print(const char *fw_path, int err)
 577 {
 578         DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
 579
 580         /*
 581          * If the reason is not known assume -ENOENT since that's the most
 582          * usual failure mode.
 583          */
 584         if (!err)
 585                 err = -ENOENT;
 586
 587         if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
 588                 return;
 589
 590         DRM_ERROR(
 591           "The driver is built-in, so to load the firmware you need to\n"
 592           "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
 593           "in your initrd/initramfs image.\n");
 594 }
 595
 596 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 597 {
 598         struct drm_device *dev = dev_priv->dev;
 599         struct drm_encoder *encoder;
 600
 601         drm_modeset_lock_all(dev);
 602         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 603                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 604
 605                 if (intel_encoder->suspend)
 606                         intel_encoder->suspend(intel_encoder);
 607         }
 608         drm_modeset_unlock_all(dev);
 609 }
 610
 611 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 612 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 613                               bool rpm_resume);
 614 static int skl_resume_prepare(struct drm_i915_private *dev_priv);
 615 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
 616
 617
 618 static int i915_drm_suspend(struct drm_device *dev)
 619 {
 620         struct drm_i915_private *dev_priv = dev->dev_private;
 621         pci_power_t opregion_target_state;
 622         int error;
 623
 624         /* ignore lid events during suspend */
 625         mutex_lock(&dev_priv->modeset_restore_lock);
 626         dev_priv->modeset_restore = MODESET_SUSPENDED;
 627         mutex_unlock(&dev_priv->modeset_restore_lock);
 628
 629         /* We do a lot of poking in a lot of registers, make sure they work
 630          * properly. */
 631         intel_display_set_init_power(dev_priv, true);
 632
 633         drm_kms_helper_poll_disable(dev);
 634
 635         pci_save_state(dev->pdev);
 636
 637         error = i915_gem_suspend(dev);
 638         if (error) {
 639                 dev_err(&dev->pdev->dev,
 640                         "GEM idle failed, resume might fail\n");
 641                 return error;
 642         }
 643
 644         intel_guc_suspend(dev);
 645
 646         intel_suspend_gt_powersave(dev);
 647
 648         /*
 649          * Disable CRTCs directly since we want to preserve sw state
 650          * for _thaw. Also, power gate the CRTC power wells.
 651          */
 652         drm_modeset_lock_all(dev);
 653         intel_display_suspend(dev);
 654         drm_modeset_unlock_all(dev);
 655
 656         intel_dp_mst_suspend(dev);
 657
 658         intel_runtime_pm_disable_interrupts(dev_priv);
 659         intel_hpd_cancel_work(dev_priv);
 660
 661         intel_suspend_encoders(dev_priv);
 662
 663         intel_suspend_hw(dev);
 664
 665         i915_gem_suspend_gtt_mappings(dev);
 666
 667         i915_save_state(dev);
 668
 669         opregion_target_state = PCI_D3cold;
 670 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 671         if (acpi_target_system_state() < ACPI_STATE_S3)
 672                 opregion_target_state = PCI_D1;
 673 #endif
 674         intel_opregion_notify_adapter(dev, opregion_target_state);
 675
 676         intel_uncore_forcewake_reset(dev, false);
 677         intel_opregion_fini(dev);
 678
 679         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 680
 681         dev_priv->suspend_count++;
 682
 683         intel_display_set_init_power(dev_priv, false);
 684
 685         return 0;
 686 }
 687
 688 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 689 {
 690         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 691         int ret;
 692
 693         ret = intel_suspend_complete(dev_priv);
 694
 695         if (ret) {
 696                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 697
 698                 return ret;
 699         }
 700
 701         i915_rc6_ctx_wa_suspend(dev_priv);
 702
 703         pci_disable_device(drm_dev->pdev);
 704         /*
 705          * During hibernation on some platforms the BIOS may try to access
 706          * the device even though it's already in D3 and hang the machine. So
 707          * leave the device in D0 on those platforms and hope the BIOS will
 708          * power down the device properly. The issue was seen on multiple old
 709          * GENs with different BIOS vendors, so having an explicit blacklist
 710          * is inpractical; apply the workaround on everything pre GEN6. The
 711          * platforms where the issue was seen:
 712          * Lenovo Thinkpad X301, X61s, X60, T60, X41
 713          * Fujitsu FSC S7110
 714          * Acer Aspire 1830T
 715          */
 716         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
 717                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 718
 719         return 0;
 720 }
 721
 722 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 723 {
 724         int error;
 725
 726         if (!dev || !dev->dev_private) {
 727                 DRM_ERROR("dev: %p\n", dev);
 728                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 729                 return -ENODEV;
 730         }
 731
 732         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 733                          state.event != PM_EVENT_FREEZE))
 734                 return -EINVAL;
 735
 736         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 737                 return 0;
 738
 739         error = i915_drm_suspend(dev);
 740         if (error)
 741                 return error;
 742
 743         return i915_drm_suspend_late(dev, false);
 744 }
 745
 746 static int i915_drm_resume(struct drm_device *dev)
 747 {
 748         struct drm_i915_private *dev_priv = dev->dev_private;
 749
 750         mutex_lock(&dev->struct_mutex);
 751         i915_gem_restore_gtt_mappings(dev);
 752         mutex_unlock(&dev->struct_mutex);
 753
 754         i915_restore_state(dev);
 755         intel_opregion_setup(dev);
 756
 757         intel_init_pch_refclk(dev);
 758         drm_mode_config_reset(dev);
 759
 760         /*
 761          * Interrupts have to be enabled before any batches are run. If not the
 762          * GPU will hang. i915_gem_init_hw() will initiate batches to
 763          * update/restore the context.
 764          *
 765          * Modeset enabling in intel_modeset_init_hw() also needs working
 766          * interrupts.
 767          */
 768         intel_runtime_pm_enable_interrupts(dev_priv);
 769
 770         mutex_lock(&dev->struct_mutex);
 771         if (i915_gem_init_hw(dev)) {
 772                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 773                         atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 774         }
 775         mutex_unlock(&dev->struct_mutex);
 776
 777         intel_guc_resume(dev);
 778
 779         intel_modeset_init_hw(dev);
 780
 781         spin_lock_irq(&dev_priv->irq_lock);
 782         if (dev_priv->display.hpd_irq_setup)
 783                 dev_priv->display.hpd_irq_setup(dev);
 784         spin_unlock_irq(&dev_priv->irq_lock);
 785
 786         drm_modeset_lock_all(dev);
 787         intel_display_resume(dev);
 788         drm_modeset_unlock_all(dev);
 789
 790         intel_dp_mst_resume(dev);
 791
 792         /*
 793          * ... but also need to make sure that hotplug processing
 794          * doesn't cause havoc. Like in the driver load code we don't
 795          * bother with the tiny race here where we might loose hotplug
 796          * notifications.
 797          * */
 798         intel_hpd_init(dev_priv);
 799         /* Config may have changed between suspend and resume */
 800         drm_helper_hpd_irq_event(dev);
 801
 802         intel_opregion_init(dev);
 803
 804         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 805
 806         mutex_lock(&dev_priv->modeset_restore_lock);
 807         dev_priv->modeset_restore = MODESET_DONE;
 808         mutex_unlock(&dev_priv->modeset_restore_lock);
 809
 810         intel_opregion_notify_adapter(dev, PCI_D0);
 811
 812         drm_kms_helper_poll_enable(dev);
 813
 814         return 0;
 815 }
 816
 817 static int i915_drm_resume_early(struct drm_device *dev)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         int ret = 0;
 821
 822         /*
 823          * We have a resume ordering issue with the snd-hda driver also
 824          * requiring our device to be power up. Due to the lack of a
 825          * parent/child relationship we currently solve this with an early
 826          * resume hook.
 827          *
 828          * FIXME: This should be solved with a special hdmi sink device or
 829          * similar so that power domains can be employed.
 830          */
 831         if (pci_enable_device(dev->pdev))
 832                 return -EIO;
 833
 834         pci_set_master(dev->pdev);
 835
 836         if (IS_VALLEYVIEW(dev_priv))
 837                 ret = vlv_resume_prepare(dev_priv, false);
 838         if (ret)
 839                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 840                           ret);
 841
 842         intel_uncore_early_sanitize(dev, true);
 843
 844         if (IS_BROXTON(dev))
 845                 ret = bxt_resume_prepare(dev_priv);
 846         else if (IS_SKYLAKE(dev_priv))
 847                 ret = skl_resume_prepare(dev_priv);
 848         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 849                 hsw_disable_pc8(dev_priv);
 850
 851         intel_uncore_sanitize(dev);
 852         intel_power_domains_init_hw(dev_priv);
 853
 854         i915_rc6_ctx_wa_resume(dev_priv);
 855
 856         return ret;
 857 }
 858
 859 int i915_resume_switcheroo(struct drm_device *dev)
 860 {
 861         int ret;
 862
 863         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 864                 return 0;
 865
 866         ret = i915_drm_resume_early(dev);
 867         if (ret)
 868                 return ret;
 869
 870         return i915_drm_resume(dev);
 871 }
 872
 873 /**
 874  * i915_reset - reset chip after a hang
 875  * @dev: drm device to reset
 876  *
 877  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 878  * reset or otherwise an error code.
 879  *
 880  * Procedure is fairly simple:
 881  *   - reset the chip using the reset reg
 882  *   - re-init context state
 883  *   - re-init hardware status page
 884  *   - re-init ring buffer
 885  *   - re-init interrupt state
 886  *   - re-init display
 887  */
 888 int i915_reset(struct drm_device *dev)
 889 {
 890         struct drm_i915_private *dev_priv = dev->dev_private;
 891         bool simulated;
 892         int ret;
 893
 894         intel_reset_gt_powersave(dev);
 895
 896         mutex_lock(&dev->struct_mutex);
 897
 898         i915_gem_reset(dev);
 899
 900         simulated = dev_priv->gpu_error.stop_rings != 0;
 901
 902         ret = intel_gpu_reset(dev);
 903
 904         /* Also reset the gpu hangman. */
 905         if (simulated) {
 906                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 907                 dev_priv->gpu_error.stop_rings = 0;
 908                 if (ret == -ENODEV) {
 909                         DRM_INFO("Reset not implemented, but ignoring "
 910                                  "error for simulated gpu hangs\n");
 911                         ret = 0;
 912                 }
 913         }
 914
 915         if (i915_stop_ring_allow_warn(dev_priv))
 916                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 917
 918         if (ret) {
 919                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 920                 mutex_unlock(&dev->struct_mutex);
 921                 return ret;
 922         }
 923
 924         intel_overlay_reset(dev_priv);
 925
 926         /* Ok, now get things going again... */
 927
 928         /*
 929          * Everything depends on having the GTT running, so we need to start
 930          * there.  Fortunately we don't need to do this unless we reset the
 931          * chip at a PCI level.
 932          *
 933          * Next we need to restore the context, but we don't use those
 934          * yet either...
 935          *
 936          * Ring buffer needs to be re-initialized in the KMS case, or if X
 937          * was running at the time of the reset (i.e. we weren't VT
 938          * switched away).
 939          */
 940
 941         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 942         dev_priv->gpu_error.reload_in_reset = true;
 943
 944         ret = i915_gem_init_hw(dev);
 945
 946         dev_priv->gpu_error.reload_in_reset = false;
 947
 948         mutex_unlock(&dev->struct_mutex);
 949         if (ret) {
 950                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 951                 return ret;
 952         }
 953
 954         /*
 955          * rps/rc6 re-init is necessary to restore state lost after the
 956          * reset and the re-install of gt irqs. Skip for ironlake per
 957          * previous concerns that it doesn't respond well to some forms
 958          * of re-init after reset.
 959          */
 960         if (INTEL_INFO(dev)->gen > 5)
 961                 intel_enable_gt_powersave(dev);
 962
 963         return 0;
 964 }
 965
 966 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 967 {
 968         struct intel_device_info *intel_info =
 969                 (struct intel_device_info *) ent->driver_data;
 970
 971         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 972                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 973                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 974                 return -ENODEV;
 975         }
 976
 977         /* Only bind to function 0 of the device. Early generations
 978          * used function 1 as a placeholder for multi-head. This causes
 979          * us confusion instead, especially on the systems where both
 980          * functions have the same PCI-ID!
 981          */
 982         if (PCI_FUNC(pdev->devfn))
 983                 return -ENODEV;
 984
 985         return drm_get_pci_dev(pdev, ent, &driver);
 986 }
 987
 988 static void
 989 i915_pci_remove(struct pci_dev *pdev)
 990 {
 991         struct drm_device *dev = pci_get_drvdata(pdev);
 992
 993         drm_put_dev(dev);
 994 }
 995
 996 static int i915_pm_suspend(struct device *dev)
 997 {
 998         struct pci_dev *pdev = to_pci_dev(dev);
 999         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1000
1001         if (!drm_dev || !drm_dev->dev_private) {
1002                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1003                 return -ENODEV;
1004         }
1005
1006         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1007                 return 0;
1008
1009         return i915_drm_suspend(drm_dev);
1010 }
1011
1012 static int i915_pm_suspend_late(struct device *dev)
1013 {
1014         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1015
1016         /*
1017          * We have a suspend ordering issue with the snd-hda driver also
1018          * requiring our device to be power up. Due to the lack of a
1019          * parent/child relationship we currently solve this with an late
1020          * suspend hook.
1021          *
1022          * FIXME: This should be solved with a special hdmi sink device or
1023          * similar so that power domains can be employed.
1024          */
1025         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1026                 return 0;
1027
1028         return i915_drm_suspend_late(drm_dev, false);
1029 }
1030
1031 static int i915_pm_poweroff_late(struct device *dev)
1032 {
1033         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1034
1035         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1036                 return 0;
1037
1038         return i915_drm_suspend_late(drm_dev, true);
1039 }
1040
1041 static int i915_pm_resume_early(struct device *dev)
1042 {
1043         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1044
1045         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1046                 return 0;
1047
1048         return i915_drm_resume_early(drm_dev);
1049 }
1050
1051 static int i915_pm_resume(struct device *dev)
1052 {
1053         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1054
1055         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1056                 return 0;
1057
1058         return i915_drm_resume(drm_dev);
1059 }
1060
1061 static int skl_suspend_complete(struct drm_i915_private *dev_priv)
1062 {
1063         /* Enabling DC6 is not a hard requirement to enter runtime D3 */
1064
1065         skl_uninit_cdclk(dev_priv);
1066
1067         return 0;
1068 }
1069
1070 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1071 {
1072         hsw_enable_pc8(dev_priv);
1073
1074         return 0;
1075 }
1076
1077 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1078 {
1079         struct drm_device *dev = dev_priv->dev;
1080
1081         /* TODO: when DC5 support is added disable DC5 here. */
1082
1083         broxton_ddi_phy_uninit(dev);
1084         broxton_uninit_cdclk(dev);
1085         bxt_enable_dc9(dev_priv);
1086
1087         return 0;
1088 }
1089
1090 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093
1094         /* TODO: when CSR FW support is added make sure the FW is loaded */
1095
1096         bxt_disable_dc9(dev_priv);
1097
1098         /*
1099          * TODO: when DC5 support is added enable DC5 here if the CSR FW
1100          * is available.
1101          */
1102         broxton_init_cdclk(dev);
1103         broxton_ddi_phy_init(dev);
1104         intel_prepare_ddi(dev);
1105
1106         return 0;
1107 }
1108
1109 static int skl_resume_prepare(struct drm_i915_private *dev_priv)
1110 {
1111         struct drm_device *dev = dev_priv->dev;
1112
1113         skl_init_cdclk(dev_priv);
1114         intel_csr_load_program(dev);
1115
1116         return 0;
1117 }
1118
1119 /*
1120  * Save all Gunit registers that may be lost after a D3 and a subsequent
1121  * S0i[R123] transition. The list of registers needing a save/restore is
1122  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1123  * registers in the following way:
1124  * - Driver: saved/restored by the driver
1125  * - Punit : saved/restored by the Punit firmware
1126  * - No, w/o marking: no need to save/restore, since the register is R/O or
1127  *                    used internally by the HW in a way that doesn't depend
1128  *                    keeping the content across a suspend/resume.
1129  * - Debug : used for debugging
1130  *
1131  * We save/restore all registers marked with 'Driver', with the following
1132  * exceptions:
1133  * - Registers out of use, including also registers marked with 'Debug'.
1134  *   These have no effect on the driver's operation, so we don't save/restore
1135  *   them to reduce the overhead.
1136  * - Registers that are fully setup by an initialization function called from
1137  *   the resume path. For example many clock gating and RPS/RC6 registers.
1138  * - Registers that provide the right functionality with their reset defaults.
1139  *
1140  * TODO: Except for registers that based on the above 3 criteria can be safely
1141  * ignored, we save/restore all others, practically treating the HW context as
1142  * a black-box for the driver. Further investigation is needed to reduce the
1143  * saved/restored registers even further, by following the same 3 criteria.
1144  */
1145 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1146 {
1147         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1148         int i;
1149
1150         /* GAM 0x4000-0x4770 */
1151         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1152         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1153         s->arb_mode             = I915_READ(ARB_MODE);
1154         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1155         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1156
1157         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1158                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1159
1160         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1161         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1162
1163         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1164         s->ecochk               = I915_READ(GAM_ECOCHK);
1165         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1166         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1167
1168         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1169
1170         /* MBC 0x9024-0x91D0, 0x8500 */
1171         s->g3dctl               = I915_READ(VLV_G3DCTL);
1172         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1173         s->mbctl                = I915_READ(GEN6_MBCTL);
1174
1175         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1176         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1177         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1178         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1179         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1180         s->rstctl               = I915_READ(GEN6_RSTCTL);
1181         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1182
1183         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1184         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1185         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1186         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1187         s->ecobus               = I915_READ(ECOBUS);
1188         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1189         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1190         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1191         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1192         s->rcedata              = I915_READ(VLV_RCEDATA);
1193         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1194
1195         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1196         s->gt_imr               = I915_READ(GTIMR);
1197         s->gt_ier               = I915_READ(GTIER);
1198         s->pm_imr               = I915_READ(GEN6_PMIMR);
1199         s->pm_ier               = I915_READ(GEN6_PMIER);
1200
1201         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1202                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1203
1204         /* GT SA CZ domain, 0x100000-0x138124 */
1205         s->tilectl              = I915_READ(TILECTL);
1206         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1207         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1208         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1209         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1210
1211         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1212         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1213         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1214         s->pcbr                 = I915_READ(VLV_PCBR);
1215         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1216
1217         /*
1218          * Not saving any of:
1219          * DFT,         0x9800-0x9EC0
1220          * SARB,        0xB000-0xB1FC
1221          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1222          * PCI CFG
1223          */
1224 }
1225
1226 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1227 {
1228         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1229         u32 val;
1230         int i;
1231
1232         /* GAM 0x4000-0x4770 */
1233         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1234         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1235         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1236         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1237         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1238
1239         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1240                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1241
1242         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1243         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1244
1245         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1246         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1247         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1248         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1249
1250         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1251
1252         /* MBC 0x9024-0x91D0, 0x8500 */
1253         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1254         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1255         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1256
1257         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1258         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1259         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1260         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1261         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1262         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1263         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1264
1265         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1266         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1267         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1268         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1269         I915_WRITE(ECOBUS,              s->ecobus);
1270         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1271         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1272         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1273         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1274         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1275         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1276
1277         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1278         I915_WRITE(GTIMR,               s->gt_imr);
1279         I915_WRITE(GTIER,               s->gt_ier);
1280         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1281         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1282
1283         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1284                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1285
1286         /* GT SA CZ domain, 0x100000-0x138124 */
1287         I915_WRITE(TILECTL,                     s->tilectl);
1288         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1289         /*
1290          * Preserve the GT allow wake and GFX force clock bit, they are not
1291          * be restored, as they are used to control the s0ix suspend/resume
1292          * sequence by the caller.
1293          */
1294         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1295         val &= VLV_GTLC_ALLOWWAKEREQ;
1296         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1297         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1298
1299         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1300         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1301         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1302         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1303
1304         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1305
1306         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1307         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1308         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1309         I915_WRITE(VLV_PCBR,                    s->pcbr);
1310         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1311 }
1312
1313 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1314 {
1315         u32 val;
1316         int err;
1317
1318 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1319
1320         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1321         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1322         if (force_on)
1323                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1324         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1325
1326         if (!force_on)
1327                 return 0;
1328
1329         err = wait_for(COND, 20);
1330         if (err)
1331                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1332                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1333
1334         return err;
1335 #undef COND
1336 }
1337
1338 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1339 {
1340         u32 val;
1341         int err = 0;
1342
1343         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1344         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1345         if (allow)
1346                 val |= VLV_GTLC_ALLOWWAKEREQ;
1347         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1348         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1349
1350 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1351               allow)
1352         err = wait_for(COND, 1);
1353         if (err)
1354                 DRM_ERROR("timeout disabling GT waking\n");
1355         return err;
1356 #undef COND
1357 }
1358
1359 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1360                                  bool wait_for_on)
1361 {
1362         u32 mask;
1363         u32 val;
1364         int err;
1365
1366         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1367         val = wait_for_on ? mask : 0;
1368 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1369         if (COND)
1370                 return 0;
1371
1372         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1373                         wait_for_on ? "on" : "off",
1374                         I915_READ(VLV_GTLC_PW_STATUS));
1375
1376         /*
1377          * RC6 transitioning can be delayed up to 2 msec (see
1378          * valleyview_enable_rps), use 3 msec for safety.
1379          */
1380         err = wait_for(COND, 3);
1381         if (err)
1382                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1383                           wait_for_on ? "on" : "off");
1384
1385         return err;
1386 #undef COND
1387 }
1388
1389 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1390 {
1391         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1392                 return;
1393
1394         DRM_ERROR("GT register access while GT waking disabled\n");
1395         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1396 }
1397
1398 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1399 {
1400         u32 mask;
1401         int err;
1402
1403         /*
1404          * Bspec defines the following GT well on flags as debug only, so
1405          * don't treat them as hard failures.
1406          */
1407         (void)vlv_wait_for_gt_wells(dev_priv, false);
1408
1409         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1410         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1411
1412         vlv_check_no_gt_access(dev_priv);
1413
1414         err = vlv_force_gfx_clock(dev_priv, true);
1415         if (err)
1416                 goto err1;
1417
1418         err = vlv_allow_gt_wake(dev_priv, false);
1419         if (err)
1420                 goto err2;
1421
1422         if (!IS_CHERRYVIEW(dev_priv->dev))
1423                 vlv_save_gunit_s0ix_state(dev_priv);
1424
1425         err = vlv_force_gfx_clock(dev_priv, false);
1426         if (err)
1427                 goto err2;
1428
1429         return 0;
1430
1431 err2:
1432         /* For safety always re-enable waking and disable gfx clock forcing */
1433         vlv_allow_gt_wake(dev_priv, true);
1434 err1:
1435         vlv_force_gfx_clock(dev_priv, false);
1436
1437         return err;
1438 }
1439
1440 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1441                                 bool rpm_resume)
1442 {
1443         struct drm_device *dev = dev_priv->dev;
1444         int err;
1445         int ret;
1446
1447         /*
1448          * If any of the steps fail just try to continue, that's the best we
1449          * can do at this point. Return the first error code (which will also
1450          * leave RPM permanently disabled).
1451          */
1452         ret = vlv_force_gfx_clock(dev_priv, true);
1453
1454         if (!IS_CHERRYVIEW(dev_priv->dev))
1455                 vlv_restore_gunit_s0ix_state(dev_priv);
1456
1457         err = vlv_allow_gt_wake(dev_priv, true);
1458         if (!ret)
1459                 ret = err;
1460
1461         err = vlv_force_gfx_clock(dev_priv, false);
1462         if (!ret)
1463                 ret = err;
1464
1465         vlv_check_no_gt_access(dev_priv);
1466
1467         if (rpm_resume) {
1468                 intel_init_clock_gating(dev);
1469                 i915_gem_restore_fences(dev);
1470         }
1471
1472         return ret;
1473 }
1474
1475 static int intel_runtime_suspend(struct device *device)
1476 {
1477         struct pci_dev *pdev = to_pci_dev(device);
1478         struct drm_device *dev = pci_get_drvdata(pdev);
1479         struct drm_i915_private *dev_priv = dev->dev_private;
1480         int ret;
1481
1482         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1483                 return -ENODEV;
1484
1485         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1486                 return -ENODEV;
1487
1488         DRM_DEBUG_KMS("Suspending device\n");
1489
1490         /*
1491          * We could deadlock here in case another thread holding struct_mutex
1492          * calls RPM suspend concurrently, since the RPM suspend will wait
1493          * first for this RPM suspend to finish. In this case the concurrent
1494          * RPM resume will be followed by its RPM suspend counterpart. Still
1495          * for consistency return -EAGAIN, which will reschedule this suspend.
1496          */
1497         if (!mutex_trylock(&dev->struct_mutex)) {
1498                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1499                 /*
1500                  * Bump the expiration timestamp, otherwise the suspend won't
1501                  * be rescheduled.
1502                  */
1503                 pm_runtime_mark_last_busy(device);
1504
1505                 return -EAGAIN;
1506         }
1507         /*
1508          * We are safe here against re-faults, since the fault handler takes
1509          * an RPM reference.
1510          */
1511         i915_gem_release_all_mmaps(dev_priv);
1512         mutex_unlock(&dev->struct_mutex);
1513
1514         intel_guc_suspend(dev);
1515
1516         intel_suspend_gt_powersave(dev);
1517         intel_runtime_pm_disable_interrupts(dev_priv);
1518
1519         ret = intel_suspend_complete(dev_priv);
1520         if (ret) {
1521                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1522                 intel_runtime_pm_enable_interrupts(dev_priv);
1523
1524                 return ret;
1525         }
1526
1527         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1528         intel_uncore_forcewake_reset(dev, false);
1529         dev_priv->pm.suspended = true;
1530
1531         /*
1532          * FIXME: We really should find a document that references the arguments
1533          * used below!
1534          */
1535         if (IS_BROADWELL(dev)) {
1536                 /*
1537                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1538                  * being detected, and the call we do at intel_runtime_resume()
1539                  * won't be able to restore them. Since PCI_D3hot matches the
1540                  * actual specification and appears to be working, use it.
1541                  */
1542                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1543         } else {
1544                 /*
1545                  * current versions of firmware which depend on this opregion
1546                  * notification have repurposed the D1 definition to mean
1547                  * "runtime suspended" vs. what you would normally expect (D3)
1548                  * to distinguish it from notifications that might be sent via
1549                  * the suspend path.
1550                  */
1551                 intel_opregion_notify_adapter(dev, PCI_D1);
1552         }
1553
1554         assert_forcewakes_inactive(dev_priv);
1555
1556         DRM_DEBUG_KMS("Device suspended\n");
1557         return 0;
1558 }
1559
1560 static int intel_runtime_resume(struct device *device)
1561 {
1562         struct pci_dev *pdev = to_pci_dev(device);
1563         struct drm_device *dev = pci_get_drvdata(pdev);
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565         int ret = 0;
1566
1567         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1568                 return -ENODEV;
1569
1570         DRM_DEBUG_KMS("Resuming device\n");
1571
1572         intel_opregion_notify_adapter(dev, PCI_D0);
1573         dev_priv->pm.suspended = false;
1574
1575         intel_guc_resume(dev);
1576
1577         if (IS_GEN6(dev_priv))
1578                 intel_init_pch_refclk(dev);
1579
1580         if (IS_BROXTON(dev))
1581                 ret = bxt_resume_prepare(dev_priv);
1582         else if (IS_SKYLAKE(dev))
1583                 ret = skl_resume_prepare(dev_priv);
1584         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1585                 hsw_disable_pc8(dev_priv);
1586         else if (IS_VALLEYVIEW(dev_priv))
1587                 ret = vlv_resume_prepare(dev_priv, true);
1588
1589         /*
1590          * No point of rolling back things in case of an error, as the best
1591          * we can do is to hope that things will still work (and disable RPM).
1592          */
1593         i915_gem_init_swizzling(dev);
1594         gen6_update_ring_freq(dev);
1595
1596         intel_runtime_pm_enable_interrupts(dev_priv);
1597
1598         /*
1599          * On VLV/CHV display interrupts are part of the display
1600          * power well, so hpd is reinitialized from there. For
1601          * everyone else do it here.
1602          */
1603         if (!IS_VALLEYVIEW(dev_priv))
1604                 intel_hpd_init(dev_priv);
1605
1606         intel_enable_gt_powersave(dev);
1607
1608         if (ret)
1609                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1610         else
1611                 DRM_DEBUG_KMS("Device resumed\n");
1612
1613         return ret;
1614 }
1615
1616 /*
1617  * This function implements common functionality of runtime and system
1618  * suspend sequence.
1619  */
1620 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1621 {
1622         int ret;
1623
1624         if (IS_BROXTON(dev_priv))
1625                 ret = bxt_suspend_complete(dev_priv);
1626         else if (IS_SKYLAKE(dev_priv))
1627                 ret = skl_suspend_complete(dev_priv);
1628         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1629                 ret = hsw_suspend_complete(dev_priv);
1630         else if (IS_VALLEYVIEW(dev_priv))
1631                 ret = vlv_suspend_complete(dev_priv);
1632         else
1633                 ret = 0;
1634
1635         return ret;
1636 }
1637
1638 static const struct dev_pm_ops i915_pm_ops = {
1639         /*
1640          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1641          * PMSG_RESUME]
1642          */
1643         .suspend = i915_pm_suspend,
1644         .suspend_late = i915_pm_suspend_late,
1645         .resume_early = i915_pm_resume_early,
1646         .resume = i915_pm_resume,
1647
1648         /*
1649          * S4 event handlers
1650          * @freeze, @freeze_late    : called (1) before creating the
1651          *                            hibernation image [PMSG_FREEZE] and
1652          *                            (2) after rebooting, before restoring
1653          *                            the image [PMSG_QUIESCE]
1654          * @thaw, @thaw_early       : called (1) after creating the hibernation
1655          *                            image, before writing it [PMSG_THAW]
1656          *                            and (2) after failing to create or
1657          *                            restore the image [PMSG_RECOVER]
1658          * @poweroff, @poweroff_late: called after writing the hibernation
1659          *                            image, before rebooting [PMSG_HIBERNATE]
1660          * @restore, @restore_early : called after rebooting and restoring the
1661          *                            hibernation image [PMSG_RESTORE]
1662          */
1663         .freeze = i915_pm_suspend,
1664         .freeze_late = i915_pm_suspend_late,
1665         .thaw_early = i915_pm_resume_early,
1666         .thaw = i915_pm_resume,
1667         .poweroff = i915_pm_suspend,
1668         .poweroff_late = i915_pm_poweroff_late,
1669         .restore_early = i915_pm_resume_early,
1670         .restore = i915_pm_resume,
1671
1672         /* S0ix (via runtime suspend) event handlers */
1673         .runtime_suspend = intel_runtime_suspend,
1674         .runtime_resume = intel_runtime_resume,
1675 };
1676
1677 static const struct vm_operations_struct i915_gem_vm_ops = {
1678         .fault = i915_gem_fault,
1679         .open = drm_gem_vm_open,
1680         .close = drm_gem_vm_close,
1681 };
1682
1683 static const struct file_operations i915_driver_fops = {
1684         .owner = THIS_MODULE,
1685         .open = drm_open,
1686         .release = drm_release,
1687         .unlocked_ioctl = drm_ioctl,
1688         .mmap = drm_gem_mmap,
1689         .poll = drm_poll,
1690         .read = drm_read,
1691 #ifdef CONFIG_COMPAT
1692         .compat_ioctl = i915_compat_ioctl,
1693 #endif
1694         .llseek = noop_llseek,
1695 };
1696
1697 static struct drm_driver driver = {
1698         /* Don't use MTRRs here; the Xserver or userspace app should
1699          * deal with them for Intel hardware.
1700          */
1701         .driver_features =
1702             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1703             DRIVER_RENDER | DRIVER_MODESET,
1704         .load = i915_driver_load,
1705         .unload = i915_driver_unload,
1706         .open = i915_driver_open,
1707         .lastclose = i915_driver_lastclose,
1708         .preclose = i915_driver_preclose,
1709         .postclose = i915_driver_postclose,
1710         .set_busid = drm_pci_set_busid,
1711
1712 #if defined(CONFIG_DEBUG_FS)
1713         .debugfs_init = i915_debugfs_init,
1714         .debugfs_cleanup = i915_debugfs_cleanup,
1715 #endif
1716         .gem_free_object = i915_gem_free_object,
1717         .gem_vm_ops = &i915_gem_vm_ops,
1718
1719         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1720         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1721         .gem_prime_export = i915_gem_prime_export,
1722         .gem_prime_import = i915_gem_prime_import,
1723
1724         .dumb_create = i915_gem_dumb_create,
1725         .dumb_map_offset = i915_gem_mmap_gtt,
1726         .dumb_destroy = drm_gem_dumb_destroy,
1727         .ioctls = i915_ioctls,
1728         .fops = &i915_driver_fops,
1729         .name = DRIVER_NAME,
1730         .desc = DRIVER_DESC,
1731         .date = DRIVER_DATE,
1732         .major = DRIVER_MAJOR,
1733         .minor = DRIVER_MINOR,
1734         .patchlevel = DRIVER_PATCHLEVEL,
1735 };
1736
1737 static struct pci_driver i915_pci_driver = {
1738         .name = DRIVER_NAME,
1739         .id_table = pciidlist,
1740         .probe = i915_pci_probe,
1741         .remove = i915_pci_remove,
1742         .driver.pm = &i915_pm_ops,
1743 };
1744
1745 static int __init i915_init(void)
1746 {
1747         driver.num_ioctls = i915_max_ioctl;
1748
1749         /*
1750          * Enable KMS by default, unless explicitly overriden by
1751          * either the i915.modeset prarameter or by the
1752          * vga_text_mode_force boot option.
1753          */
1754
1755         if (i915.modeset == 0)
1756                 driver.driver_features &= ~DRIVER_MODESET;
1757
1758 #ifdef CONFIG_VGA_CONSOLE
1759         if (vgacon_text_force() && i915.modeset == -1)
1760                 driver.driver_features &= ~DRIVER_MODESET;
1761 #endif
1762
1763         if (!(driver.driver_features & DRIVER_MODESET)) {
1764                 /* Silently fail loading to not upset userspace. */
1765                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1766                 return 0;
1767         }
1768
1769         if (i915.nuclear_pageflip)
1770                 driver.driver_features |= DRIVER_ATOMIC;
1771
1772         return drm_pci_init(&driver, &i915_pci_driver);
1773 }
1774
1775 static void __exit i915_exit(void)
1776 {
1777         if (!(driver.driver_features & DRIVER_MODESET))
1778                 return; /* Never loaded a driver. */
1779
1780         drm_pci_exit(&driver, &i915_pci_driver);
1781 }
1782
1783 module_init(i915_init);
1784 module_exit(i915_exit);
1785
1786 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1787 MODULE_AUTHOR("Intel Corporation");
1788
1789 MODULE_DESCRIPTION(DRIVER_DESC);
1790 MODULE_LICENSE("GPL and additional rights");