2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private *dev_priv)
104 if (IS_GEN6(dev_priv))
105 return GEN6_CONTEXT_ALIGN;
107 return GEN7_CONTEXT_ALIGN;
110 static int get_context_size(struct drm_i915_private *dev_priv)
115 switch (INTEL_GEN(dev_priv)) {
117 reg = I915_READ(CXT_SIZE);
118 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
121 reg = I915_READ(GEN7_CXT_SIZE);
122 if (IS_HASWELL(dev_priv))
123 ret = HSW_CXT_TOTAL_SIZE;
125 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
128 ret = GEN8_CXT_TOTAL_SIZE;
137 void i915_gem_context_free(struct kref *ctx_ref)
139 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
142 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
143 trace_i915_context_free(ctx);
144 GEM_BUG_ON(!ctx->closed);
146 i915_ppgtt_put(ctx->ppgtt);
148 for (i = 0; i < I915_NUM_ENGINES; i++) {
149 struct intel_context *ce = &ctx->engine[i];
154 WARN_ON(ce->pin_count);
156 intel_ring_free(ce->ring);
158 i915_vma_put(ce->state);
161 kfree(ctx->jump_whitelist);
164 list_del(&ctx->link);
166 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
170 struct drm_i915_gem_object *
171 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
173 struct drm_i915_gem_object *obj;
176 lockdep_assert_held(&dev->struct_mutex);
178 obj = i915_gem_object_create(dev, size);
183 * Try to make the context utilize L3 as well as LLC.
185 * On VLV we don't have L3 controls in the PTEs so we
186 * shouldn't touch the cache level, especially as that
187 * would make the object snooped which might have a
188 * negative performance impact.
190 * Snooping is required on non-llc platforms in execlist
191 * mode, but since all GGTT accesses use PAT entry 0 we
192 * get snooping anyway regardless of cache_level.
194 * This is only applicable for Ivy Bridge devices since
195 * later platforms don't have L3 control bits in the PTE.
197 if (IS_IVYBRIDGE(dev)) {
198 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
199 /* Failure shouldn't ever happen this early */
201 i915_gem_object_put(obj);
209 static void i915_ppgtt_close(struct i915_address_space *vm)
211 struct list_head *phases[] = {
218 GEM_BUG_ON(vm->closed);
221 for (phase = phases; *phase; phase++) {
222 struct i915_vma *vma, *vn;
224 list_for_each_entry_safe(vma, vn, *phase, vm_link)
225 if (!i915_vma_is_closed(vma))
230 static void context_close(struct i915_gem_context *ctx)
232 GEM_BUG_ON(ctx->closed);
235 i915_ppgtt_close(&ctx->ppgtt->base);
236 ctx->file_priv = ERR_PTR(-EBADF);
237 i915_gem_context_put(ctx);
240 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
244 ret = ida_simple_get(&dev_priv->context_hw_ida,
245 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
247 /* Contexts are only released when no longer active.
248 * Flush any pending retires to hopefully release some
249 * stale contexts and try again.
251 i915_gem_retire_requests(dev_priv);
252 ret = ida_simple_get(&dev_priv->context_hw_ida,
253 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
262 static struct i915_gem_context *
263 __create_hw_context(struct drm_device *dev,
264 struct drm_i915_file_private *file_priv)
266 struct drm_i915_private *dev_priv = to_i915(dev);
267 struct i915_gem_context *ctx;
270 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
272 return ERR_PTR(-ENOMEM);
274 ret = assign_hw_id(dev_priv, &ctx->hw_id);
280 kref_init(&ctx->ref);
281 list_add_tail(&ctx->link, &dev_priv->context_list);
282 ctx->i915 = dev_priv;
284 ctx->ggtt_alignment = get_context_alignment(dev_priv);
286 if (dev_priv->hw_context_size) {
287 struct drm_i915_gem_object *obj;
288 struct i915_vma *vma;
290 obj = i915_gem_alloc_context_obj(dev,
291 dev_priv->hw_context_size);
297 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
299 i915_gem_object_put(obj);
304 ctx->engine[RCS].state = vma;
307 /* Default context will never have a file_priv */
308 if (file_priv != NULL) {
309 ret = idr_alloc(&file_priv->context_idr, ctx,
310 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
314 ret = DEFAULT_CONTEXT_HANDLE;
316 ctx->file_priv = file_priv;
318 ctx->pid = get_task_pid(current, PIDTYPE_PID);
320 ctx->user_handle = ret;
321 /* NB: Mark all slices as needing a remap so that when the context first
322 * loads it will restore whatever remap state already exists. If there
323 * is no remap info, it will be a NOP. */
324 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
326 ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
327 ctx->ring_size = 4 * PAGE_SIZE;
328 ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
329 GEN8_CTX_ADDRESSING_MODE_SHIFT;
330 ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
332 ctx->jump_whitelist = NULL;
333 ctx->jump_whitelist_cmds = 0;
343 * The default context needs to exist per ring that uses contexts. It stores the
344 * context state of the GPU for applications that don't utilize HW contexts, as
345 * well as an idle case.
347 static struct i915_gem_context *
348 i915_gem_create_context(struct drm_device *dev,
349 struct drm_i915_file_private *file_priv)
351 struct i915_gem_context *ctx;
353 lockdep_assert_held(&dev->struct_mutex);
355 ctx = __create_hw_context(dev, file_priv);
359 if (USES_FULL_PPGTT(dev)) {
360 struct i915_hw_ppgtt *ppgtt =
361 i915_ppgtt_create(to_i915(dev), file_priv);
364 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
366 idr_remove(&file_priv->context_idr, ctx->user_handle);
368 return ERR_CAST(ppgtt);
374 trace_i915_context_create(ctx);
380 * i915_gem_context_create_gvt - create a GVT GEM context
383 * This function is used to create a GVT specific GEM context.
386 * pointer to i915_gem_context on success, error pointer if failed
389 struct i915_gem_context *
390 i915_gem_context_create_gvt(struct drm_device *dev)
392 struct i915_gem_context *ctx;
395 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
396 return ERR_PTR(-ENODEV);
398 ret = i915_mutex_lock_interruptible(dev);
402 ctx = i915_gem_create_context(dev, NULL);
406 ctx->execlists_force_single_submission = true;
407 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
409 mutex_unlock(&dev->struct_mutex);
413 static void i915_gem_context_unpin(struct i915_gem_context *ctx,
414 struct intel_engine_cs *engine)
416 if (i915.enable_execlists) {
417 intel_lr_context_unpin(ctx, engine);
419 struct intel_context *ce = &ctx->engine[engine->id];
422 i915_vma_unpin(ce->state);
424 i915_gem_context_put(ctx);
428 int i915_gem_context_init(struct drm_device *dev)
430 struct drm_i915_private *dev_priv = to_i915(dev);
431 struct i915_gem_context *ctx;
433 /* Init should only be called once per module load. Eventually the
434 * restriction on the context_disabled check can be loosened. */
435 if (WARN_ON(dev_priv->kernel_context))
438 if (intel_vgpu_active(dev_priv) &&
439 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
440 if (!i915.enable_execlists) {
441 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
446 /* Using the simple ida interface, the max is limited by sizeof(int) */
447 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
448 ida_init(&dev_priv->context_hw_ida);
450 if (i915.enable_execlists) {
451 /* NB: intentionally left blank. We will allocate our own
452 * backing objects as we need them, thank you very much */
453 dev_priv->hw_context_size = 0;
454 } else if (HAS_HW_CONTEXTS(dev_priv)) {
455 dev_priv->hw_context_size =
456 round_up(get_context_size(dev_priv), 4096);
457 if (dev_priv->hw_context_size > (1<<20)) {
458 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
459 dev_priv->hw_context_size);
460 dev_priv->hw_context_size = 0;
464 ctx = i915_gem_create_context(dev, NULL);
466 DRM_ERROR("Failed to create default global context (error %ld)\n",
471 dev_priv->kernel_context = ctx;
473 DRM_DEBUG_DRIVER("%s context support initialized\n",
474 i915.enable_execlists ? "LR" :
475 dev_priv->hw_context_size ? "HW" : "fake");
479 void i915_gem_context_lost(struct drm_i915_private *dev_priv)
481 struct intel_engine_cs *engine;
483 lockdep_assert_held(&dev_priv->drm.struct_mutex);
485 for_each_engine(engine, dev_priv) {
486 if (engine->last_context) {
487 i915_gem_context_unpin(engine->last_context, engine);
488 engine->last_context = NULL;
492 /* Force the GPU state to be restored on enabling */
493 if (!i915.enable_execlists) {
494 struct i915_gem_context *ctx;
496 list_for_each_entry(ctx, &dev_priv->context_list, link) {
497 if (!i915_gem_context_is_default(ctx))
500 for_each_engine(engine, dev_priv)
501 ctx->engine[engine->id].initialised = false;
503 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
506 for_each_engine(engine, dev_priv) {
507 struct intel_context *kce =
508 &dev_priv->kernel_context->engine[engine->id];
510 kce->initialised = true;
515 void i915_gem_context_fini(struct drm_device *dev)
517 struct drm_i915_private *dev_priv = to_i915(dev);
518 struct i915_gem_context *dctx = dev_priv->kernel_context;
520 lockdep_assert_held(&dev->struct_mutex);
523 dev_priv->kernel_context = NULL;
525 ida_destroy(&dev_priv->context_hw_ida);
528 static int context_idr_cleanup(int id, void *p, void *data)
530 struct i915_gem_context *ctx = p;
536 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
538 struct drm_i915_file_private *file_priv = file->driver_priv;
539 struct i915_gem_context *ctx;
541 idr_init(&file_priv->context_idr);
543 mutex_lock(&dev->struct_mutex);
544 ctx = i915_gem_create_context(dev, file_priv);
545 mutex_unlock(&dev->struct_mutex);
548 idr_destroy(&file_priv->context_idr);
555 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
557 struct drm_i915_file_private *file_priv = file->driver_priv;
559 lockdep_assert_held(&dev->struct_mutex);
561 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
562 idr_destroy(&file_priv->context_idr);
566 mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
568 struct drm_i915_private *dev_priv = req->i915;
569 struct intel_ring *ring = req->ring;
570 struct intel_engine_cs *engine = req->engine;
571 u32 flags = hw_flags | MI_MM_SPACE_GTT;
572 const int num_rings =
573 /* Use an extended w/a on ivb+ if signalling from other rings */
575 INTEL_INFO(dev_priv)->num_rings - 1 :
579 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
580 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
581 * explicitly, so we rely on the value at ring init, stored in
582 * itlb_before_ctx_switch.
584 if (IS_GEN6(dev_priv)) {
585 ret = engine->emit_flush(req, EMIT_INVALIDATE);
590 /* These flags are for resource streamer on HSW+ */
591 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
592 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
593 else if (INTEL_GEN(dev_priv) < 8)
594 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
598 if (INTEL_GEN(dev_priv) >= 7)
599 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
601 ret = intel_ring_begin(req, len);
605 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
606 if (INTEL_GEN(dev_priv) >= 7) {
607 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
609 struct intel_engine_cs *signaller;
611 intel_ring_emit(ring,
612 MI_LOAD_REGISTER_IMM(num_rings));
613 for_each_engine(signaller, dev_priv) {
614 if (signaller == engine)
617 intel_ring_emit_reg(ring,
618 RING_PSMI_CTL(signaller->mmio_base));
619 intel_ring_emit(ring,
620 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
625 intel_ring_emit(ring, MI_NOOP);
626 intel_ring_emit(ring, MI_SET_CONTEXT);
627 intel_ring_emit(ring,
628 i915_ggtt_offset(req->ctx->engine[RCS].state) | flags);
630 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
631 * WaMiSetContext_Hang:snb,ivb,vlv
633 intel_ring_emit(ring, MI_NOOP);
635 if (INTEL_GEN(dev_priv) >= 7) {
637 struct intel_engine_cs *signaller;
638 i915_reg_t last_reg = {}; /* keep gcc quiet */
640 intel_ring_emit(ring,
641 MI_LOAD_REGISTER_IMM(num_rings));
642 for_each_engine(signaller, dev_priv) {
643 if (signaller == engine)
646 last_reg = RING_PSMI_CTL(signaller->mmio_base);
647 intel_ring_emit_reg(ring, last_reg);
648 intel_ring_emit(ring,
649 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
652 /* Insert a delay before the next switch! */
653 intel_ring_emit(ring,
654 MI_STORE_REGISTER_MEM |
655 MI_SRM_LRM_GLOBAL_GTT);
656 intel_ring_emit_reg(ring, last_reg);
657 intel_ring_emit(ring,
658 i915_ggtt_offset(engine->scratch));
659 intel_ring_emit(ring, MI_NOOP);
661 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
664 intel_ring_advance(ring);
669 static int remap_l3(struct drm_i915_gem_request *req, int slice)
671 u32 *remap_info = req->i915->l3_parity.remap_info[slice];
672 struct intel_ring *ring = req->ring;
678 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
683 * Note: We do not worry about the concurrent register cacheline hang
684 * here because no other code should access these registers other than
685 * at initialization time.
687 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
688 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
689 intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));
690 intel_ring_emit(ring, remap_info[i]);
692 intel_ring_emit(ring, MI_NOOP);
693 intel_ring_advance(ring);
698 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
699 struct intel_engine_cs *engine,
700 struct i915_gem_context *to)
705 if (!to->engine[RCS].initialised)
708 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
711 return to == engine->last_context;
715 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
716 struct intel_engine_cs *engine,
717 struct i915_gem_context *to)
722 /* Always load the ppgtt on first use */
723 if (!engine->last_context)
726 /* Same context without new entries, skip */
727 if (engine->last_context == to &&
728 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
731 if (engine->id != RCS)
734 if (INTEL_GEN(engine->i915) < 8)
741 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
742 struct i915_gem_context *to,
748 if (!IS_GEN8(to->i915))
751 if (hw_flags & MI_RESTORE_INHIBIT)
757 static int do_rcs_switch(struct drm_i915_gem_request *req)
759 struct i915_gem_context *to = req->ctx;
760 struct intel_engine_cs *engine = req->engine;
761 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
762 struct i915_vma *vma = to->engine[RCS].state;
763 struct i915_gem_context *from;
767 if (skip_rcs_switch(ppgtt, engine, to))
770 /* Clear this page out of any CPU caches for coherent swap-in/out. */
771 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
772 ret = i915_gem_object_set_to_gtt_domain(vma->obj, false);
777 /* Trying to pin first makes error handling easier. */
778 ret = i915_vma_pin(vma, 0, to->ggtt_alignment, PIN_GLOBAL);
783 * Pin can switch back to the default context if we end up calling into
784 * evict_everything - as a last ditch gtt defrag effort that also
785 * switches to the default context. Hence we need to reload from here.
787 * XXX: Doing so is painfully broken!
789 from = engine->last_context;
791 if (needs_pd_load_pre(ppgtt, engine, to)) {
792 /* Older GENs and non render rings still want the load first,
793 * "PP_DCLV followed by PP_DIR_BASE register through Load
794 * Register Immediate commands in Ring Buffer before submitting
796 trace_switch_mm(engine, to);
797 ret = ppgtt->switch_mm(ppgtt, req);
802 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
803 /* NB: If we inhibit the restore, the context is not allowed to
804 * die because future work may end up depending on valid address
805 * space. This means we must enforce that a page table load
806 * occur when this occurs. */
807 hw_flags = MI_RESTORE_INHIBIT;
808 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
809 hw_flags = MI_FORCE_RESTORE;
813 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
814 ret = mi_set_context(req, hw_flags);
819 /* The backing object for the context is done after switching to the
820 * *next* context. Therefore we cannot retire the previous context until
821 * the next context has already started running. In fact, the below code
822 * is a bit suboptimal because the retiring can occur simply after the
823 * MI_SET_CONTEXT instead of when the next seqno has completed.
826 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
827 * whole damn pipeline, we don't need to explicitly mark the
828 * object dirty. The only exception is that the context must be
829 * correct in case the object gets swapped out. Ideally we'd be
830 * able to defer doing this until we know the object would be
831 * swapped, but there is no way to do that yet.
833 i915_vma_move_to_active(from->engine[RCS].state, req, 0);
834 /* state is kept alive until the next request */
835 i915_vma_unpin(from->engine[RCS].state);
836 i915_gem_context_put(from);
838 engine->last_context = i915_gem_context_get(to);
840 /* GEN8 does *not* require an explicit reload if the PDPs have been
841 * setup, and we do not wish to move them.
843 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
844 trace_switch_mm(engine, to);
845 ret = ppgtt->switch_mm(ppgtt, req);
846 /* The hardware context switch is emitted, but we haven't
847 * actually changed the state - so it's probably safe to bail
848 * here. Still, let the user know something dangerous has
856 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
858 for (i = 0; i < MAX_L3_SLICES; i++) {
859 if (!(to->remap_slice & (1<<i)))
862 ret = remap_l3(req, i);
866 to->remap_slice &= ~(1<<i);
869 if (!to->engine[RCS].initialised) {
870 if (engine->init_context) {
871 ret = engine->init_context(req);
875 to->engine[RCS].initialised = true;
886 * i915_switch_context() - perform a GPU context switch.
887 * @req: request for which we'll execute the context switch
889 * The context life cycle is simple. The context refcount is incremented and
890 * decremented by 1 and create and destroy. If the context is in use by the GPU,
891 * it will have a refcount > 1. This allows us to destroy the context abstract
892 * object while letting the normal object tracking destroy the backing BO.
894 * This function should not be used in execlists mode. Instead the context is
895 * switched by writing to the ELSP and requests keep a reference to their
898 int i915_switch_context(struct drm_i915_gem_request *req)
900 struct intel_engine_cs *engine = req->engine;
902 lockdep_assert_held(&req->i915->drm.struct_mutex);
903 if (i915.enable_execlists)
906 if (!req->ctx->engine[engine->id].state) {
907 struct i915_gem_context *to = req->ctx;
908 struct i915_hw_ppgtt *ppgtt =
909 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
911 if (needs_pd_load_pre(ppgtt, engine, to)) {
914 trace_switch_mm(engine, to);
915 ret = ppgtt->switch_mm(ppgtt, req);
919 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
922 if (to != engine->last_context) {
923 if (engine->last_context)
924 i915_gem_context_put(engine->last_context);
925 engine->last_context = i915_gem_context_get(to);
931 return do_rcs_switch(req);
934 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
936 struct intel_engine_cs *engine;
938 for_each_engine(engine, dev_priv) {
939 struct drm_i915_gem_request *req;
942 if (engine->last_context == NULL)
945 if (engine->last_context == dev_priv->kernel_context)
948 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
952 ret = i915_switch_context(req);
953 i915_add_request_no_flush(req);
961 static bool contexts_enabled(struct drm_device *dev)
963 return i915.enable_execlists || to_i915(dev)->hw_context_size;
966 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
967 struct drm_file *file)
969 struct drm_i915_gem_context_create *args = data;
970 struct drm_i915_file_private *file_priv = file->driver_priv;
971 struct i915_gem_context *ctx;
974 if (!contexts_enabled(dev))
980 ret = i915_mutex_lock_interruptible(dev);
984 ctx = i915_gem_create_context(dev, file_priv);
985 mutex_unlock(&dev->struct_mutex);
989 args->ctx_id = ctx->user_handle;
990 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
995 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file)
998 struct drm_i915_gem_context_destroy *args = data;
999 struct drm_i915_file_private *file_priv = file->driver_priv;
1000 struct i915_gem_context *ctx;
1006 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
1009 ret = i915_mutex_lock_interruptible(dev);
1013 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1015 mutex_unlock(&dev->struct_mutex);
1016 return PTR_ERR(ctx);
1019 idr_remove(&file_priv->context_idr, ctx->user_handle);
1021 mutex_unlock(&dev->struct_mutex);
1023 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
1027 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1028 struct drm_file *file)
1030 struct drm_i915_file_private *file_priv = file->driver_priv;
1031 struct drm_i915_gem_context_param *args = data;
1032 struct i915_gem_context *ctx;
1035 ret = i915_mutex_lock_interruptible(dev);
1039 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1041 mutex_unlock(&dev->struct_mutex);
1042 return PTR_ERR(ctx);
1046 switch (args->param) {
1047 case I915_CONTEXT_PARAM_BAN_PERIOD:
1048 args->value = ctx->hang_stats.ban_period_seconds;
1050 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1051 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1053 case I915_CONTEXT_PARAM_GTT_SIZE:
1055 args->value = ctx->ppgtt->base.total;
1056 else if (to_i915(dev)->mm.aliasing_ppgtt)
1057 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1059 args->value = to_i915(dev)->ggtt.base.total;
1061 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1062 args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE);
1068 mutex_unlock(&dev->struct_mutex);
1073 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1074 struct drm_file *file)
1076 struct drm_i915_file_private *file_priv = file->driver_priv;
1077 struct drm_i915_gem_context_param *args = data;
1078 struct i915_gem_context *ctx;
1081 ret = i915_mutex_lock_interruptible(dev);
1085 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1087 mutex_unlock(&dev->struct_mutex);
1088 return PTR_ERR(ctx);
1091 switch (args->param) {
1092 case I915_CONTEXT_PARAM_BAN_PERIOD:
1095 else if (args->value < ctx->hang_stats.ban_period_seconds &&
1096 !capable(CAP_SYS_ADMIN))
1099 ctx->hang_stats.ban_period_seconds = args->value;
1101 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1105 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1106 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1109 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1114 ctx->flags |= CONTEXT_NO_ERROR_CAPTURE;
1116 ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE;
1123 mutex_unlock(&dev->struct_mutex);
1128 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1129 void *data, struct drm_file *file)
1131 struct drm_i915_private *dev_priv = to_i915(dev);
1132 struct drm_i915_reset_stats *args = data;
1133 struct i915_ctx_hang_stats *hs;
1134 struct i915_gem_context *ctx;
1137 if (args->flags || args->pad)
1140 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1143 ret = i915_mutex_lock_interruptible(dev);
1147 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1149 mutex_unlock(&dev->struct_mutex);
1150 return PTR_ERR(ctx);
1152 hs = &ctx->hang_stats;
1154 if (capable(CAP_SYS_ADMIN))
1155 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1157 args->reset_count = 0;
1159 args->batch_active = hs->batch_active;
1160 args->batch_pending = hs->batch_pending;
1162 mutex_unlock(&dev->struct_mutex);