drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <linux/dma_remapping.h>
  30 #include <linux/reservation.h>
  31 #include <linux/uaccess.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35
  36 #include "i915_drv.h"
  37 #include "i915_gem_dmabuf.h"
  38 #include "i915_trace.h"
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41
  42 #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
  43
  44 #define  __EXEC_OBJECT_HAS_PIN          (1<<31)
  45 #define  __EXEC_OBJECT_HAS_FENCE        (1<<30)
  46 #define  __EXEC_OBJECT_NEEDS_MAP        (1<<29)
  47 #define  __EXEC_OBJECT_NEEDS_BIAS       (1<<28)
  48 #define  __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
  49
  50 #define BATCH_OFFSET_BIAS (256*1024)
  51
  52 struct i915_execbuffer_params {
  53         struct drm_device               *dev;
  54         struct drm_file                 *file;
  55         struct i915_vma                 *batch;
  56         u32                             dispatch_flags;
  57         u32                             args_batch_start_offset;
  58         u64                             args_batch_len;
  59         struct intel_engine_cs          *engine;
  60         struct i915_gem_context         *ctx;
  61         struct drm_i915_gem_request     *request;
  62 };
  63
  64 struct eb_vmas {
  65         struct drm_i915_private *i915;
  66         struct list_head vmas;
  67         int and;
  68         union {
  69                 struct i915_vma *lut[0];
  70                 struct hlist_head buckets[0];
  71         };
  72 };
  73
  74 static struct eb_vmas *
  75 eb_create(struct drm_i915_private *i915,
  76           struct drm_i915_gem_execbuffer2 *args)
  77 {
  78         struct eb_vmas *eb = NULL;
  79
  80         if (args->flags & I915_EXEC_HANDLE_LUT) {
  81                 unsigned size = args->buffer_count;
  82                 size *= sizeof(struct i915_vma *);
  83                 size += sizeof(struct eb_vmas);
  84                 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  85         }
  86
  87         if (eb == NULL) {
  88                 unsigned size = args->buffer_count;
  89                 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  90                 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  91                 while (count > 2*size)
  92                         count >>= 1;
  93                 eb = kzalloc(count*sizeof(struct hlist_head) +
  94                              sizeof(struct eb_vmas),
  95                              GFP_TEMPORARY);
  96                 if (eb == NULL)
  97                         return eb;
  98
  99                 eb->and = count - 1;
 100         } else
 101                 eb->and = -args->buffer_count;
 102
 103         eb->i915 = i915;
 104         INIT_LIST_HEAD(&eb->vmas);
 105         return eb;
 106 }
 107
 108 static void
 109 eb_reset(struct eb_vmas *eb)
 110 {
 111         if (eb->and >= 0)
 112                 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 113 }
 114
 115 static struct i915_vma *
 116 eb_get_batch(struct eb_vmas *eb)
 117 {
 118         struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
 119
 120         /*
 121          * SNA is doing fancy tricks with compressing batch buffers, which leads
 122          * to negative relocation deltas. Usually that works out ok since the
 123          * relocate address is still positive, except when the batch is placed
 124          * very low in the GTT. Ensure this doesn't happen.
 125          *
 126          * Note that actual hangs have only been observed on gen7, but for
 127          * paranoia do it everywhere.
 128          */
 129         if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
 130                 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 131
 132         return vma;
 133 }
 134
 135 static int
 136 eb_lookup_vmas(struct eb_vmas *eb,
 137                struct drm_i915_gem_exec_object2 *exec,
 138                const struct drm_i915_gem_execbuffer2 *args,
 139                struct i915_address_space *vm,
 140                struct drm_file *file)
 141 {
 142         struct drm_i915_gem_object *obj;
 143         struct list_head objects;
 144         int i, ret;
 145
 146         INIT_LIST_HEAD(&objects);
 147         spin_lock(&file->table_lock);
 148         /* Grab a reference to the object and release the lock so we can lookup
 149          * or create the VMA without using GFP_ATOMIC */
 150         for (i = 0; i < args->buffer_count; i++) {
 151                 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
 152                 if (obj == NULL) {
 153                         spin_unlock(&file->table_lock);
 154                         DRM_DEBUG("Invalid object handle %d at index %d\n",
 155                                    exec[i].handle, i);
 156                         ret = -ENOENT;
 157                         goto err;
 158                 }
 159
 160                 if (!list_empty(&obj->obj_exec_link)) {
 161                         spin_unlock(&file->table_lock);
 162                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
 163                                    obj, exec[i].handle, i);
 164                         ret = -EINVAL;
 165                         goto err;
 166                 }
 167
 168                 i915_gem_object_get(obj);
 169                 list_add_tail(&obj->obj_exec_link, &objects);
 170         }
 171         spin_unlock(&file->table_lock);
 172
 173         i = 0;
 174         while (!list_empty(&objects)) {
 175                 struct i915_vma *vma;
 176
 177                 obj = list_first_entry(&objects,
 178                                        struct drm_i915_gem_object,
 179                                        obj_exec_link);
 180
 181                 /*
 182                  * NOTE: We can leak any vmas created here when something fails
 183                  * later on. But that's no issue since vma_unbind can deal with
 184                  * vmas which are not actually bound. And since only
 185                  * lookup_or_create exists as an interface to get at the vma
 186                  * from the (obj, vm) we don't run the risk of creating
 187                  * duplicated vmas for the same vm.
 188                  */
 189                 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, NULL);
 190                 if (unlikely(IS_ERR(vma))) {
 191                         DRM_DEBUG("Failed to lookup VMA\n");
 192                         ret = PTR_ERR(vma);
 193                         goto err;
 194                 }
 195
 196                 /* Transfer ownership from the objects list to the vmas list. */
 197                 list_add_tail(&vma->exec_list, &eb->vmas);
 198                 list_del_init(&obj->obj_exec_link);
 199
 200                 vma->exec_entry = &exec[i];
 201                 if (eb->and < 0) {
 202                         eb->lut[i] = vma;
 203                 } else {
 204                         uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
 205                         vma->exec_handle = handle;
 206                         hlist_add_head(&vma->exec_node,
 207                                        &eb->buckets[handle & eb->and]);
 208                 }
 209                 ++i;
 210         }
 211
 212         return 0;
 213
 214
 215 err:
 216         while (!list_empty(&objects)) {
 217                 obj = list_first_entry(&objects,
 218                                        struct drm_i915_gem_object,
 219                                        obj_exec_link);
 220                 list_del_init(&obj->obj_exec_link);
 221                 i915_gem_object_put(obj);
 222         }
 223         /*
 224          * Objects already transfered to the vmas list will be unreferenced by
 225          * eb_destroy.
 226          */
 227
 228         return ret;
 229 }
 230
 231 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
 232 {
 233         if (eb->and < 0) {
 234                 if (handle >= -eb->and)
 235                         return NULL;
 236                 return eb->lut[handle];
 237         } else {
 238                 struct hlist_head *head;
 239                 struct i915_vma *vma;
 240
 241                 head = &eb->buckets[handle & eb->and];
 242                 hlist_for_each_entry(vma, head, exec_node) {
 243                         if (vma->exec_handle == handle)
 244                                 return vma;
 245                 }
 246                 return NULL;
 247         }
 248 }
 249
 250 static void
 251 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
 252 {
 253         struct drm_i915_gem_exec_object2 *entry;
 254
 255         if (!drm_mm_node_allocated(&vma->node))
 256                 return;
 257
 258         entry = vma->exec_entry;
 259
 260         if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
 261                 i915_vma_unpin_fence(vma);
 262
 263         if (entry->flags & __EXEC_OBJECT_HAS_PIN)
 264                 __i915_vma_unpin(vma);
 265
 266         entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
 267 }
 268
 269 static void eb_destroy(struct eb_vmas *eb)
 270 {
 271         while (!list_empty(&eb->vmas)) {
 272                 struct i915_vma *vma;
 273
 274                 vma = list_first_entry(&eb->vmas,
 275                                        struct i915_vma,
 276                                        exec_list);
 277                 list_del_init(&vma->exec_list);
 278                 i915_gem_execbuffer_unreserve_vma(vma);
 279                 i915_vma_put(vma);
 280         }
 281         kfree(eb);
 282 }
 283
 284 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 285 {
 286         if (!i915_gem_object_has_struct_page(obj))
 287                 return false;
 288
 289         if (DBG_USE_CPU_RELOC)
 290                 return DBG_USE_CPU_RELOC > 0;
 291
 292         return (HAS_LLC(obj->base.dev) ||
 293                 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 294                 obj->cache_level != I915_CACHE_NONE);
 295 }
 296
 297 /* Used to convert any address to canonical form.
 298  * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
 299  * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
 300  * addresses to be in a canonical form:
 301  * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
 302  * canonical form [63:48] == [47]."
 303  */
 304 #define GEN8_HIGH_ADDRESS_BIT 47
 305 static inline uint64_t gen8_canonical_addr(uint64_t address)
 306 {
 307         return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
 308 }
 309
 310 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
 311 {
 312         return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
 313 }
 314
 315 static inline uint64_t
 316 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
 317                   uint64_t target_offset)
 318 {
 319         return gen8_canonical_addr((int)reloc->delta + target_offset);
 320 }
 321
 322 struct reloc_cache {
 323         struct drm_i915_private *i915;
 324         struct drm_mm_node node;
 325         unsigned long vaddr;
 326         unsigned int page;
 327         bool use_64bit_reloc;
 328 };
 329
 330 static void reloc_cache_init(struct reloc_cache *cache,
 331                              struct drm_i915_private *i915)
 332 {
 333         cache->page = -1;
 334         cache->vaddr = 0;
 335         cache->i915 = i915;
 336         cache->use_64bit_reloc = INTEL_GEN(cache->i915) >= 8;
 337         cache->node.allocated = false;
 338 }
 339
 340 static inline void *unmask_page(unsigned long p)
 341 {
 342         return (void *)(uintptr_t)(p & PAGE_MASK);
 343 }
 344
 345 static inline unsigned int unmask_flags(unsigned long p)
 346 {
 347         return p & ~PAGE_MASK;
 348 }
 349
 350 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
 351
 352 static void reloc_cache_fini(struct reloc_cache *cache)
 353 {
 354         void *vaddr;
 355
 356         if (!cache->vaddr)
 357                 return;
 358
 359         vaddr = unmask_page(cache->vaddr);
 360         if (cache->vaddr & KMAP) {
 361                 if (cache->vaddr & CLFLUSH_AFTER)
 362                         mb();
 363
 364                 kunmap_atomic(vaddr);
 365                 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
 366         } else {
 367                 wmb();
 368                 io_mapping_unmap_atomic((void __iomem *)vaddr);
 369                 if (cache->node.allocated) {
 370                         struct i915_ggtt *ggtt = &cache->i915->ggtt;
 371
 372                         ggtt->base.clear_range(&ggtt->base,
 373                                                cache->node.start,
 374                                                cache->node.size,
 375                                                true);
 376                         drm_mm_remove_node(&cache->node);
 377                 } else {
 378                         i915_vma_unpin((struct i915_vma *)cache->node.mm);
 379                 }
 380         }
 381 }
 382
 383 static void *reloc_kmap(struct drm_i915_gem_object *obj,
 384                         struct reloc_cache *cache,
 385                         int page)
 386 {
 387         void *vaddr;
 388
 389         if (cache->vaddr) {
 390                 kunmap_atomic(unmask_page(cache->vaddr));
 391         } else {
 392                 unsigned int flushes;
 393                 int ret;
 394
 395                 ret = i915_gem_obj_prepare_shmem_write(obj, &flushes);
 396                 if (ret)
 397                         return ERR_PTR(ret);
 398
 399                 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
 400                 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
 401
 402                 cache->vaddr = flushes | KMAP;
 403                 cache->node.mm = (void *)obj;
 404                 if (flushes)
 405                         mb();
 406         }
 407
 408         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
 409         cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
 410         cache->page = page;
 411
 412         return vaddr;
 413 }
 414
 415 static void *reloc_iomap(struct drm_i915_gem_object *obj,
 416                          struct reloc_cache *cache,
 417                          int page)
 418 {
 419         struct i915_ggtt *ggtt = &cache->i915->ggtt;
 420         unsigned long offset;
 421         void *vaddr;
 422
 423         if (cache->node.allocated) {
 424                 wmb();
 425                 ggtt->base.insert_page(&ggtt->base,
 426                                        i915_gem_object_get_dma_address(obj, page),
 427                                        cache->node.start, I915_CACHE_NONE, 0);
 428                 cache->page = page;
 429                 return unmask_page(cache->vaddr);
 430         }
 431
 432         if (cache->vaddr) {
 433                 io_mapping_unmap_atomic(unmask_page(cache->vaddr));
 434         } else {
 435                 struct i915_vma *vma;
 436                 int ret;
 437
 438                 if (use_cpu_reloc(obj))
 439                         return NULL;
 440
 441                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
 442                 if (ret)
 443                         return ERR_PTR(ret);
 444
 445                 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
 446                                                PIN_MAPPABLE | PIN_NONBLOCK);
 447                 if (IS_ERR(vma)) {
 448                         memset(&cache->node, 0, sizeof(cache->node));
 449                         ret = drm_mm_insert_node_in_range_generic
 450                                 (&ggtt->base.mm, &cache->node,
 451                                  4096, 0, 0,
 452                                  0, ggtt->mappable_end,
 453                                  DRM_MM_SEARCH_DEFAULT,
 454                                  DRM_MM_CREATE_DEFAULT);
 455                         if (ret) /* no inactive aperture space, use cpu reloc */
 456                                 return NULL;
 457                 } else {
 458                         ret = i915_vma_put_fence(vma);
 459                         if (ret) {
 460                                 i915_vma_unpin(vma);
 461                                 return ERR_PTR(ret);
 462                         }
 463
 464                         cache->node.start = vma->node.start;
 465                         cache->node.mm = (void *)vma;
 466                 }
 467         }
 468
 469         offset = cache->node.start;
 470         if (cache->node.allocated) {
 471                 ggtt->base.insert_page(&ggtt->base,
 472                                        i915_gem_object_get_dma_address(obj, page),
 473                                        offset, I915_CACHE_NONE, 0);
 474         } else {
 475                 offset += page << PAGE_SHIFT;
 476         }
 477
 478         vaddr = io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset);
 479         cache->page = page;
 480         cache->vaddr = (unsigned long)vaddr;
 481
 482         return vaddr;
 483 }
 484
 485 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
 486                          struct reloc_cache *cache,
 487                          int page)
 488 {
 489         void *vaddr;
 490
 491         if (cache->page == page) {
 492                 vaddr = unmask_page(cache->vaddr);
 493         } else {
 494                 vaddr = NULL;
 495                 if ((cache->vaddr & KMAP) == 0)
 496                         vaddr = reloc_iomap(obj, cache, page);
 497                 if (!vaddr)
 498                         vaddr = reloc_kmap(obj, cache, page);
 499         }
 500
 501         return vaddr;
 502 }
 503
 504 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 505 {
 506         if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
 507                 if (flushes & CLFLUSH_BEFORE) {
 508                         clflushopt(addr);
 509                         mb();
 510                 }
 511
 512                 *addr = value;
 513
 514                 /* Writes to the same cacheline are serialised by the CPU
 515                  * (including clflush). On the write path, we only require
 516                  * that it hits memory in an orderly fashion and place
 517                  * mb barriers at the start and end of the relocation phase
 518                  * to ensure ordering of clflush wrt to the system.
 519                  */
 520                 if (flushes & CLFLUSH_AFTER)
 521                         clflushopt(addr);
 522         } else
 523                 *addr = value;
 524 }
 525
 526 static int
 527 relocate_entry(struct drm_i915_gem_object *obj,
 528                const struct drm_i915_gem_relocation_entry *reloc,
 529                struct reloc_cache *cache,
 530                u64 target_offset)
 531 {
 532         u64 offset = reloc->offset;
 533         bool wide = cache->use_64bit_reloc;
 534         void *vaddr;
 535
 536         target_offset = relocation_target(reloc, target_offset);
 537 repeat:
 538         vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT);
 539         if (IS_ERR(vaddr))
 540                 return PTR_ERR(vaddr);
 541
 542         clflush_write32(vaddr + offset_in_page(offset),
 543                         lower_32_bits(target_offset),
 544                         cache->vaddr);
 545
 546         if (wide) {
 547                 offset += sizeof(u32);
 548                 target_offset >>= 32;
 549                 wide = false;
 550                 goto repeat;
 551         }
 552
 553         return 0;
 554 }
 555
 556 static bool object_is_idle(struct drm_i915_gem_object *obj)
 557 {
 558         unsigned long active = i915_gem_object_get_active(obj);
 559         int idx;
 560
 561         for_each_active(active, idx) {
 562                 if (!i915_gem_active_is_idle(&obj->last_read[idx],
 563                                              &obj->base.dev->struct_mutex))
 564                         return false;
 565         }
 566
 567         return true;
 568 }
 569
 570 static int
 571 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 572                                    struct eb_vmas *eb,
 573                                    struct drm_i915_gem_relocation_entry *reloc,
 574                                    struct reloc_cache *cache)
 575 {
 576         struct drm_device *dev = obj->base.dev;
 577         struct drm_gem_object *target_obj;
 578         struct drm_i915_gem_object *target_i915_obj;
 579         struct i915_vma *target_vma;
 580         uint64_t target_offset;
 581         int ret;
 582
 583         /* we've already hold a reference to all valid objects */
 584         target_vma = eb_get_vma(eb, reloc->target_handle);
 585         if (unlikely(target_vma == NULL))
 586                 return -ENOENT;
 587         target_i915_obj = target_vma->obj;
 588         target_obj = &target_vma->obj->base;
 589
 590         target_offset = gen8_canonical_addr(target_vma->node.start);
 591
 592         /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 593          * pipe_control writes because the gpu doesn't properly redirect them
 594          * through the ppgtt for non_secure batchbuffers. */
 595         if (unlikely(IS_GEN6(dev) &&
 596             reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
 597                 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
 598                                     PIN_GLOBAL);
 599                 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
 600                         return ret;
 601         }
 602
 603         /* Validate that the target is in a valid r/w GPU domain */
 604         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 605                 DRM_DEBUG("reloc with multiple write domains: "
 606                           "obj %p target %d offset %d "
 607                           "read %08x write %08x",
 608                           obj, reloc->target_handle,
 609                           (int) reloc->offset,
 610                           reloc->read_domains,
 611                           reloc->write_domain);
 612                 return -EINVAL;
 613         }
 614         if (unlikely((reloc->write_domain | reloc->read_domains)
 615                      & ~I915_GEM_GPU_DOMAINS)) {
 616                 DRM_DEBUG("reloc with read/write non-GPU domains: "
 617                           "obj %p target %d offset %d "
 618                           "read %08x write %08x",
 619                           obj, reloc->target_handle,
 620                           (int) reloc->offset,
 621                           reloc->read_domains,
 622                           reloc->write_domain);
 623                 return -EINVAL;
 624         }
 625
 626         target_obj->pending_read_domains |= reloc->read_domains;
 627         target_obj->pending_write_domain |= reloc->write_domain;
 628
 629         /* If the relocation already has the right value in it, no
 630          * more work needs to be done.
 631          */
 632         if (target_offset == reloc->presumed_offset)
 633                 return 0;
 634
 635         /* Check that the relocation address is valid... */
 636         if (unlikely(reloc->offset >
 637                      obj->base.size - (cache->use_64bit_reloc ? 8 : 4))) {
 638                 DRM_DEBUG("Relocation beyond object bounds: "
 639                           "obj %p target %d offset %d size %d.\n",
 640                           obj, reloc->target_handle,
 641                           (int) reloc->offset,
 642                           (int) obj->base.size);
 643                 return -EINVAL;
 644         }
 645         if (unlikely(reloc->offset & 3)) {
 646                 DRM_DEBUG("Relocation not 4-byte aligned: "
 647                           "obj %p target %d offset %d.\n",
 648                           obj, reloc->target_handle,
 649                           (int) reloc->offset);
 650                 return -EINVAL;
 651         }
 652
 653         /* We can't wait for rendering with pagefaults disabled */
 654         if (pagefault_disabled() && !object_is_idle(obj))
 655                 return -EFAULT;
 656
 657         ret = relocate_entry(obj, reloc, cache, target_offset);
 658         if (ret)
 659                 return ret;
 660
 661         /* and update the user's relocation entry */
 662         reloc->presumed_offset = target_offset;
 663         return 0;
 664 }
 665
 666 static int
 667 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
 668                                  struct eb_vmas *eb)
 669 {
 670 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
 671         struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
 672         struct drm_i915_gem_relocation_entry __user *user_relocs;
 673         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 674         struct reloc_cache cache;
 675         int remain, ret = 0;
 676
 677         user_relocs = u64_to_user_ptr(entry->relocs_ptr);
 678         reloc_cache_init(&cache, eb->i915);
 679
 680         remain = entry->relocation_count;
 681         while (remain) {
 682                 struct drm_i915_gem_relocation_entry *r = stack_reloc;
 683                 int count = remain;
 684                 if (count > ARRAY_SIZE(stack_reloc))
 685                         count = ARRAY_SIZE(stack_reloc);
 686                 remain -= count;
 687
 688                 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) {
 689                         ret = -EFAULT;
 690                         goto out;
 691                 }
 692
 693                 do {
 694                         u64 offset = r->presumed_offset;
 695
 696                         ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, &cache);
 697                         if (ret)
 698                                 goto out;
 699
 700                         if (r->presumed_offset != offset &&
 701                             __put_user(r->presumed_offset,
 702                                        &user_relocs->presumed_offset)) {
 703                                 ret = -EFAULT;
 704                                 goto out;
 705                         }
 706
 707                         user_relocs++;
 708                         r++;
 709                 } while (--count);
 710         }
 711
 712 out:
 713         reloc_cache_fini(&cache);
 714         return ret;
 715 #undef N_RELOC
 716 }
 717
 718 static int
 719 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
 720                                       struct eb_vmas *eb,
 721                                       struct drm_i915_gem_relocation_entry *relocs)
 722 {
 723         const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 724         struct reloc_cache cache;
 725         int i, ret = 0;
 726
 727         reloc_cache_init(&cache, eb->i915);
 728         for (i = 0; i < entry->relocation_count; i++) {
 729                 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], &cache);
 730                 if (ret)
 731                         break;
 732         }
 733         reloc_cache_fini(&cache);
 734
 735         return ret;
 736 }
 737
 738 static int
 739 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
 740 {
 741         struct i915_vma *vma;
 742         int ret = 0;
 743
 744         /* This is the fast path and we cannot handle a pagefault whilst
 745          * holding the struct mutex lest the user pass in the relocations
 746          * contained within a mmaped bo. For in such a case we, the page
 747          * fault handler would call i915_gem_fault() and we would try to
 748          * acquire the struct mutex again. Obviously this is bad and so
 749          * lockdep complains vehemently.
 750          */
 751         pagefault_disable();
 752         list_for_each_entry(vma, &eb->vmas, exec_list) {
 753                 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
 754                 if (ret)
 755                         break;
 756         }
 757         pagefault_enable();
 758
 759         return ret;
 760 }
 761
 762 static bool only_mappable_for_reloc(unsigned int flags)
 763 {
 764         return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
 765                 __EXEC_OBJECT_NEEDS_MAP;
 766 }
 767
 768 static int
 769 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 770                                 struct intel_engine_cs *engine,
 771                                 bool *need_reloc)
 772 {
 773         struct drm_i915_gem_object *obj = vma->obj;
 774         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 775         uint64_t flags;
 776         int ret;
 777
 778         flags = PIN_USER;
 779         if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
 780                 flags |= PIN_GLOBAL;
 781
 782         if (!drm_mm_node_allocated(&vma->node)) {
 783                 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
 784                  * limit address to the first 4GBs for unflagged objects.
 785                  */
 786                 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
 787                         flags |= PIN_ZONE_4G;
 788                 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
 789                         flags |= PIN_GLOBAL | PIN_MAPPABLE;
 790                 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
 791                         flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
 792                 if (entry->flags & EXEC_OBJECT_PINNED)
 793                         flags |= entry->offset | PIN_OFFSET_FIXED;
 794                 if ((flags & PIN_MAPPABLE) == 0)
 795                         flags |= PIN_HIGH;
 796         }
 797
 798         ret = i915_vma_pin(vma,
 799                            entry->pad_to_size,
 800                            entry->alignment,
 801                            flags);
 802         if ((ret == -ENOSPC || ret == -E2BIG) &&
 803             only_mappable_for_reloc(entry->flags))
 804                 ret = i915_vma_pin(vma,
 805                                    entry->pad_to_size,
 806                                    entry->alignment,
 807                                    flags & ~PIN_MAPPABLE);
 808         if (ret)
 809                 return ret;
 810
 811         entry->flags |= __EXEC_OBJECT_HAS_PIN;
 812
 813         if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 814                 ret = i915_vma_get_fence(vma);
 815                 if (ret)
 816                         return ret;
 817
 818                 if (i915_vma_pin_fence(vma))
 819                         entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 820         }
 821
 822         if (entry->offset != vma->node.start) {
 823                 entry->offset = vma->node.start;
 824                 *need_reloc = true;
 825         }
 826
 827         if (entry->flags & EXEC_OBJECT_WRITE) {
 828                 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
 829                 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static bool
 836 need_reloc_mappable(struct i915_vma *vma)
 837 {
 838         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 839
 840         if (entry->relocation_count == 0)
 841                 return false;
 842
 843         if (!i915_vma_is_ggtt(vma))
 844                 return false;
 845
 846         /* See also use_cpu_reloc() */
 847         if (HAS_LLC(vma->obj->base.dev))
 848                 return false;
 849
 850         if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
 851                 return false;
 852
 853         return true;
 854 }
 855
 856 static bool
 857 eb_vma_misplaced(struct i915_vma *vma)
 858 {
 859         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 860
 861         WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
 862                 !i915_vma_is_ggtt(vma));
 863
 864         if (entry->alignment &&
 865             vma->node.start & (entry->alignment - 1))
 866                 return true;
 867
 868         if (vma->node.size < entry->pad_to_size)
 869                 return true;
 870
 871         if (entry->flags & EXEC_OBJECT_PINNED &&
 872             vma->node.start != entry->offset)
 873                 return true;
 874
 875         if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
 876             vma->node.start < BATCH_OFFSET_BIAS)
 877                 return true;
 878
 879         /* avoid costly ping-pong once a batch bo ended up non-mappable */
 880         if (entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
 881             !i915_vma_is_map_and_fenceable(vma))
 882                 return !only_mappable_for_reloc(entry->flags);
 883
 884         if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
 885             (vma->node.start + vma->node.size + 4095) >> 32)
 886                 return true;
 887
 888         return false;
 889 }
 890
 891 static int
 892 i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
 893                             struct list_head *vmas,
 894                             struct i915_gem_context *ctx,
 895                             bool *need_relocs)
 896 {
 897         struct drm_i915_gem_object *obj;
 898         struct i915_vma *vma;
 899         struct i915_address_space *vm;
 900         struct list_head ordered_vmas;
 901         struct list_head pinned_vmas;
 902         bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
 903         int retry;
 904
 905         vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
 906
 907         INIT_LIST_HEAD(&ordered_vmas);
 908         INIT_LIST_HEAD(&pinned_vmas);
 909         while (!list_empty(vmas)) {
 910                 struct drm_i915_gem_exec_object2 *entry;
 911                 bool need_fence, need_mappable;
 912
 913                 vma = list_first_entry(vmas, struct i915_vma, exec_list);
 914                 obj = vma->obj;
 915                 entry = vma->exec_entry;
 916
 917                 if (ctx->flags & CONTEXT_NO_ZEROMAP)
 918                         entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 919
 920                 if (!has_fenced_gpu_access)
 921                         entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 922                 need_fence =
 923                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 924                         i915_gem_object_is_tiled(obj);
 925                 need_mappable = need_fence || need_reloc_mappable(vma);
 926
 927                 if (entry->flags & EXEC_OBJECT_PINNED)
 928                         list_move_tail(&vma->exec_list, &pinned_vmas);
 929                 else if (need_mappable) {
 930                         entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
 931                         list_move(&vma->exec_list, &ordered_vmas);
 932                 } else
 933                         list_move_tail(&vma->exec_list, &ordered_vmas);
 934
 935                 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
 936                 obj->base.pending_write_domain = 0;
 937         }
 938         list_splice(&ordered_vmas, vmas);
 939         list_splice(&pinned_vmas, vmas);
 940
 941         /* Attempt to pin all of the buffers into the GTT.
 942          * This is done in 3 phases:
 943          *
 944          * 1a. Unbind all objects that do not match the GTT constraints for
 945          *     the execbuffer (fenceable, mappable, alignment etc).
 946          * 1b. Increment pin count for already bound objects.
 947          * 2.  Bind new objects.
 948          * 3.  Decrement pin count.
 949          *
 950          * This avoid unnecessary unbinding of later objects in order to make
 951          * room for the earlier objects *unless* we need to defragment.
 952          */
 953         retry = 0;
 954         do {
 955                 int ret = 0;
 956
 957                 /* Unbind any ill-fitting objects or pin. */
 958                 list_for_each_entry(vma, vmas, exec_list) {
 959                         if (!drm_mm_node_allocated(&vma->node))
 960                                 continue;
 961
 962                         if (eb_vma_misplaced(vma))
 963                                 ret = i915_vma_unbind(vma);
 964                         else
 965                                 ret = i915_gem_execbuffer_reserve_vma(vma,
 966                                                                       engine,
 967                                                                       need_relocs);
 968                         if (ret)
 969                                 goto err;
 970                 }
 971
 972                 /* Bind fresh objects */
 973                 list_for_each_entry(vma, vmas, exec_list) {
 974                         if (drm_mm_node_allocated(&vma->node))
 975                                 continue;
 976
 977                         ret = i915_gem_execbuffer_reserve_vma(vma, engine,
 978                                                               need_relocs);
 979                         if (ret)
 980                                 goto err;
 981                 }
 982
 983 err:
 984                 if (ret != -ENOSPC || retry++)
 985                         return ret;
 986
 987                 /* Decrement pin count for bound objects */
 988                 list_for_each_entry(vma, vmas, exec_list)
 989                         i915_gem_execbuffer_unreserve_vma(vma);
 990
 991                 ret = i915_gem_evict_vm(vm, true);
 992                 if (ret)
 993                         return ret;
 994         } while (1);
 995 }
 996
 997 static int
 998 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 999                                   struct drm_i915_gem_execbuffer2 *args,
1000                                   struct drm_file *file,
1001                                   struct intel_engine_cs *engine,
1002                                   struct eb_vmas *eb,
1003                                   struct drm_i915_gem_exec_object2 *exec,
1004                                   struct i915_gem_context *ctx)
1005 {
1006         struct drm_i915_gem_relocation_entry *reloc;
1007         struct i915_address_space *vm;
1008         struct i915_vma *vma;
1009         bool need_relocs;
1010         int *reloc_offset;
1011         int i, total, ret;
1012         unsigned count = args->buffer_count;
1013
1014         vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
1015
1016         /* We may process another execbuffer during the unlock... */
1017         while (!list_empty(&eb->vmas)) {
1018                 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
1019                 list_del_init(&vma->exec_list);
1020                 i915_gem_execbuffer_unreserve_vma(vma);
1021                 i915_vma_put(vma);
1022         }
1023
1024         mutex_unlock(&dev->struct_mutex);
1025
1026         total = 0;
1027         for (i = 0; i < count; i++)
1028                 total += exec[i].relocation_count;
1029
1030         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
1031         reloc = drm_malloc_ab(total, sizeof(*reloc));
1032         if (reloc == NULL || reloc_offset == NULL) {
1033                 drm_free_large(reloc);
1034                 drm_free_large(reloc_offset);
1035                 mutex_lock(&dev->struct_mutex);
1036                 return -ENOMEM;
1037         }
1038
1039         total = 0;
1040         for (i = 0; i < count; i++) {
1041                 struct drm_i915_gem_relocation_entry __user *user_relocs;
1042                 u64 invalid_offset = (u64)-1;
1043                 int j;
1044
1045                 user_relocs = u64_to_user_ptr(exec[i].relocs_ptr);
1046
1047                 if (copy_from_user(reloc+total, user_relocs,
1048                                    exec[i].relocation_count * sizeof(*reloc))) {
1049                         ret = -EFAULT;
1050                         mutex_lock(&dev->struct_mutex);
1051                         goto err;
1052                 }
1053
1054                 /* As we do not update the known relocation offsets after
1055                  * relocating (due to the complexities in lock handling),
1056                  * we need to mark them as invalid now so that we force the
1057                  * relocation processing next time. Just in case the target
1058                  * object is evicted and then rebound into its old
1059                  * presumed_offset before the next execbuffer - if that
1060                  * happened we would make the mistake of assuming that the
1061                  * relocations were valid.
1062                  */
1063                 for (j = 0; j < exec[i].relocation_count; j++) {
1064                         if (__copy_to_user(&user_relocs[j].presumed_offset,
1065                                            &invalid_offset,
1066                                            sizeof(invalid_offset))) {
1067                                 ret = -EFAULT;
1068                                 mutex_lock(&dev->struct_mutex);
1069                                 goto err;
1070                         }
1071                 }
1072
1073                 reloc_offset[i] = total;
1074                 total += exec[i].relocation_count;
1075         }
1076
1077         ret = i915_mutex_lock_interruptible(dev);
1078         if (ret) {
1079                 mutex_lock(&dev->struct_mutex);
1080                 goto err;
1081         }
1082
1083         /* reacquire the objects */
1084         eb_reset(eb);
1085         ret = eb_lookup_vmas(eb, exec, args, vm, file);
1086         if (ret)
1087                 goto err;
1088
1089         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1090         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1091                                           &need_relocs);
1092         if (ret)
1093                 goto err;
1094
1095         list_for_each_entry(vma, &eb->vmas, exec_list) {
1096                 int offset = vma->exec_entry - exec;
1097                 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
1098                                                             reloc + reloc_offset[offset]);
1099                 if (ret)
1100                         goto err;
1101         }
1102
1103         /* Leave the user relocations as are, this is the painfully slow path,
1104          * and we want to avoid the complication of dropping the lock whilst
1105          * having buffers reserved in the aperture and so causing spurious
1106          * ENOSPC for random operations.
1107          */
1108
1109 err:
1110         drm_free_large(reloc);
1111         drm_free_large(reloc_offset);
1112         return ret;
1113 }
1114
1115 static unsigned int eb_other_engines(struct drm_i915_gem_request *req)
1116 {
1117         unsigned int mask;
1118
1119         mask = ~intel_engine_flag(req->engine) & I915_BO_ACTIVE_MASK;
1120         mask <<= I915_BO_ACTIVE_SHIFT;
1121
1122         return mask;
1123 }
1124
1125 static int
1126 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
1127                                 struct list_head *vmas)
1128 {
1129         const unsigned int other_rings = eb_other_engines(req);
1130         struct i915_vma *vma;
1131         int ret;
1132
1133         list_for_each_entry(vma, vmas, exec_list) {
1134                 struct drm_i915_gem_object *obj = vma->obj;
1135                 struct reservation_object *resv;
1136
1137                 if (obj->flags & other_rings) {
1138                         ret = i915_gem_request_await_object
1139                                 (req, obj, obj->base.pending_write_domain);
1140                         if (ret)
1141                                 return ret;
1142                 }
1143
1144                 resv = i915_gem_object_get_dmabuf_resv(obj);
1145                 if (resv) {
1146                         ret = i915_sw_fence_await_reservation
1147                                 (&req->submit, resv, &i915_fence_ops,
1148                                  obj->base.pending_write_domain, 10*HZ,
1149                                  GFP_KERNEL | __GFP_NOWARN);
1150                         if (ret < 0)
1151                                 return ret;
1152                 }
1153
1154                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
1155                         i915_gem_clflush_object(obj, false);
1156         }
1157
1158         /* Unconditionally flush any chipset caches (for streaming writes). */
1159         i915_gem_chipset_flush(req->engine->i915);
1160
1161         /* Unconditionally invalidate GPU caches and TLBs. */
1162         return req->engine->emit_flush(req, EMIT_INVALIDATE);
1163 }
1164
1165 static bool
1166 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1167 {
1168         if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
1169                 return false;
1170
1171         /* Kernel clipping was a DRI1 misfeature */
1172         if (exec->num_cliprects || exec->cliprects_ptr)
1173                 return false;
1174
1175         if (exec->DR4 == 0xffffffff) {
1176                 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1177                 exec->DR4 = 0;
1178         }
1179         if (exec->DR1 || exec->DR4)
1180                 return false;
1181
1182         if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1183                 return false;
1184
1185         return true;
1186 }
1187
1188 static int
1189 validate_exec_list(struct drm_device *dev,
1190                    struct drm_i915_gem_exec_object2 *exec,
1191                    int count)
1192 {
1193         unsigned relocs_total = 0;
1194         unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1195         unsigned invalid_flags;
1196         int i;
1197
1198         /* INTERNAL flags must not overlap with external ones */
1199         BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS);
1200
1201         invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1202         if (USES_FULL_PPGTT(dev))
1203                 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1204
1205         for (i = 0; i < count; i++) {
1206                 char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr);
1207                 int length; /* limited by fault_in_pages_readable() */
1208
1209                 if (exec[i].flags & invalid_flags)
1210                         return -EINVAL;
1211
1212                 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1213                  * any non-page-aligned or non-canonical addresses.
1214                  */
1215                 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1216                         if (exec[i].offset !=
1217                             gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1218                                 return -EINVAL;
1219                 }
1220
1221                 /* From drm_mm perspective address space is continuous,
1222                  * so from this point we're always using non-canonical
1223                  * form internally.
1224                  */
1225                 exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1226
1227                 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1228                         return -EINVAL;
1229
1230                 /* pad_to_size was once a reserved field, so sanitize it */
1231                 if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) {
1232                         if (offset_in_page(exec[i].pad_to_size))
1233                                 return -EINVAL;
1234                 } else {
1235                         exec[i].pad_to_size = 0;
1236                 }
1237
1238                 /* First check for malicious input causing overflow in
1239                  * the worst case where we need to allocate the entire
1240                  * relocation tree as a single array.
1241                  */
1242                 if (exec[i].relocation_count > relocs_max - relocs_total)
1243                         return -EINVAL;
1244                 relocs_total += exec[i].relocation_count;
1245
1246                 length = exec[i].relocation_count *
1247                         sizeof(struct drm_i915_gem_relocation_entry);
1248                 /*
1249                  * We must check that the entire relocation array is safe
1250                  * to read, but since we may need to update the presumed
1251                  * offsets during execution, check for full write access.
1252                  */
1253                 if (!access_ok(VERIFY_WRITE, ptr, length))
1254                         return -EFAULT;
1255
1256                 if (likely(!i915.prefault_disable)) {
1257                         if (fault_in_pages_readable(ptr, length))
1258                                 return -EFAULT;
1259                 }
1260         }
1261
1262         return 0;
1263 }
1264
1265 static struct i915_gem_context *
1266 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1267                           struct intel_engine_cs *engine, const u32 ctx_id)
1268 {
1269         struct i915_gem_context *ctx;
1270         struct i915_ctx_hang_stats *hs;
1271
1272         ctx = i915_gem_context_lookup(file->driver_priv, ctx_id);
1273         if (IS_ERR(ctx))
1274                 return ctx;
1275
1276         hs = &ctx->hang_stats;
1277         if (hs->banned) {
1278                 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1279                 return ERR_PTR(-EIO);
1280         }
1281
1282         return ctx;
1283 }
1284
1285 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
1286 {
1287         return !(obj->cache_level == I915_CACHE_NONE ||
1288                  obj->cache_level == I915_CACHE_WT);
1289 }
1290
1291 void i915_vma_move_to_active(struct i915_vma *vma,
1292                              struct drm_i915_gem_request *req,
1293                              unsigned int flags)
1294 {
1295         struct drm_i915_gem_object *obj = vma->obj;
1296         const unsigned int idx = req->engine->id;
1297
1298         GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1299
1300         obj->dirty = 1; /* be paranoid  */
1301
1302         /* Add a reference if we're newly entering the active list.
1303          * The order in which we add operations to the retirement queue is
1304          * vital here: mark_active adds to the start of the callback list,
1305          * such that subsequent callbacks are called first. Therefore we
1306          * add the active reference first and queue for it to be dropped
1307          * *last*.
1308          */
1309         if (!i915_gem_object_is_active(obj))
1310                 i915_gem_object_get(obj);
1311         i915_gem_object_set_active(obj, idx);
1312         i915_gem_active_set(&obj->last_read[idx], req);
1313
1314         if (flags & EXEC_OBJECT_WRITE) {
1315                 i915_gem_active_set(&obj->last_write, req);
1316
1317                 intel_fb_obj_invalidate(obj, ORIGIN_CS);
1318
1319                 /* update for the implicit flush after a batch */
1320                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1321                 if (!obj->cache_dirty && gpu_write_needs_clflush(obj))
1322                         obj->cache_dirty = true;
1323         }
1324
1325         if (flags & EXEC_OBJECT_NEEDS_FENCE)
1326                 i915_gem_active_set(&vma->last_fence, req);
1327
1328         i915_vma_set_active(vma, idx);
1329         i915_gem_active_set(&vma->last_read[idx], req);
1330         list_move_tail(&vma->vm_link, &vma->vm->active_list);
1331 }
1332
1333 static void eb_export_fence(struct drm_i915_gem_object *obj,
1334                             struct drm_i915_gem_request *req,
1335                             unsigned int flags)
1336 {
1337         struct reservation_object *resv;
1338
1339         resv = i915_gem_object_get_dmabuf_resv(obj);
1340         if (!resv)
1341                 return;
1342
1343         /* Ignore errors from failing to allocate the new fence, we can't
1344          * handle an error right now. Worst case should be missed
1345          * synchronisation leading to rendering corruption.
1346          */
1347         ww_mutex_lock(&resv->lock, NULL);
1348         if (flags & EXEC_OBJECT_WRITE)
1349                 reservation_object_add_excl_fence(resv, &req->fence);
1350         else if (reservation_object_reserve_shared(resv) == 0)
1351                 reservation_object_add_shared_fence(resv, &req->fence);
1352         ww_mutex_unlock(&resv->lock);
1353 }
1354
1355 static void
1356 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1357                                    struct drm_i915_gem_request *req)
1358 {
1359         struct i915_vma *vma;
1360
1361         list_for_each_entry(vma, vmas, exec_list) {
1362                 struct drm_i915_gem_object *obj = vma->obj;
1363                 u32 old_read = obj->base.read_domains;
1364                 u32 old_write = obj->base.write_domain;
1365
1366                 obj->base.write_domain = obj->base.pending_write_domain;
1367                 if (obj->base.write_domain)
1368                         vma->exec_entry->flags |= EXEC_OBJECT_WRITE;
1369                 else
1370                         obj->base.pending_read_domains |= obj->base.read_domains;
1371                 obj->base.read_domains = obj->base.pending_read_domains;
1372
1373                 i915_vma_move_to_active(vma, req, vma->exec_entry->flags);
1374                 eb_export_fence(obj, req, vma->exec_entry->flags);
1375                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1376         }
1377 }
1378
1379 static int
1380 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1381 {
1382         struct intel_ring *ring = req->ring;
1383         int ret, i;
1384
1385         if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1386                 DRM_DEBUG("sol reset is gen7/rcs only\n");
1387                 return -EINVAL;
1388         }
1389
1390         ret = intel_ring_begin(req, 4 * 3);
1391         if (ret)
1392                 return ret;
1393
1394         for (i = 0; i < 4; i++) {
1395                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1396                 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1397                 intel_ring_emit(ring, 0);
1398         }
1399
1400         intel_ring_advance(ring);
1401
1402         return 0;
1403 }
1404
1405 static struct i915_vma*
1406 shadow_batch_pin(struct drm_i915_gem_object *obj, struct i915_address_space *vm)
1407 {
1408         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
1409         u64 flags;
1410
1411         /*
1412          * PPGTT backed shadow buffers must be mapped RO, to prevent
1413          * post-scan tampering
1414          */
1415         if (CMDPARSER_USES_GGTT(dev_priv)) {
1416                 flags = PIN_GLOBAL;
1417                 vm = &dev_priv->ggtt.base;
1418         } else if (vm->has_read_only) {
1419                 flags = PIN_USER;
1420                 i915_gem_object_set_readonly(obj);
1421         } else {
1422                 DRM_DEBUG("Cannot prevent post-scan tampering without RO capable vm\n");
1423                 return ERR_PTR(-EINVAL);
1424         }
1425
1426         return i915_gem_object_pin(obj, vm, NULL, 0, 0, flags);
1427 }
1428
1429 static struct i915_vma *
1430 i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1431                           struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1432                           struct i915_execbuffer_params *params,
1433                           struct eb_vmas *eb,
1434                           struct i915_address_space *vm)
1435 {
1436         struct drm_i915_gem_object *batch_obj = params->batch->obj;
1437         struct drm_i915_gem_object *shadow_batch_obj;
1438         struct i915_vma *vma;
1439         u64 batch_start;
1440         u32 batch_start_offset = params->args_batch_start_offset;
1441         u32 batch_len = params->args_batch_len;
1442         u64 shadow_batch_start;
1443         int ret;
1444
1445
1446         shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1447                                                    PAGE_ALIGN(batch_len));
1448         if (IS_ERR(shadow_batch_obj))
1449                 return ERR_CAST(shadow_batch_obj);
1450
1451         vma = shadow_batch_pin(shadow_batch_obj, vm);
1452         if (IS_ERR(vma))
1453                 goto out;
1454
1455         batch_start = gen8_canonical_addr(params->batch->node.start) +
1456                       batch_start_offset;
1457         shadow_batch_start = gen8_canonical_addr(vma->node.start);
1458
1459         ret = intel_engine_cmd_parser(params->ctx,
1460                                       engine,
1461                                       batch_obj,
1462                                       batch_start,
1463                                       batch_start_offset,
1464                                       batch_len,
1465                                       shadow_batch_obj,
1466                                       shadow_batch_start);
1467         if (ret) {
1468                 i915_vma_unpin(vma);
1469
1470                 /*
1471                  * Unsafe GGTT-backed buffers can still be submitted safely
1472                  * as non-secure.
1473                  * For PPGTT backing however, we have no choice but to forcibly
1474                  * reject unsafe buffers
1475                  */
1476                 if (CMDPARSER_USES_GGTT(eb->i915) && (ret == -EACCES))
1477                         /* Execute original buffer non-secure */
1478                         vma = NULL;
1479                 else
1480                         vma = ERR_PTR(ret);
1481
1482                 goto out;
1483         }
1484
1485         memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1486
1487         vma->exec_entry = shadow_exec_entry;
1488         vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1489         i915_gem_object_get(shadow_batch_obj);
1490         list_add_tail(&vma->exec_list, &eb->vmas);
1491
1492 out:
1493         i915_gem_object_unpin_pages(shadow_batch_obj);
1494         return vma;
1495 }
1496
1497 static int
1498 execbuf_submit(struct i915_execbuffer_params *params,
1499                struct drm_i915_gem_execbuffer2 *args,
1500                struct list_head *vmas)
1501 {
1502         u64 exec_start, exec_len;
1503         int ret;
1504
1505         ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1506         if (ret)
1507                 return ret;
1508
1509         ret = i915_switch_context(params->request);
1510         if (ret)
1511                 return ret;
1512
1513         if (args->flags & I915_EXEC_CONSTANTS_MASK) {
1514                 DRM_DEBUG("I915_EXEC_CONSTANTS_* unsupported\n");
1515                 return -EINVAL;
1516         }
1517
1518         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1519                 ret = i915_reset_gen7_sol_offsets(params->request);
1520                 if (ret)
1521                         return ret;
1522         }
1523
1524         exec_len   = params->args_batch_len;
1525         exec_start = params->batch->node.start +
1526                      params->args_batch_start_offset;
1527
1528         ret = params->engine->emit_bb_start(params->request,
1529                                             exec_start, exec_len,
1530                                             params->dispatch_flags);
1531         if (ret)
1532                 return ret;
1533
1534         trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1535
1536         i915_gem_execbuffer_move_to_active(vmas, params->request);
1537
1538         return 0;
1539 }
1540
1541 /**
1542  * Find one BSD ring to dispatch the corresponding BSD command.
1543  * The engine index is returned.
1544  */
1545 static unsigned int
1546 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1547                          struct drm_file *file)
1548 {
1549         struct drm_i915_file_private *file_priv = file->driver_priv;
1550
1551         /* Check whether the file_priv has already selected one ring. */
1552         if ((int)file_priv->bsd_engine < 0)
1553                 file_priv->bsd_engine = atomic_fetch_xor(1,
1554                          &dev_priv->mm.bsd_engine_dispatch_index);
1555
1556         return file_priv->bsd_engine;
1557 }
1558
1559 #define I915_USER_RINGS (4)
1560
1561 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1562         [I915_EXEC_DEFAULT]     = RCS,
1563         [I915_EXEC_RENDER]      = RCS,
1564         [I915_EXEC_BLT]         = BCS,
1565         [I915_EXEC_BSD]         = VCS,
1566         [I915_EXEC_VEBOX]       = VECS
1567 };
1568
1569 static struct intel_engine_cs *
1570 eb_select_engine(struct drm_i915_private *dev_priv,
1571                  struct drm_file *file,
1572                  struct drm_i915_gem_execbuffer2 *args)
1573 {
1574         unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1575         struct intel_engine_cs *engine;
1576
1577         if (user_ring_id > I915_USER_RINGS) {
1578                 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1579                 return NULL;
1580         }
1581
1582         if ((user_ring_id != I915_EXEC_BSD) &&
1583             ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1584                 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1585                           "bsd dispatch flags: %d\n", (int)(args->flags));
1586                 return NULL;
1587         }
1588
1589         if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1590                 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1591
1592                 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1593                         bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
1594                 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1595                            bsd_idx <= I915_EXEC_BSD_RING2) {
1596                         bsd_idx >>= I915_EXEC_BSD_SHIFT;
1597                         bsd_idx--;
1598                 } else {
1599                         DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1600                                   bsd_idx);
1601                         return NULL;
1602                 }
1603
1604                 engine = &dev_priv->engine[_VCS(bsd_idx)];
1605         } else {
1606                 engine = &dev_priv->engine[user_ring_map[user_ring_id]];
1607         }
1608
1609         if (!intel_engine_initialized(engine)) {
1610                 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1611                 return NULL;
1612         }
1613
1614         return engine;
1615 }
1616
1617 static int
1618 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1619                        struct drm_file *file,
1620                        struct drm_i915_gem_execbuffer2 *args,
1621                        struct drm_i915_gem_exec_object2 *exec)
1622 {
1623         struct drm_i915_private *dev_priv = to_i915(dev);
1624         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1625         struct eb_vmas *eb;
1626         struct drm_i915_gem_exec_object2 shadow_exec_entry;
1627         struct intel_engine_cs *engine;
1628         struct i915_gem_context *ctx;
1629         struct i915_address_space *vm;
1630         struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1631         struct i915_execbuffer_params *params = &params_master;
1632         const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1633         u32 dispatch_flags;
1634         int ret;
1635         bool need_relocs;
1636
1637         if (!i915_gem_check_execbuffer(args))
1638                 return -EINVAL;
1639
1640         ret = validate_exec_list(dev, exec, args->buffer_count);
1641         if (ret)
1642                 return ret;
1643
1644         dispatch_flags = 0;
1645         if (args->flags & I915_EXEC_SECURE) {
1646                 if (INTEL_GEN(dev_priv) >= 11)
1647                         return -ENODEV;
1648
1649                 /* Return -EPERM to trigger fallback code on old binaries. */
1650                 if (!HAS_SECURE_BATCHES(dev_priv))
1651                         return -EPERM;
1652
1653                 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
1654                         return -EPERM;
1655
1656                 dispatch_flags |= I915_DISPATCH_SECURE;
1657         }
1658         if (args->flags & I915_EXEC_IS_PINNED)
1659                 dispatch_flags |= I915_DISPATCH_PINNED;
1660
1661         engine = eb_select_engine(dev_priv, file, args);
1662         if (!engine)
1663                 return -EINVAL;
1664
1665         if (args->buffer_count < 1) {
1666                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1667                 return -EINVAL;
1668         }
1669
1670         if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1671                 if (!HAS_RESOURCE_STREAMER(dev)) {
1672                         DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1673                         return -EINVAL;
1674                 }
1675                 if (engine->id != RCS) {
1676                         DRM_DEBUG("RS is not available on %s\n",
1677                                  engine->name);
1678                         return -EINVAL;
1679                 }
1680
1681                 dispatch_flags |= I915_DISPATCH_RS;
1682         }
1683
1684         /* Take a local wakeref for preparing to dispatch the execbuf as
1685          * we expect to access the hardware fairly frequently in the
1686          * process. Upon first dispatch, we acquire another prolonged
1687          * wakeref that we hold until the GPU has been idle for at least
1688          * 100ms.
1689          */
1690         intel_runtime_pm_get(dev_priv);
1691
1692         ret = i915_mutex_lock_interruptible(dev);
1693         if (ret)
1694                 goto pre_mutex_err;
1695
1696         ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1697         if (IS_ERR(ctx)) {
1698                 mutex_unlock(&dev->struct_mutex);
1699                 ret = PTR_ERR(ctx);
1700                 goto pre_mutex_err;
1701         }
1702
1703         i915_gem_context_get(ctx);
1704
1705         if (ctx->ppgtt)
1706                 vm = &ctx->ppgtt->base;
1707         else
1708                 vm = &ggtt->base;
1709
1710         memset(&params_master, 0x00, sizeof(params_master));
1711
1712         eb = eb_create(dev_priv, args);
1713         if (eb == NULL) {
1714                 i915_gem_context_put(ctx);
1715                 mutex_unlock(&dev->struct_mutex);
1716                 ret = -ENOMEM;
1717                 goto pre_mutex_err;
1718         }
1719
1720         /* Look up object handles */
1721         ret = eb_lookup_vmas(eb, exec, args, vm, file);
1722         if (ret)
1723                 goto err;
1724
1725         /* take note of the batch buffer before we might reorder the lists */
1726         params->batch = eb_get_batch(eb);
1727
1728         /* Move the objects en-masse into the GTT, evicting if necessary. */
1729         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1730         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1731                                           &need_relocs);
1732         if (ret)
1733                 goto err;
1734
1735         /* The objects are in their final locations, apply the relocations. */
1736         if (need_relocs)
1737                 ret = i915_gem_execbuffer_relocate(eb);
1738         if (ret) {
1739                 if (ret == -EFAULT) {
1740                         ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1741                                                                 engine,
1742                                                                 eb, exec, ctx);
1743                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1744                 }
1745                 if (ret)
1746                         goto err;
1747         }
1748
1749         /* Set the pending read domains for the batch buffer to COMMAND */
1750         if (params->batch->obj->base.pending_write_domain) {
1751                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1752                 ret = -EINVAL;
1753                 goto err;
1754         }
1755         if (args->batch_start_offset > params->batch->size ||
1756             args->batch_len > params->batch->size - args->batch_start_offset) {
1757                 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
1758                 ret = -EINVAL;
1759                 goto err;
1760         }
1761
1762         params->ctx = ctx;
1763         params->args_batch_start_offset = args->batch_start_offset;
1764         params->args_batch_len = args->batch_len;
1765         if (args->batch_len == 0)
1766                 params->args_batch_len = params->batch->size - params->args_batch_start_offset;
1767
1768         if (intel_engine_requires_cmd_parser(engine) ||
1769             (intel_engine_using_cmd_parser(engine) && args->batch_len)) {
1770                 struct i915_vma *vma;
1771
1772                 vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry,
1773                                                 params, eb, vm);
1774                 if (IS_ERR(vma)) {
1775                         ret = PTR_ERR(vma);
1776                         goto err;
1777                 }
1778
1779                 if (vma) {
1780                         if (CMDPARSER_USES_GGTT(dev_priv))
1781                                 dispatch_flags |= I915_DISPATCH_SECURE;
1782                         params->args_batch_start_offset = 0;
1783                         params->batch = vma;
1784                 }
1785         }
1786
1787         params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1788
1789         /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1790          * batch" bit. Hence we need to pin secure batches into the global gtt.
1791          * hsw should have this fixed, but bdw mucks it up again. */
1792         if (dispatch_flags & I915_DISPATCH_SECURE) {
1793                 struct drm_i915_gem_object *obj = params->batch->obj;
1794                 struct i915_vma *vma;
1795
1796                 /*
1797                  * So on first glance it looks freaky that we pin the batch here
1798                  * outside of the reservation loop. But:
1799                  * - The batch is already pinned into the relevant ppgtt, so we
1800                  *   already have the backing storage fully allocated.
1801                  * - No other BO uses the global gtt (well contexts, but meh),
1802                  *   so we don't really have issues with multiple objects not
1803                  *   fitting due to fragmentation.
1804                  * So this is actually safe.
1805                  */
1806                 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
1807                 if (IS_ERR(vma)) {
1808                         ret = PTR_ERR(vma);
1809                         goto err;
1810                 }
1811
1812                 params->batch = vma;
1813         }
1814
1815         /* Allocate a request for this batch buffer nice and early. */
1816         params->request = i915_gem_request_alloc(engine, ctx);
1817         if (IS_ERR(params->request)) {
1818                 ret = PTR_ERR(params->request);
1819                 goto err_batch_unpin;
1820         }
1821
1822         /* Whilst this request exists, batch_obj will be on the
1823          * active_list, and so will hold the active reference. Only when this
1824          * request is retired will the the batch_obj be moved onto the
1825          * inactive_list and lose its active reference. Hence we do not need
1826          * to explicitly hold another reference here.
1827          */
1828         params->request->batch = params->batch;
1829
1830         ret = i915_gem_request_add_to_client(params->request, file);
1831         if (ret)
1832                 goto err_request;
1833
1834         /*
1835          * Save assorted stuff away to pass through to *_submission().
1836          * NB: This data should be 'persistent' and not local as it will
1837          * kept around beyond the duration of the IOCTL once the GPU
1838          * scheduler arrives.
1839          */
1840         params->dev                     = dev;
1841         params->file                    = file;
1842         params->engine                    = engine;
1843         params->dispatch_flags          = dispatch_flags;
1844
1845         ret = execbuf_submit(params, args, &eb->vmas);
1846 err_request:
1847         __i915_add_request(params->request, ret == 0);
1848
1849 err_batch_unpin:
1850         /*
1851          * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1852          * batch vma for correctness. For less ugly and less fragility this
1853          * needs to be adjusted to also track the ggtt batch vma properly as
1854          * active.
1855          */
1856         if (dispatch_flags & I915_DISPATCH_SECURE)
1857                 i915_vma_unpin(params->batch);
1858 err:
1859         /* the request owns the ref now */
1860         i915_gem_context_put(ctx);
1861         eb_destroy(eb);
1862
1863         mutex_unlock(&dev->struct_mutex);
1864
1865 pre_mutex_err:
1866         /* intel_gpu_busy should also get a ref, so it will free when the device
1867          * is really idle. */
1868         intel_runtime_pm_put(dev_priv);
1869         return ret;
1870 }
1871
1872 /*
1873  * Legacy execbuffer just creates an exec2 list from the original exec object
1874  * list array and passes it to the real function.
1875  */
1876 int
1877 i915_gem_execbuffer(struct drm_device *dev, void *data,
1878                     struct drm_file *file)
1879 {
1880         struct drm_i915_gem_execbuffer *args = data;
1881         struct drm_i915_gem_execbuffer2 exec2;
1882         struct drm_i915_gem_exec_object *exec_list = NULL;
1883         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1884         int ret, i;
1885
1886         if (args->buffer_count < 1) {
1887                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1888                 return -EINVAL;
1889         }
1890
1891         /* Copy in the exec list from userland */
1892         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1893         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1894         if (exec_list == NULL || exec2_list == NULL) {
1895                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1896                           args->buffer_count);
1897                 drm_free_large(exec_list);
1898                 drm_free_large(exec2_list);
1899                 return -ENOMEM;
1900         }
1901         ret = copy_from_user(exec_list,
1902                              u64_to_user_ptr(args->buffers_ptr),
1903                              sizeof(*exec_list) * args->buffer_count);
1904         if (ret != 0) {
1905                 DRM_DEBUG("copy %d exec entries failed %d\n",
1906                           args->buffer_count, ret);
1907                 drm_free_large(exec_list);
1908                 drm_free_large(exec2_list);
1909                 return -EFAULT;
1910         }
1911
1912         for (i = 0; i < args->buffer_count; i++) {
1913                 exec2_list[i].handle = exec_list[i].handle;
1914                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1915                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1916                 exec2_list[i].alignment = exec_list[i].alignment;
1917                 exec2_list[i].offset = exec_list[i].offset;
1918                 if (INTEL_INFO(dev)->gen < 4)
1919                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1920                 else
1921                         exec2_list[i].flags = 0;
1922         }
1923
1924         exec2.buffers_ptr = args->buffers_ptr;
1925         exec2.buffer_count = args->buffer_count;
1926         exec2.batch_start_offset = args->batch_start_offset;
1927         exec2.batch_len = args->batch_len;
1928         exec2.DR1 = args->DR1;
1929         exec2.DR4 = args->DR4;
1930         exec2.num_cliprects = args->num_cliprects;
1931         exec2.cliprects_ptr = args->cliprects_ptr;
1932         exec2.flags = I915_EXEC_RENDER;
1933         i915_execbuffer2_set_context_id(exec2, 0);
1934
1935         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1936         if (!ret) {
1937                 struct drm_i915_gem_exec_object __user *user_exec_list =
1938                         u64_to_user_ptr(args->buffers_ptr);
1939
1940                 /* Copy the new buffer offsets back to the user's exec list. */
1941                 for (i = 0; i < args->buffer_count; i++) {
1942                         exec2_list[i].offset =
1943                                 gen8_canonical_addr(exec2_list[i].offset);
1944                         ret = __copy_to_user(&user_exec_list[i].offset,
1945                                              &exec2_list[i].offset,
1946                                              sizeof(user_exec_list[i].offset));
1947                         if (ret) {
1948                                 ret = -EFAULT;
1949                                 DRM_DEBUG("failed to copy %d exec entries "
1950                                           "back to user (%d)\n",
1951                                           args->buffer_count, ret);
1952                                 break;
1953                         }
1954                 }
1955         }
1956
1957         drm_free_large(exec_list);
1958         drm_free_large(exec2_list);
1959         return ret;
1960 }
1961
1962 int
1963 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1964                      struct drm_file *file)
1965 {
1966         struct drm_i915_gem_execbuffer2 *args = data;
1967         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1968         int ret;
1969
1970         if (args->buffer_count < 1 ||
1971             args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1972                 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1973                 return -EINVAL;
1974         }
1975
1976         if (args->rsvd2 != 0) {
1977                 DRM_DEBUG("dirty rvsd2 field\n");
1978                 return -EINVAL;
1979         }
1980
1981         exec2_list = drm_malloc_gfp(args->buffer_count,
1982                                     sizeof(*exec2_list),
1983                                     GFP_TEMPORARY);
1984         if (exec2_list == NULL) {
1985                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1986                           args->buffer_count);
1987                 return -ENOMEM;
1988         }
1989         ret = copy_from_user(exec2_list,
1990                              u64_to_user_ptr(args->buffers_ptr),
1991                              sizeof(*exec2_list) * args->buffer_count);
1992         if (ret != 0) {
1993                 DRM_DEBUG("copy %d exec entries failed %d\n",
1994                           args->buffer_count, ret);
1995                 drm_free_large(exec2_list);
1996                 return -EFAULT;
1997         }
1998
1999         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
2000         if (!ret) {
2001                 /* Copy the new buffer offsets back to the user's exec list. */
2002                 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2003                                    u64_to_user_ptr(args->buffers_ptr);
2004                 int i;
2005
2006                 for (i = 0; i < args->buffer_count; i++) {
2007                         exec2_list[i].offset =
2008                                 gen8_canonical_addr(exec2_list[i].offset);
2009                         ret = __copy_to_user(&user_exec_list[i].offset,
2010                                              &exec2_list[i].offset,
2011                                              sizeof(user_exec_list[i].offset));
2012                         if (ret) {
2013                                 ret = -EFAULT;
2014                                 DRM_DEBUG("failed to copy %d exec entries "
2015                                           "back to user\n",
2016                                           args->buffer_count);
2017                                 break;
2018                         }
2019                 }
2020         }
2021
2022         drm_free_large(exec2_list);
2023         return ret;
2024 }