drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include <linux/stop_machine.h>
  32 #include <linux/zlib.h>
  33 #include "i915_drv.h"
  34
  35 static const char *engine_str(int engine)
  36 {
  37         switch (engine) {
  38         case RCS: return "render";
  39         case VCS: return "bsd";
  40         case BCS: return "blt";
  41         case VECS: return "vebox";
  42         case VCS2: return "bsd2";
  43         default: return "";
  44         }
  45 }
  46
  47 static const char *tiling_flag(int tiling)
  48 {
  49         switch (tiling) {
  50         default:
  51         case I915_TILING_NONE: return "";
  52         case I915_TILING_X: return " X";
  53         case I915_TILING_Y: return " Y";
  54         }
  55 }
  56
  57 static const char *dirty_flag(int dirty)
  58 {
  59         return dirty ? " dirty" : "";
  60 }
  61
  62 static const char *purgeable_flag(int purgeable)
  63 {
  64         return purgeable ? " purgeable" : "";
  65 }
  66
  67 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  68 {
  69
  70         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  71                 e->err = -ENOSPC;
  72                 return false;
  73         }
  74
  75         if (e->bytes == e->size - 1 || e->err)
  76                 return false;
  77
  78         return true;
  79 }
  80
  81 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  82                               unsigned len)
  83 {
  84         if (e->pos + len <= e->start) {
  85                 e->pos += len;
  86                 return false;
  87         }
  88
  89         /* First vsnprintf needs to fit in its entirety for memmove */
  90         if (len >= e->size) {
  91                 e->err = -EIO;
  92                 return false;
  93         }
  94
  95         return true;
  96 }
  97
  98 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
  99                                  unsigned len)
 100 {
 101         /* If this is first printf in this window, adjust it so that
 102          * start position matches start of the buffer
 103          */
 104
 105         if (e->pos < e->start) {
 106                 const size_t off = e->start - e->pos;
 107
 108                 /* Should not happen but be paranoid */
 109                 if (off > len || e->bytes) {
 110                         e->err = -EIO;
 111                         return;
 112                 }
 113
 114                 memmove(e->buf, e->buf + off, len - off);
 115                 e->bytes = len - off;
 116                 e->pos = e->start;
 117                 return;
 118         }
 119
 120         e->bytes += len;
 121         e->pos += len;
 122 }
 123
 124 __printf(2, 0)
 125 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 126                                const char *f, va_list args)
 127 {
 128         unsigned len;
 129
 130         if (!__i915_error_ok(e))
 131                 return;
 132
 133         /* Seek the first printf which is hits start position */
 134         if (e->pos < e->start) {
 135                 va_list tmp;
 136
 137                 va_copy(tmp, args);
 138                 len = vsnprintf(NULL, 0, f, tmp);
 139                 va_end(tmp);
 140
 141                 if (!__i915_error_seek(e, len))
 142                         return;
 143         }
 144
 145         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 146         if (len >= e->size - e->bytes)
 147                 len = e->size - e->bytes - 1;
 148
 149         __i915_error_advance(e, len);
 150 }
 151
 152 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 153                             const char *str)
 154 {
 155         unsigned len;
 156
 157         if (!__i915_error_ok(e))
 158                 return;
 159
 160         len = strlen(str);
 161
 162         /* Seek the first printf which is hits start position */
 163         if (e->pos < e->start) {
 164                 if (!__i915_error_seek(e, len))
 165                         return;
 166         }
 167
 168         if (len >= e->size - e->bytes)
 169                 len = e->size - e->bytes - 1;
 170         memcpy(e->buf + e->bytes, str, len);
 171
 172         __i915_error_advance(e, len);
 173 }
 174
 175 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 176 #define err_puts(e, s) i915_error_puts(e, s)
 177
 178 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 179
 180 struct compress {
 181         struct z_stream_s zstream;
 182         void *tmp;
 183 };
 184
 185 static bool compress_init(struct compress *c)
 186 {
 187         struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
 188
 189         zstream->workspace =
 190                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 191                         GFP_ATOMIC | __GFP_NOWARN);
 192         if (!zstream->workspace)
 193                 return false;
 194
 195         if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
 196                 kfree(zstream->workspace);
 197                 return false;
 198         }
 199
 200         c->tmp = NULL;
 201         if (i915_has_memcpy_from_wc())
 202                 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 203
 204         return true;
 205 }
 206
 207 static int compress_page(struct compress *c,
 208                          void *src,
 209                          struct drm_i915_error_object *dst)
 210 {
 211         struct z_stream_s *zstream = &c->zstream;
 212
 213         zstream->next_in = src;
 214         if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 215                 zstream->next_in = c->tmp;
 216         zstream->avail_in = PAGE_SIZE;
 217
 218         do {
 219                 if (zstream->avail_out == 0) {
 220                         unsigned long page;
 221
 222                         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 223                         if (!page)
 224                                 return -ENOMEM;
 225
 226                         dst->pages[dst->page_count++] = (void *)page;
 227
 228                         zstream->next_out = (void *)page;
 229                         zstream->avail_out = PAGE_SIZE;
 230                 }
 231
 232                 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
 233                         return -EIO;
 234
 235                 cond_resched();
 236         } while (zstream->avail_in);
 237
 238         /* Fallback to uncompressed if we increase size? */
 239         if (0 && zstream->total_out > zstream->total_in)
 240                 return -E2BIG;
 241
 242         return 0;
 243 }
 244
 245 static void compress_fini(struct compress *c,
 246                           struct drm_i915_error_object *dst)
 247 {
 248         struct z_stream_s *zstream = &c->zstream;
 249
 250         if (dst) {
 251                 zlib_deflate(zstream, Z_FINISH);
 252                 dst->unused = zstream->avail_out;
 253         }
 254
 255         zlib_deflateEnd(zstream);
 256         kfree(zstream->workspace);
 257
 258         if (c->tmp)
 259                 free_page((unsigned long)c->tmp);
 260 }
 261
 262 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 263 {
 264         err_puts(m, ":");
 265 }
 266
 267 #else
 268
 269 struct compress {
 270 };
 271
 272 static bool compress_init(struct compress *c)
 273 {
 274         return true;
 275 }
 276
 277 static int compress_page(struct compress *c,
 278                          void *src,
 279                          struct drm_i915_error_object *dst)
 280 {
 281         unsigned long page;
 282         void *ptr;
 283
 284         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 285         if (!page)
 286                 return -ENOMEM;
 287
 288         ptr = (void *)page;
 289         if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
 290                 memcpy(ptr, src, PAGE_SIZE);
 291         dst->pages[dst->page_count++] = ptr;
 292         cond_resched();
 293
 294         return 0;
 295 }
 296
 297 static void compress_fini(struct compress *c,
 298                           struct drm_i915_error_object *dst)
 299 {
 300 }
 301
 302 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 303 {
 304         err_puts(m, "~");
 305 }
 306
 307 #endif
 308
 309 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 310                                 const char *name,
 311                                 struct drm_i915_error_buffer *err,
 312                                 int count)
 313 {
 314         int i;
 315
 316         err_printf(m, "%s [%d]:\n", name, count);
 317
 318         while (count--) {
 319                 err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
 320                            upper_32_bits(err->gtt_offset),
 321                            lower_32_bits(err->gtt_offset),
 322                            err->size,
 323                            err->read_domains,
 324                            err->write_domain);
 325                 for (i = 0; i < I915_NUM_ENGINES; i++)
 326                         err_printf(m, "%02x ", err->rseqno[i]);
 327
 328                 err_printf(m, "] %02x", err->wseqno);
 329                 err_puts(m, tiling_flag(err->tiling));
 330                 err_puts(m, dirty_flag(err->dirty));
 331                 err_puts(m, purgeable_flag(err->purgeable));
 332                 err_puts(m, err->userptr ? " userptr" : "");
 333                 err_puts(m, err->engine != -1 ? " " : "");
 334                 err_puts(m, engine_str(err->engine));
 335                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 336
 337                 if (err->name)
 338                         err_printf(m, " (name: %d)", err->name);
 339                 if (err->fence_reg != I915_FENCE_REG_NONE)
 340                         err_printf(m, " (fence: %d)", err->fence_reg);
 341
 342                 err_puts(m, "\n");
 343                 err++;
 344         }
 345 }
 346
 347 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 348                                  const struct drm_i915_error_engine *ee)
 349 {
 350         int slice;
 351         int subslice;
 352
 353         err_printf(m, "  INSTDONE: 0x%08x\n",
 354                    ee->instdone.instdone);
 355
 356         if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
 357                 return;
 358
 359         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 360                    ee->instdone.slice_common);
 361
 362         if (INTEL_GEN(m->i915) <= 6)
 363                 return;
 364
 365         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 366                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 367                            slice, subslice,
 368                            ee->instdone.sampler[slice][subslice]);
 369
 370         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 371                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 372                            slice, subslice,
 373                            ee->instdone.row[slice][subslice]);
 374 }
 375
 376 static void error_print_request(struct drm_i915_error_state_buf *m,
 377                                 const char *prefix,
 378                                 const struct drm_i915_error_request *erq)
 379 {
 380         if (!erq->seqno)
 381                 return;
 382
 383         err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n",
 384                    prefix, erq->pid, erq->ban_score,
 385                    erq->context, erq->seqno,
 386                    jiffies_to_msecs(jiffies - erq->jiffies),
 387                    erq->head, erq->tail);
 388 }
 389
 390 static void error_print_context(struct drm_i915_error_state_buf *m,
 391                                 const char *header,
 392                                 const struct drm_i915_error_context *ctx)
 393 {
 394         err_printf(m, "%s%s[%d] user_handle %d hw_id %d, ban score %d guilty %d active %d\n",
 395                    header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
 396                    ctx->ban_score, ctx->guilty, ctx->active);
 397 }
 398
 399 static void error_print_engine(struct drm_i915_error_state_buf *m,
 400                                const struct drm_i915_error_engine *ee)
 401 {
 402         err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
 403         err_printf(m, "  START: 0x%08x\n", ee->start);
 404         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 405         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 406                    ee->tail, ee->rq_post, ee->rq_tail);
 407         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 408         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 409         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 410         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 411                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 412         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 413         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 414
 415         error_print_instdone(m, ee);
 416
 417         if (ee->batchbuffer) {
 418                 u64 start = ee->batchbuffer->gtt_offset;
 419                 u64 end = start + ee->batchbuffer->gtt_size;
 420
 421                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 422                            upper_32_bits(start), lower_32_bits(start),
 423                            upper_32_bits(end), lower_32_bits(end));
 424         }
 425         if (INTEL_GEN(m->i915) >= 4) {
 426                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 427                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 428                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 429                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 430         }
 431         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 432         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 433                    lower_32_bits(ee->faddr));
 434         if (INTEL_GEN(m->i915) >= 6) {
 435                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 436                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 437                 err_printf(m, "  SYNC_0: 0x%08x\n",
 438                            ee->semaphore_mboxes[0]);
 439                 err_printf(m, "  SYNC_1: 0x%08x\n",
 440                            ee->semaphore_mboxes[1]);
 441                 if (HAS_VEBOX(m->i915))
 442                         err_printf(m, "  SYNC_2: 0x%08x\n",
 443                                    ee->semaphore_mboxes[2]);
 444         }
 445         if (USES_PPGTT(m->i915)) {
 446                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 447
 448                 if (INTEL_GEN(m->i915) >= 8) {
 449                         int i;
 450                         for (i = 0; i < 4; i++)
 451                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 452                                            i, ee->vm_info.pdp[i]);
 453                 } else {
 454                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 455                                    ee->vm_info.pp_dir_base);
 456                 }
 457         }
 458         err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
 459         err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
 460         err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
 461         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
 462         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
 463         err_printf(m, "  hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
 464         err_printf(m, "  hangcheck action: %s\n",
 465                    hangcheck_action_to_str(ee->hangcheck_action));
 466         err_printf(m, "  hangcheck action timestamp: %lu, %u ms ago\n",
 467                    ee->hangcheck_timestamp,
 468                    jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
 469         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 470
 471         error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
 472         error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
 473         error_print_context(m, "  Active context: ", &ee->context);
 474 }
 475
 476 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 477 {
 478         va_list args;
 479
 480         va_start(args, f);
 481         i915_error_vprintf(e, f, args);
 482         va_end(args);
 483 }
 484
 485 static int
 486 ascii85_encode_len(int len)
 487 {
 488         return DIV_ROUND_UP(len, 4);
 489 }
 490
 491 static bool
 492 ascii85_encode(u32 in, char *out)
 493 {
 494         int i;
 495
 496         if (in == 0)
 497                 return false;
 498
 499         out[5] = '\0';
 500         for (i = 5; i--; ) {
 501                 out[i] = '!' + in % 85;
 502                 in /= 85;
 503         }
 504
 505         return true;
 506 }
 507
 508 static void print_error_obj(struct drm_i915_error_state_buf *m,
 509                             struct intel_engine_cs *engine,
 510                             const char *name,
 511                             struct drm_i915_error_object *obj)
 512 {
 513         char out[6];
 514         int page;
 515
 516         if (!obj)
 517                 return;
 518
 519         if (name) {
 520                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
 521                            engine ? engine->name : "global", name,
 522                            upper_32_bits(obj->gtt_offset),
 523                            lower_32_bits(obj->gtt_offset));
 524         }
 525
 526         err_compression_marker(m);
 527         for (page = 0; page < obj->page_count; page++) {
 528                 int i, len;
 529
 530                 len = PAGE_SIZE;
 531                 if (page == obj->page_count - 1)
 532                         len -= obj->unused;
 533                 len = ascii85_encode_len(len);
 534
 535                 for (i = 0; i < len; i++) {
 536                         if (ascii85_encode(obj->pages[page][i], out))
 537                                 err_puts(m, out);
 538                         else
 539                                 err_puts(m, "z");
 540                 }
 541         }
 542         err_puts(m, "\n");
 543 }
 544
 545 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 546                                    const struct intel_device_info *info)
 547 {
 548 #define PRINT_FLAG(x)  err_printf(m, #x ": %s\n", yesno(info->x))
 549         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 550 #undef PRINT_FLAG
 551 }
 552
 553 static __always_inline void err_print_param(struct drm_i915_error_state_buf *m,
 554                                             const char *name,
 555                                             const char *type,
 556                                             const void *x)
 557 {
 558         if (!__builtin_strcmp(type, "bool"))
 559                 err_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
 560         else if (!__builtin_strcmp(type, "int"))
 561                 err_printf(m, "i915.%s=%d\n", name, *(const int *)x);
 562         else if (!__builtin_strcmp(type, "unsigned int"))
 563                 err_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
 564         else if (!__builtin_strcmp(type, "char *"))
 565                 err_printf(m, "i915.%s=%s\n", name, *(const char **)x);
 566         else
 567                 BUILD_BUG();
 568 }
 569
 570 static void err_print_params(struct drm_i915_error_state_buf *m,
 571                              const struct i915_params *p)
 572 {
 573 #define PRINT(T, x) err_print_param(m, #x, #T, &p->x);
 574         I915_PARAMS_FOR_EACH(PRINT);
 575 #undef PRINT
 576 }
 577
 578 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 579                             struct drm_i915_private *i915)
 580 {
 581         struct pci_dev *pdev = i915->drm.pdev;
 582
 583         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 584         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 585         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 586                    pdev->subsystem_vendor,
 587                    pdev->subsystem_device);
 588 }
 589
 590 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 591                             const struct i915_gpu_state *error)
 592 {
 593         struct drm_i915_private *dev_priv = m->i915;
 594         struct drm_i915_error_object *obj;
 595         int i, j;
 596
 597         if (!error) {
 598                 err_printf(m, "No error state collected\n");
 599                 return 0;
 600         }
 601
 602         if (*error->error_msg)
 603                 err_printf(m, "%s\n", error->error_msg);
 604         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 605         err_printf(m, "Time: %ld s %ld us\n",
 606                    error->time.tv_sec, error->time.tv_usec);
 607         err_printf(m, "Boottime: %ld s %ld us\n",
 608                    error->boottime.tv_sec, error->boottime.tv_usec);
 609         err_printf(m, "Uptime: %ld s %ld us\n",
 610                    error->uptime.tv_sec, error->uptime.tv_usec);
 611
 612         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 613                 if (error->engine[i].hangcheck_stalled &&
 614                     error->engine[i].context.pid) {
 615                         err_printf(m, "Active process (on ring %s): %s [%d], score %d\n",
 616                                    engine_str(i),
 617                                    error->engine[i].context.comm,
 618                                    error->engine[i].context.pid,
 619                                    error->engine[i].context.ban_score);
 620                 }
 621         }
 622         err_printf(m, "Reset count: %u\n", error->reset_count);
 623         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 624         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 625         err_print_pciid(m, error->i915);
 626
 627         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 628
 629         if (HAS_CSR(dev_priv)) {
 630                 struct intel_csr *csr = &dev_priv->csr;
 631
 632                 err_printf(m, "DMC loaded: %s\n",
 633                            yesno(csr->dmc_payload != NULL));
 634                 err_printf(m, "DMC fw version: %d.%d\n",
 635                            CSR_VERSION_MAJOR(csr->version),
 636                            CSR_VERSION_MINOR(csr->version));
 637         }
 638
 639         err_printf(m, "GT awake: %s\n", yesno(error->awake));
 640         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 641         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 642         err_printf(m, "EIR: 0x%08x\n", error->eir);
 643         err_printf(m, "IER: 0x%08x\n", error->ier);
 644         for (i = 0; i < error->ngtier; i++)
 645                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
 646         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 647         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 648         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 649         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 650         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 651
 652         for (i = 0; i < error->nfence; i++)
 653                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 654
 655         if (INTEL_GEN(dev_priv) >= 6) {
 656                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 657
 658                 if (INTEL_GEN(dev_priv) >= 8)
 659                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 660                                    error->fault_data1, error->fault_data0);
 661
 662                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 663         }
 664
 665         if (IS_GEN7(dev_priv))
 666                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 667
 668         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 669                 if (error->engine[i].engine_id != -1)
 670                         error_print_engine(m, &error->engine[i]);
 671         }
 672
 673         for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
 674                 char buf[128];
 675                 int len, first = 1;
 676
 677                 if (!error->active_vm[i])
 678                         break;
 679
 680                 len = scnprintf(buf, sizeof(buf), "Active (");
 681                 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
 682                         if (error->engine[j].vm != error->active_vm[i])
 683                                 continue;
 684
 685                         len += scnprintf(buf + len, sizeof(buf), "%s%s",
 686                                          first ? "" : ", ",
 687                                          dev_priv->engine[j]->name);
 688                         first = 0;
 689                 }
 690                 scnprintf(buf + len, sizeof(buf), ")");
 691                 print_error_buffers(m, buf,
 692                                     error->active_bo[i],
 693                                     error->active_bo_count[i]);
 694         }
 695
 696         print_error_buffers(m, "Pinned (global)",
 697                             error->pinned_bo,
 698                             error->pinned_bo_count);
 699
 700         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 701                 const struct drm_i915_error_engine *ee = &error->engine[i];
 702
 703                 obj = ee->batchbuffer;
 704                 if (obj) {
 705                         err_puts(m, dev_priv->engine[i]->name);
 706                         if (ee->context.pid)
 707                                 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d)",
 708                                            ee->context.comm,
 709                                            ee->context.pid,
 710                                            ee->context.handle,
 711                                            ee->context.hw_id,
 712                                            ee->context.ban_score);
 713                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 714                                    upper_32_bits(obj->gtt_offset),
 715                                    lower_32_bits(obj->gtt_offset));
 716                         print_error_obj(m, dev_priv->engine[i], NULL, obj);
 717                 }
 718
 719                 for (j = 0; j < ee->user_bo_count; j++)
 720                         print_error_obj(m, dev_priv->engine[i],
 721                                         "user", ee->user_bo[j]);
 722
 723                 if (ee->num_requests) {
 724                         err_printf(m, "%s --- %d requests\n",
 725                                    dev_priv->engine[i]->name,
 726                                    ee->num_requests);
 727                         for (j = 0; j < ee->num_requests; j++)
 728                                 error_print_request(m, " ", &ee->requests[j]);
 729                 }
 730
 731                 if (IS_ERR(ee->waiters)) {
 732                         err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
 733                                    dev_priv->engine[i]->name);
 734                 } else if (ee->num_waiters) {
 735                         err_printf(m, "%s --- %d waiters\n",
 736                                    dev_priv->engine[i]->name,
 737                                    ee->num_waiters);
 738                         for (j = 0; j < ee->num_waiters; j++) {
 739                                 err_printf(m, " seqno 0x%08x for %s [%d]\n",
 740                                            ee->waiters[j].seqno,
 741                                            ee->waiters[j].comm,
 742                                            ee->waiters[j].pid);
 743                         }
 744                 }
 745
 746                 print_error_obj(m, dev_priv->engine[i],
 747                                 "ringbuffer", ee->ringbuffer);
 748
 749                 print_error_obj(m, dev_priv->engine[i],
 750                                 "HW Status", ee->hws_page);
 751
 752                 print_error_obj(m, dev_priv->engine[i],
 753                                 "HW context", ee->ctx);
 754
 755                 print_error_obj(m, dev_priv->engine[i],
 756                                 "WA context", ee->wa_ctx);
 757
 758                 print_error_obj(m, dev_priv->engine[i],
 759                                 "WA batchbuffer", ee->wa_batchbuffer);
 760         }
 761
 762         print_error_obj(m, NULL, "Semaphores", error->semaphore);
 763
 764         print_error_obj(m, NULL, "GuC log buffer", error->guc_log);
 765
 766         if (error->overlay)
 767                 intel_overlay_print_error_state(m, error->overlay);
 768
 769         if (error->display)
 770                 intel_display_print_error_state(m, error->display);
 771
 772         err_print_capabilities(m, &error->device_info);
 773         err_print_params(m, &error->params);
 774
 775         if (m->bytes == 0 && m->err)
 776                 return m->err;
 777
 778         return 0;
 779 }
 780
 781 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 782                               struct drm_i915_private *i915,
 783                               size_t count, loff_t pos)
 784 {
 785         memset(ebuf, 0, sizeof(*ebuf));
 786         ebuf->i915 = i915;
 787
 788         /* We need to have enough room to store any i915_error_state printf
 789          * so that we can move it to start position.
 790          */
 791         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 792         ebuf->buf = kmalloc(ebuf->size,
 793                                 GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
 794
 795         if (ebuf->buf == NULL) {
 796                 ebuf->size = PAGE_SIZE;
 797                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 798         }
 799
 800         if (ebuf->buf == NULL) {
 801                 ebuf->size = 128;
 802                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 803         }
 804
 805         if (ebuf->buf == NULL)
 806                 return -ENOMEM;
 807
 808         ebuf->start = pos;
 809
 810         return 0;
 811 }
 812
 813 static void i915_error_object_free(struct drm_i915_error_object *obj)
 814 {
 815         int page;
 816
 817         if (obj == NULL)
 818                 return;
 819
 820         for (page = 0; page < obj->page_count; page++)
 821                 free_page((unsigned long)obj->pages[page]);
 822
 823         kfree(obj);
 824 }
 825
 826 static __always_inline void free_param(const char *type, void *x)
 827 {
 828         if (!__builtin_strcmp(type, "char *"))
 829                 kfree(*(void **)x);
 830 }
 831
 832 void __i915_gpu_state_free(struct kref *error_ref)
 833 {
 834         struct i915_gpu_state *error =
 835                 container_of(error_ref, typeof(*error), ref);
 836         long i, j;
 837
 838         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 839                 struct drm_i915_error_engine *ee = &error->engine[i];
 840
 841                 for (j = 0; j < ee->user_bo_count; j++)
 842                         i915_error_object_free(ee->user_bo[j]);
 843                 kfree(ee->user_bo);
 844
 845                 i915_error_object_free(ee->batchbuffer);
 846                 i915_error_object_free(ee->wa_batchbuffer);
 847                 i915_error_object_free(ee->ringbuffer);
 848                 i915_error_object_free(ee->hws_page);
 849                 i915_error_object_free(ee->ctx);
 850                 i915_error_object_free(ee->wa_ctx);
 851
 852                 kfree(ee->requests);
 853                 if (!IS_ERR_OR_NULL(ee->waiters))
 854                         kfree(ee->waiters);
 855         }
 856
 857         i915_error_object_free(error->semaphore);
 858         i915_error_object_free(error->guc_log);
 859
 860         for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
 861                 kfree(error->active_bo[i]);
 862         kfree(error->pinned_bo);
 863
 864         kfree(error->overlay);
 865         kfree(error->display);
 866
 867 #define FREE(T, x) free_param(#T, &error->params.x);
 868         I915_PARAMS_FOR_EACH(FREE);
 869 #undef FREE
 870
 871         kfree(error);
 872 }
 873
 874 static struct drm_i915_error_object *
 875 i915_error_object_create(struct drm_i915_private *i915,
 876                          struct i915_vma *vma)
 877 {
 878         struct i915_ggtt *ggtt = &i915->ggtt;
 879         const u64 slot = ggtt->error_capture.start;
 880         struct drm_i915_error_object *dst;
 881         struct compress compress;
 882         unsigned long num_pages;
 883         struct sgt_iter iter;
 884         dma_addr_t dma;
 885
 886         if (!vma)
 887                 return NULL;
 888
 889         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 890         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 891         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
 892                       GFP_ATOMIC | __GFP_NOWARN);
 893         if (!dst)
 894                 return NULL;
 895
 896         dst->gtt_offset = vma->node.start;
 897         dst->gtt_size = vma->node.size;
 898         dst->page_count = 0;
 899         dst->unused = 0;
 900
 901         if (!compress_init(&compress)) {
 902                 kfree(dst);
 903                 return NULL;
 904         }
 905
 906         for_each_sgt_dma(dma, iter, vma->pages) {
 907                 void __iomem *s;
 908                 int ret;
 909
 910                 ggtt->base.insert_page(&ggtt->base, dma, slot,
 911                                        I915_CACHE_NONE, 0);
 912
 913                 s = io_mapping_map_atomic_wc(&ggtt->mappable, slot);
 914                 ret = compress_page(&compress, (void  __force *)s, dst);
 915                 io_mapping_unmap_atomic(s);
 916
 917                 if (ret)
 918                         goto unwind;
 919         }
 920         goto out;
 921
 922 unwind:
 923         while (dst->page_count--)
 924                 free_page((unsigned long)dst->pages[dst->page_count]);
 925         kfree(dst);
 926         dst = NULL;
 927
 928 out:
 929         compress_fini(&compress, dst);
 930         ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
 931         return dst;
 932 }
 933
 934 /* The error capture is special as tries to run underneath the normal
 935  * locking rules - so we use the raw version of the i915_gem_active lookup.
 936  */
 937 static inline uint32_t
 938 __active_get_seqno(struct i915_gem_active *active)
 939 {
 940         struct drm_i915_gem_request *request;
 941
 942         request = __i915_gem_active_peek(active);
 943         return request ? request->global_seqno : 0;
 944 }
 945
 946 static inline int
 947 __active_get_engine_id(struct i915_gem_active *active)
 948 {
 949         struct drm_i915_gem_request *request;
 950
 951         request = __i915_gem_active_peek(active);
 952         return request ? request->engine->id : -1;
 953 }
 954
 955 static void capture_bo(struct drm_i915_error_buffer *err,
 956                        struct i915_vma *vma)
 957 {
 958         struct drm_i915_gem_object *obj = vma->obj;
 959         int i;
 960
 961         err->size = obj->base.size;
 962         err->name = obj->base.name;
 963
 964         for (i = 0; i < I915_NUM_ENGINES; i++)
 965                 err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
 966         err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
 967         err->engine = __active_get_engine_id(&obj->frontbuffer_write);
 968
 969         err->gtt_offset = vma->node.start;
 970         err->read_domains = obj->base.read_domains;
 971         err->write_domain = obj->base.write_domain;
 972         err->fence_reg = vma->fence ? vma->fence->id : -1;
 973         err->tiling = i915_gem_object_get_tiling(obj);
 974         err->dirty = obj->mm.dirty;
 975         err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
 976         err->userptr = obj->userptr.mm != NULL;
 977         err->cache_level = obj->cache_level;
 978 }
 979
 980 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
 981                             int count, struct list_head *head,
 982                             bool pinned_only)
 983 {
 984         struct i915_vma *vma;
 985         int i = 0;
 986
 987         list_for_each_entry(vma, head, vm_link) {
 988                 if (pinned_only && !i915_vma_is_pinned(vma))
 989                         continue;
 990
 991                 capture_bo(err++, vma);
 992                 if (++i == count)
 993                         break;
 994         }
 995
 996         return i;
 997 }
 998
 999 /* Generate a semi-unique error code. The code is not meant to have meaning, The
1000  * code's only purpose is to try to prevent false duplicated bug reports by
1001  * grossly estimating a GPU error state.
1002  *
1003  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1004  * the hang if we could strip the GTT offset information from it.
1005  *
1006  * It's only a small step better than a random number in its current form.
1007  */
1008 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
1009                                          struct i915_gpu_state *error,
1010                                          int *engine_id)
1011 {
1012         uint32_t error_code = 0;
1013         int i;
1014
1015         /* IPEHR would be an ideal way to detect errors, as it's the gross
1016          * measure of "the command that hung." However, has some very common
1017          * synchronization commands which almost always appear in the case
1018          * strictly a client bug. Use instdone to differentiate those some.
1019          */
1020         for (i = 0; i < I915_NUM_ENGINES; i++) {
1021                 if (error->engine[i].hangcheck_stalled) {
1022                         if (engine_id)
1023                                 *engine_id = i;
1024
1025                         return error->engine[i].ipehr ^
1026                                error->engine[i].instdone.instdone;
1027                 }
1028         }
1029
1030         return error_code;
1031 }
1032
1033 static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
1034                                    struct i915_gpu_state *error)
1035 {
1036         int i;
1037
1038         if (INTEL_GEN(dev_priv) >= 6) {
1039                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1040                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1041         } else if (INTEL_GEN(dev_priv) >= 4) {
1042                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1043                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1044         } else {
1045                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1046                         error->fence[i] = I915_READ(FENCE_REG(i));
1047         }
1048         error->nfence = i;
1049 }
1050
1051 static inline u32
1052 gen8_engine_sync_index(struct intel_engine_cs *engine,
1053                        struct intel_engine_cs *other)
1054 {
1055         int idx;
1056
1057         /*
1058          * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
1059          * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
1060          * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
1061          * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
1062          * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
1063          */
1064
1065         idx = (other - engine) - 1;
1066         if (idx < 0)
1067                 idx += I915_NUM_ENGINES;
1068
1069         return idx;
1070 }
1071
1072 static void gen8_record_semaphore_state(struct i915_gpu_state *error,
1073                                         struct intel_engine_cs *engine,
1074                                         struct drm_i915_error_engine *ee)
1075 {
1076         struct drm_i915_private *dev_priv = engine->i915;
1077         struct intel_engine_cs *to;
1078         enum intel_engine_id id;
1079
1080         if (!error->semaphore)
1081                 return;
1082
1083         for_each_engine(to, dev_priv, id) {
1084                 int idx;
1085                 u16 signal_offset;
1086                 u32 *tmp;
1087
1088                 if (engine == to)
1089                         continue;
1090
1091                 signal_offset =
1092                         (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
1093                 tmp = error->semaphore->pages[0];
1094                 idx = gen8_engine_sync_index(engine, to);
1095
1096                 ee->semaphore_mboxes[idx] = tmp[signal_offset];
1097         }
1098 }
1099
1100 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1101                                         struct drm_i915_error_engine *ee)
1102 {
1103         struct drm_i915_private *dev_priv = engine->i915;
1104
1105         ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1106         ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1107         if (HAS_VEBOX(dev_priv))
1108                 ee->semaphore_mboxes[2] =
1109                         I915_READ(RING_SYNC_2(engine->mmio_base));
1110 }
1111
1112 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1113                                         struct drm_i915_error_engine *ee)
1114 {
1115         struct intel_breadcrumbs *b = &engine->breadcrumbs;
1116         struct drm_i915_error_waiter *waiter;
1117         struct rb_node *rb;
1118         int count;
1119
1120         ee->num_waiters = 0;
1121         ee->waiters = NULL;
1122
1123         if (RB_EMPTY_ROOT(&b->waiters))
1124                 return;
1125
1126         if (!spin_trylock_irq(&b->rb_lock)) {
1127                 ee->waiters = ERR_PTR(-EDEADLK);
1128                 return;
1129         }
1130
1131         count = 0;
1132         for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1133                 count++;
1134         spin_unlock_irq(&b->rb_lock);
1135
1136         waiter = NULL;
1137         if (count)
1138                 waiter = kmalloc_array(count,
1139                                        sizeof(struct drm_i915_error_waiter),
1140                                        GFP_ATOMIC);
1141         if (!waiter)
1142                 return;
1143
1144         if (!spin_trylock_irq(&b->rb_lock)) {
1145                 kfree(waiter);
1146                 ee->waiters = ERR_PTR(-EDEADLK);
1147                 return;
1148         }
1149
1150         ee->waiters = waiter;
1151         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1152                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1153
1154                 strcpy(waiter->comm, w->tsk->comm);
1155                 waiter->pid = w->tsk->pid;
1156                 waiter->seqno = w->seqno;
1157                 waiter++;
1158
1159                 if (++ee->num_waiters == count)
1160                         break;
1161         }
1162         spin_unlock_irq(&b->rb_lock);
1163 }
1164
1165 static void error_record_engine_registers(struct i915_gpu_state *error,
1166                                           struct intel_engine_cs *engine,
1167                                           struct drm_i915_error_engine *ee)
1168 {
1169         struct drm_i915_private *dev_priv = engine->i915;
1170
1171         if (INTEL_GEN(dev_priv) >= 6) {
1172                 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1173                 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1174                 if (INTEL_GEN(dev_priv) >= 8)
1175                         gen8_record_semaphore_state(error, engine, ee);
1176                 else
1177                         gen6_record_semaphore_state(engine, ee);
1178         }
1179
1180         if (INTEL_GEN(dev_priv) >= 4) {
1181                 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1182                 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1183                 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1184                 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1185                 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1186                 if (INTEL_GEN(dev_priv) >= 8) {
1187                         ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1188                         ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1189                 }
1190                 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1191         } else {
1192                 ee->faddr = I915_READ(DMA_FADD_I8XX);
1193                 ee->ipeir = I915_READ(IPEIR);
1194                 ee->ipehr = I915_READ(IPEHR);
1195         }
1196
1197         intel_engine_get_instdone(engine, &ee->instdone);
1198
1199         ee->waiting = intel_engine_has_waiter(engine);
1200         ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1201         ee->acthd = intel_engine_get_active_head(engine);
1202         ee->seqno = intel_engine_get_seqno(engine);
1203         ee->last_seqno = intel_engine_last_submit(engine);
1204         ee->start = I915_READ_START(engine);
1205         ee->head = I915_READ_HEAD(engine);
1206         ee->tail = I915_READ_TAIL(engine);
1207         ee->ctl = I915_READ_CTL(engine);
1208         if (INTEL_GEN(dev_priv) > 2)
1209                 ee->mode = I915_READ_MODE(engine);
1210
1211         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1212                 i915_reg_t mmio;
1213
1214                 if (IS_GEN7(dev_priv)) {
1215                         switch (engine->id) {
1216                         default:
1217                         case RCS:
1218                                 mmio = RENDER_HWS_PGA_GEN7;
1219                                 break;
1220                         case BCS:
1221                                 mmio = BLT_HWS_PGA_GEN7;
1222                                 break;
1223                         case VCS:
1224                                 mmio = BSD_HWS_PGA_GEN7;
1225                                 break;
1226                         case VECS:
1227                                 mmio = VEBOX_HWS_PGA_GEN7;
1228                                 break;
1229                         }
1230                 } else if (IS_GEN6(engine->i915)) {
1231                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1232                 } else {
1233                         /* XXX: gen8 returns to sanity */
1234                         mmio = RING_HWS_PGA(engine->mmio_base);
1235                 }
1236
1237                 ee->hws = I915_READ(mmio);
1238         }
1239
1240         ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1241         ee->hangcheck_action = engine->hangcheck.action;
1242         ee->hangcheck_stalled = engine->hangcheck.stalled;
1243         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1244                                                   engine);
1245
1246         if (USES_PPGTT(dev_priv)) {
1247                 int i;
1248
1249                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1250
1251                 if (IS_GEN6(dev_priv))
1252                         ee->vm_info.pp_dir_base =
1253                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
1254                 else if (IS_GEN7(dev_priv))
1255                         ee->vm_info.pp_dir_base =
1256                                 I915_READ(RING_PP_DIR_BASE(engine));
1257                 else if (INTEL_GEN(dev_priv) >= 8)
1258                         for (i = 0; i < 4; i++) {
1259                                 ee->vm_info.pdp[i] =
1260                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
1261                                 ee->vm_info.pdp[i] <<= 32;
1262                                 ee->vm_info.pdp[i] |=
1263                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
1264                         }
1265         }
1266 }
1267
1268 static void record_request(struct drm_i915_gem_request *request,
1269                            struct drm_i915_error_request *erq)
1270 {
1271         erq->context = request->ctx->hw_id;
1272         erq->ban_score = atomic_read(&request->ctx->ban_score);
1273         erq->seqno = request->global_seqno;
1274         erq->jiffies = request->emitted_jiffies;
1275         erq->head = request->head;
1276         erq->tail = request->tail;
1277
1278         rcu_read_lock();
1279         erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
1280         rcu_read_unlock();
1281 }
1282
1283 static void engine_record_requests(struct intel_engine_cs *engine,
1284                                    struct drm_i915_gem_request *first,
1285                                    struct drm_i915_error_engine *ee)
1286 {
1287         struct drm_i915_gem_request *request;
1288         int count;
1289
1290         count = 0;
1291         request = first;
1292         list_for_each_entry_from(request, &engine->timeline->requests, link)
1293                 count++;
1294         if (!count)
1295                 return;
1296
1297         ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1298         if (!ee->requests)
1299                 return;
1300
1301         ee->num_requests = count;
1302
1303         count = 0;
1304         request = first;
1305         list_for_each_entry_from(request, &engine->timeline->requests, link) {
1306                 if (count >= ee->num_requests) {
1307                         /*
1308                          * If the ring request list was changed in
1309                          * between the point where the error request
1310                          * list was created and dimensioned and this
1311                          * point then just exit early to avoid crashes.
1312                          *
1313                          * We don't need to communicate that the
1314                          * request list changed state during error
1315                          * state capture and that the error state is
1316                          * slightly incorrect as a consequence since we
1317                          * are typically only interested in the request
1318                          * list state at the point of error state
1319                          * capture, not in any changes happening during
1320                          * the capture.
1321                          */
1322                         break;
1323                 }
1324
1325                 record_request(request, &ee->requests[count++]);
1326         }
1327         ee->num_requests = count;
1328 }
1329
1330 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1331                                           struct drm_i915_error_engine *ee)
1332 {
1333         const struct execlist_port *port = engine->execlist_port;
1334         unsigned int n;
1335
1336         for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
1337                 struct drm_i915_gem_request *rq = port_request(&port[n]);
1338
1339                 if (!rq)
1340                         break;
1341
1342                 record_request(rq, &ee->execlist[n]);
1343         }
1344 }
1345
1346 static void record_context(struct drm_i915_error_context *e,
1347                            struct i915_gem_context *ctx)
1348 {
1349         if (ctx->pid) {
1350                 struct task_struct *task;
1351
1352                 rcu_read_lock();
1353                 task = pid_task(ctx->pid, PIDTYPE_PID);
1354                 if (task) {
1355                         strcpy(e->comm, task->comm);
1356                         e->pid = task->pid;
1357                 }
1358                 rcu_read_unlock();
1359         }
1360
1361         e->handle = ctx->user_handle;
1362         e->hw_id = ctx->hw_id;
1363         e->ban_score = atomic_read(&ctx->ban_score);
1364         e->guilty = atomic_read(&ctx->guilty_count);
1365         e->active = atomic_read(&ctx->active_count);
1366 }
1367
1368 static void request_record_user_bo(struct drm_i915_gem_request *request,
1369                                    struct drm_i915_error_engine *ee)
1370 {
1371         struct i915_gem_capture_list *c;
1372         struct drm_i915_error_object **bo;
1373         long count;
1374
1375         count = 0;
1376         for (c = request->capture_list; c; c = c->next)
1377                 count++;
1378
1379         bo = NULL;
1380         if (count)
1381                 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
1382         if (!bo)
1383                 return;
1384
1385         count = 0;
1386         for (c = request->capture_list; c; c = c->next) {
1387                 bo[count] = i915_error_object_create(request->i915, c->vma);
1388                 if (!bo[count])
1389                         break;
1390                 count++;
1391         }
1392
1393         ee->user_bo = bo;
1394         ee->user_bo_count = count;
1395 }
1396
1397 static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1398                                   struct i915_gpu_state *error)
1399 {
1400         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1401         int i;
1402
1403         error->semaphore =
1404                 i915_error_object_create(dev_priv, dev_priv->semaphore);
1405
1406         for (i = 0; i < I915_NUM_ENGINES; i++) {
1407                 struct intel_engine_cs *engine = dev_priv->engine[i];
1408                 struct drm_i915_error_engine *ee = &error->engine[i];
1409                 struct drm_i915_gem_request *request;
1410
1411                 ee->engine_id = -1;
1412
1413                 if (!engine)
1414                         continue;
1415
1416                 ee->engine_id = i;
1417
1418                 error_record_engine_registers(error, engine, ee);
1419                 error_record_engine_waiters(engine, ee);
1420                 error_record_engine_execlists(engine, ee);
1421
1422                 request = i915_gem_find_active_request(engine);
1423                 if (request) {
1424                         struct intel_ring *ring;
1425
1426                         ee->vm = request->ctx->ppgtt ?
1427                                 &request->ctx->ppgtt->base : &ggtt->base;
1428
1429                         record_context(&ee->context, request->ctx);
1430
1431                         /* We need to copy these to an anonymous buffer
1432                          * as the simplest method to avoid being overwritten
1433                          * by userspace.
1434                          */
1435                         ee->batchbuffer =
1436                                 i915_error_object_create(dev_priv,
1437                                                          request->batch);
1438
1439                         if (HAS_BROKEN_CS_TLB(dev_priv))
1440                                 ee->wa_batchbuffer =
1441                                         i915_error_object_create(dev_priv,
1442                                                                  engine->scratch);
1443                         request_record_user_bo(request, ee);
1444
1445                         ee->ctx =
1446                                 i915_error_object_create(dev_priv,
1447                                                          request->ctx->engine[i].state);
1448
1449                         error->simulated |=
1450                                 i915_gem_context_no_error_capture(request->ctx);
1451
1452                         ee->rq_head = request->head;
1453                         ee->rq_post = request->postfix;
1454                         ee->rq_tail = request->tail;
1455
1456                         ring = request->ring;
1457                         ee->cpu_ring_head = ring->head;
1458                         ee->cpu_ring_tail = ring->tail;
1459                         ee->ringbuffer =
1460                                 i915_error_object_create(dev_priv, ring->vma);
1461
1462                         engine_record_requests(engine, request, ee);
1463                 }
1464
1465                 ee->hws_page =
1466                         i915_error_object_create(dev_priv,
1467                                                  engine->status_page.vma);
1468
1469                 ee->wa_ctx =
1470                         i915_error_object_create(dev_priv, engine->wa_ctx.vma);
1471         }
1472 }
1473
1474 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1475                                 struct i915_gpu_state *error,
1476                                 struct i915_address_space *vm,
1477                                 int idx)
1478 {
1479         struct drm_i915_error_buffer *active_bo;
1480         struct i915_vma *vma;
1481         int count;
1482
1483         count = 0;
1484         list_for_each_entry(vma, &vm->active_list, vm_link)
1485                 count++;
1486
1487         active_bo = NULL;
1488         if (count)
1489                 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1490         if (active_bo)
1491                 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1492         else
1493                 count = 0;
1494
1495         error->active_vm[idx] = vm;
1496         error->active_bo[idx] = active_bo;
1497         error->active_bo_count[idx] = count;
1498 }
1499
1500 static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
1501                                         struct i915_gpu_state *error)
1502 {
1503         int cnt = 0, i, j;
1504
1505         BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1506         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1507         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1508
1509         /* Scan each engine looking for unique active contexts/vm */
1510         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1511                 struct drm_i915_error_engine *ee = &error->engine[i];
1512                 bool found;
1513
1514                 if (!ee->vm)
1515                         continue;
1516
1517                 found = false;
1518                 for (j = 0; j < i && !found; j++)
1519                         found = error->engine[j].vm == ee->vm;
1520                 if (!found)
1521                         i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1522         }
1523 }
1524
1525 static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
1526                                         struct i915_gpu_state *error)
1527 {
1528         struct i915_address_space *vm = &dev_priv->ggtt.base;
1529         struct drm_i915_error_buffer *bo;
1530         struct i915_vma *vma;
1531         int count_inactive, count_active;
1532
1533         count_inactive = 0;
1534         list_for_each_entry(vma, &vm->active_list, vm_link)
1535                 count_inactive++;
1536
1537         count_active = 0;
1538         list_for_each_entry(vma, &vm->inactive_list, vm_link)
1539                 count_active++;
1540
1541         bo = NULL;
1542         if (count_inactive + count_active)
1543                 bo = kcalloc(count_inactive + count_active,
1544                              sizeof(*bo), GFP_ATOMIC);
1545         if (!bo)
1546                 return;
1547
1548         count_inactive = capture_error_bo(bo, count_inactive,
1549                                           &vm->active_list, true);
1550         count_active = capture_error_bo(bo + count_inactive, count_active,
1551                                         &vm->inactive_list, true);
1552         error->pinned_bo_count = count_inactive + count_active;
1553         error->pinned_bo = bo;
1554 }
1555
1556 static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
1557                                             struct i915_gpu_state *error)
1558 {
1559         /* Capturing log buf contents won't be useful if logging was disabled */
1560         if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
1561                 return;
1562
1563         error->guc_log = i915_error_object_create(dev_priv,
1564                                                   dev_priv->guc.log.vma);
1565 }
1566
1567 /* Capture all registers which don't fit into another category. */
1568 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1569                                    struct i915_gpu_state *error)
1570 {
1571         int i;
1572
1573         /* General organization
1574          * 1. Registers specific to a single generation
1575          * 2. Registers which belong to multiple generations
1576          * 3. Feature specific registers.
1577          * 4. Everything else
1578          * Please try to follow the order.
1579          */
1580
1581         /* 1: Registers specific to a single generation */
1582         if (IS_VALLEYVIEW(dev_priv)) {
1583                 error->gtier[0] = I915_READ(GTIER);
1584                 error->ier = I915_READ(VLV_IER);
1585                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1586         }
1587
1588         if (IS_GEN7(dev_priv))
1589                 error->err_int = I915_READ(GEN7_ERR_INT);
1590
1591         if (INTEL_GEN(dev_priv) >= 8) {
1592                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1593                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1594         }
1595
1596         if (IS_GEN6(dev_priv)) {
1597                 error->forcewake = I915_READ_FW(FORCEWAKE);
1598                 error->gab_ctl = I915_READ(GAB_CTL);
1599                 error->gfx_mode = I915_READ(GFX_MODE);
1600         }
1601
1602         /* 2: Registers which belong to multiple generations */
1603         if (INTEL_GEN(dev_priv) >= 7)
1604                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1605
1606         if (INTEL_GEN(dev_priv) >= 6) {
1607                 error->derrmr = I915_READ(DERRMR);
1608                 error->error = I915_READ(ERROR_GEN6);
1609                 error->done_reg = I915_READ(DONE_REG);
1610         }
1611
1612         if (INTEL_GEN(dev_priv) >= 5)
1613                 error->ccid = I915_READ(CCID);
1614
1615         /* 3: Feature specific registers */
1616         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1617                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1618                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1619         }
1620
1621         /* 4: Everything else */
1622         if (INTEL_GEN(dev_priv) >= 8) {
1623                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1624                 for (i = 0; i < 4; i++)
1625                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1626                 error->ngtier = 4;
1627         } else if (HAS_PCH_SPLIT(dev_priv)) {
1628                 error->ier = I915_READ(DEIER);
1629                 error->gtier[0] = I915_READ(GTIER);
1630                 error->ngtier = 1;
1631         } else if (IS_GEN2(dev_priv)) {
1632                 error->ier = I915_READ16(IER);
1633         } else if (!IS_VALLEYVIEW(dev_priv)) {
1634                 error->ier = I915_READ(IER);
1635         }
1636         error->eir = I915_READ(EIR);
1637         error->pgtbl_er = I915_READ(PGTBL_ER);
1638 }
1639
1640 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1641                                    struct i915_gpu_state *error,
1642                                    u32 engine_mask,
1643                                    const char *error_msg)
1644 {
1645         u32 ecode;
1646         int engine_id = -1, len;
1647
1648         ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1649
1650         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1651                         "GPU HANG: ecode %d:%d:0x%08x",
1652                         INTEL_GEN(dev_priv), engine_id, ecode);
1653
1654         if (engine_id != -1 && error->engine[engine_id].context.pid)
1655                 len += scnprintf(error->error_msg + len,
1656                                  sizeof(error->error_msg) - len,
1657                                  ", in %s [%d]",
1658                                  error->engine[engine_id].context.comm,
1659                                  error->engine[engine_id].context.pid);
1660
1661         scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1662                   ", reason: %s, action: %s",
1663                   error_msg,
1664                   engine_mask ? "reset" : "continue");
1665 }
1666
1667 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1668                                    struct i915_gpu_state *error)
1669 {
1670         error->awake = dev_priv->gt.awake;
1671         error->wakelock = atomic_read(&dev_priv->pm.wakeref_count);
1672         error->suspended = dev_priv->pm.suspended;
1673
1674         error->iommu = -1;
1675 #ifdef CONFIG_INTEL_IOMMU
1676         error->iommu = intel_iommu_gfx_mapped;
1677 #endif
1678         error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1679         error->suspend_count = dev_priv->suspend_count;
1680
1681         memcpy(&error->device_info,
1682                INTEL_INFO(dev_priv),
1683                sizeof(error->device_info));
1684 }
1685
1686 static __always_inline void dup_param(const char *type, void *x)
1687 {
1688         if (!__builtin_strcmp(type, "char *"))
1689                 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC);
1690 }
1691
1692 static int capture(void *data)
1693 {
1694         struct i915_gpu_state *error = data;
1695
1696         do_gettimeofday(&error->time);
1697         error->boottime = ktime_to_timeval(ktime_get_boottime());
1698         error->uptime =
1699                 ktime_to_timeval(ktime_sub(ktime_get(),
1700                                            error->i915->gt.last_init_time));
1701
1702         error->params = i915;
1703 #define DUP(T, x) dup_param(#T, &error->params.x);
1704         I915_PARAMS_FOR_EACH(DUP);
1705 #undef DUP
1706
1707         i915_capture_gen_state(error->i915, error);
1708         i915_capture_reg_state(error->i915, error);
1709         i915_gem_record_fences(error->i915, error);
1710         i915_gem_record_rings(error->i915, error);
1711         i915_capture_active_buffers(error->i915, error);
1712         i915_capture_pinned_buffers(error->i915, error);
1713         i915_gem_capture_guc_log_buffer(error->i915, error);
1714
1715         error->overlay = intel_overlay_capture_error_state(error->i915);
1716         error->display = intel_display_capture_error_state(error->i915);
1717
1718         return 0;
1719 }
1720
1721 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1722
1723 struct i915_gpu_state *
1724 i915_capture_gpu_state(struct drm_i915_private *i915)
1725 {
1726         struct i915_gpu_state *error;
1727
1728         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1729         if (!error)
1730                 return NULL;
1731
1732         kref_init(&error->ref);
1733         error->i915 = i915;
1734
1735         stop_machine(capture, error, NULL);
1736
1737         return error;
1738 }
1739
1740 /**
1741  * i915_capture_error_state - capture an error record for later analysis
1742  * @dev: drm device
1743  *
1744  * Should be called when an error is detected (either a hang or an error
1745  * interrupt) to capture error state from the time of the error.  Fills
1746  * out a structure which becomes available in debugfs for user level tools
1747  * to pick up.
1748  */
1749 void i915_capture_error_state(struct drm_i915_private *dev_priv,
1750                               u32 engine_mask,
1751                               const char *error_msg)
1752 {
1753         static bool warned;
1754         struct i915_gpu_state *error;
1755         unsigned long flags;
1756
1757         if (!i915.error_capture)
1758                 return;
1759
1760         if (READ_ONCE(dev_priv->gpu_error.first_error))
1761                 return;
1762
1763         error = i915_capture_gpu_state(dev_priv);
1764         if (!error) {
1765                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1766                 return;
1767         }
1768
1769         i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1770         DRM_INFO("%s\n", error->error_msg);
1771
1772         if (!error->simulated) {
1773                 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1774                 if (!dev_priv->gpu_error.first_error) {
1775                         dev_priv->gpu_error.first_error = error;
1776                         error = NULL;
1777                 }
1778                 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1779         }
1780
1781         if (error) {
1782                 __i915_gpu_state_free(&error->ref);
1783                 return;
1784         }
1785
1786         if (!warned &&
1787             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1788                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1789                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1790                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1791                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1792                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1793                          dev_priv->drm.primary->index);
1794                 warned = true;
1795         }
1796 }
1797
1798 struct i915_gpu_state *
1799 i915_first_error_state(struct drm_i915_private *i915)
1800 {
1801         struct i915_gpu_state *error;
1802
1803         spin_lock_irq(&i915->gpu_error.lock);
1804         error = i915->gpu_error.first_error;
1805         if (error)
1806                 i915_gpu_state_get(error);
1807         spin_unlock_irq(&i915->gpu_error.lock);
1808
1809         return error;
1810 }
1811
1812 void i915_reset_error_state(struct drm_i915_private *i915)
1813 {
1814         struct i915_gpu_state *error;
1815
1816         spin_lock_irq(&i915->gpu_error.lock);
1817         error = i915->gpu_error.first_error;
1818         i915->gpu_error.first_error = NULL;
1819         spin_unlock_irq(&i915->gpu_error.lock);
1820
1821         i915_gpu_state_put(error);
1822 }