drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 174
 175 /* For display hotplug interrupt */
 176 static inline void
 177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 178                                      uint32_t mask,
 179                                      uint32_t bits)
 180 {
 181         uint32_t val;
 182
 183         lockdep_assert_held(&dev_priv->irq_lock);
 184         WARN_ON(bits & ~mask);
 185
 186         val = I915_READ(PORT_HOTPLUG_EN);
 187         val &= ~mask;
 188         val |= bits;
 189         I915_WRITE(PORT_HOTPLUG_EN, val);
 190 }
 191
 192 /**
 193  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 194  * @dev_priv: driver private
 195  * @mask: bits to update
 196  * @bits: bits to enable
 197  * NOTE: the HPD enable bits are modified both inside and outside
 198  * of an interrupt context. To avoid that read-modify-write cycles
 199  * interfer, these bits are protected by a spinlock. Since this
 200  * function is usually not called from a context where the lock is
 201  * held already, this function acquires the lock itself. A non-locking
 202  * version is also available.
 203  */
 204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 205                                    uint32_t mask,
 206                                    uint32_t bits)
 207 {
 208         spin_lock_irq(&dev_priv->irq_lock);
 209         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 210         spin_unlock_irq(&dev_priv->irq_lock);
 211 }
 212
 213 /**
 214  * ilk_update_display_irq - update DEIMR
 215  * @dev_priv: driver private
 216  * @interrupt_mask: mask of interrupt bits to update
 217  * @enabled_irq_mask: mask of interrupt bits to enable
 218  */
 219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 220                             uint32_t interrupt_mask,
 221                             uint32_t enabled_irq_mask)
 222 {
 223         uint32_t new_val;
 224
 225         lockdep_assert_held(&dev_priv->irq_lock);
 226
 227         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 228
 229         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 230                 return;
 231
 232         new_val = dev_priv->irq_mask;
 233         new_val &= ~interrupt_mask;
 234         new_val |= (~enabled_irq_mask & interrupt_mask);
 235
 236         if (new_val != dev_priv->irq_mask) {
 237                 dev_priv->irq_mask = new_val;
 238                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 239                 POSTING_READ(DEIMR);
 240         }
 241 }
 242
 243 /**
 244  * ilk_update_gt_irq - update GTIMR
 245  * @dev_priv: driver private
 246  * @interrupt_mask: mask of interrupt bits to update
 247  * @enabled_irq_mask: mask of interrupt bits to enable
 248  */
 249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 250                               uint32_t interrupt_mask,
 251                               uint32_t enabled_irq_mask)
 252 {
 253         lockdep_assert_held(&dev_priv->irq_lock);
 254
 255         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 256
 257         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 258                 return;
 259
 260         dev_priv->gt_irq_mask &= ~interrupt_mask;
 261         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 262         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268         POSTING_READ_FW(GTIMR);
 269 }
 270
 271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 272 {
 273         ilk_update_gt_irq(dev_priv, mask, 0);
 274 }
 275
 276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 277 {
 278         return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 279 }
 280
 281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 282 {
 283         return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 284 }
 285
 286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 287 {
 288         return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 289 }
 290
 291 /**
 292  * snb_update_pm_irq - update GEN6_PMIMR
 293  * @dev_priv: driver private
 294  * @interrupt_mask: mask of interrupt bits to update
 295  * @enabled_irq_mask: mask of interrupt bits to enable
 296  */
 297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 298                               uint32_t interrupt_mask,
 299                               uint32_t enabled_irq_mask)
 300 {
 301         uint32_t new_val;
 302
 303         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 304
 305         lockdep_assert_held(&dev_priv->irq_lock);
 306
 307         new_val = dev_priv->pm_imr;
 308         new_val &= ~interrupt_mask;
 309         new_val |= (~enabled_irq_mask & interrupt_mask);
 310
 311         if (new_val != dev_priv->pm_imr) {
 312                 dev_priv->pm_imr = new_val;
 313                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
 314                 POSTING_READ(gen6_pm_imr(dev_priv));
 315         }
 316 }
 317
 318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 319 {
 320         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 321                 return;
 322
 323         snb_update_pm_irq(dev_priv, mask, mask);
 324 }
 325
 326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_mask_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         lockdep_assert_held(&dev_priv->irq_lock);
 344
 345         I915_WRITE(reg, reset_mask);
 346         I915_WRITE(reg, reset_mask);
 347         POSTING_READ(reg);
 348 }
 349
 350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 351 {
 352         lockdep_assert_held(&dev_priv->irq_lock);
 353
 354         dev_priv->pm_ier |= enable_mask;
 355         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 356         gen6_unmask_pm_irq(dev_priv, enable_mask);
 357         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 358 }
 359
 360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 361 {
 362         lockdep_assert_held(&dev_priv->irq_lock);
 363
 364         dev_priv->pm_ier &= ~disable_mask;
 365         __gen6_mask_pm_irq(dev_priv, disable_mask);
 366         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 367         /* though a barrier is missing here, but don't really need a one */
 368 }
 369
 370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
 374         dev_priv->rps.pm_iir = 0;
 375         spin_unlock_irq(&dev_priv->irq_lock);
 376 }
 377
 378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 379 {
 380         if (READ_ONCE(dev_priv->rps.interrupts_enabled))
 381                 return;
 382
 383         spin_lock_irq(&dev_priv->irq_lock);
 384         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 385         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 386         dev_priv->rps.interrupts_enabled = true;
 387         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 388
 389         spin_unlock_irq(&dev_priv->irq_lock);
 390 }
 391
 392 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 393 {
 394         if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
 395                 return;
 396
 397         spin_lock_irq(&dev_priv->irq_lock);
 398         dev_priv->rps.interrupts_enabled = false;
 399
 400         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 401
 402         gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 403
 404         spin_unlock_irq(&dev_priv->irq_lock);
 405         synchronize_irq(dev_priv->drm.irq);
 406
 407         /* Now that we will not be generating any more work, flush any
 408          * outsanding tasks. As we are called on the RPS idle path,
 409          * we will reset the GPU to minimum frequencies, so the current
 410          * state of the worker can be discarded.
 411          */
 412         cancel_work_sync(&dev_priv->rps.work);
 413         gen6_reset_rps_interrupts(dev_priv);
 414 }
 415
 416 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 417 {
 418         spin_lock_irq(&dev_priv->irq_lock);
 419         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 420         spin_unlock_irq(&dev_priv->irq_lock);
 421 }
 422
 423 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 424 {
 425         spin_lock_irq(&dev_priv->irq_lock);
 426         if (!dev_priv->guc.interrupts_enabled) {
 427                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 428                                        dev_priv->pm_guc_events);
 429                 dev_priv->guc.interrupts_enabled = true;
 430                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 431         }
 432         spin_unlock_irq(&dev_priv->irq_lock);
 433 }
 434
 435 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 436 {
 437         spin_lock_irq(&dev_priv->irq_lock);
 438         dev_priv->guc.interrupts_enabled = false;
 439
 440         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 441
 442         spin_unlock_irq(&dev_priv->irq_lock);
 443         synchronize_irq(dev_priv->drm.irq);
 444
 445         gen9_reset_guc_interrupts(dev_priv);
 446 }
 447
 448 /**
 449  * bdw_update_port_irq - update DE port interrupt
 450  * @dev_priv: driver private
 451  * @interrupt_mask: mask of interrupt bits to update
 452  * @enabled_irq_mask: mask of interrupt bits to enable
 453  */
 454 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 455                                 uint32_t interrupt_mask,
 456                                 uint32_t enabled_irq_mask)
 457 {
 458         uint32_t new_val;
 459         uint32_t old_val;
 460
 461         lockdep_assert_held(&dev_priv->irq_lock);
 462
 463         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 464
 465         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 466                 return;
 467
 468         old_val = I915_READ(GEN8_DE_PORT_IMR);
 469
 470         new_val = old_val;
 471         new_val &= ~interrupt_mask;
 472         new_val |= (~enabled_irq_mask & interrupt_mask);
 473
 474         if (new_val != old_val) {
 475                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 476                 POSTING_READ(GEN8_DE_PORT_IMR);
 477         }
 478 }
 479
 480 /**
 481  * bdw_update_pipe_irq - update DE pipe interrupt
 482  * @dev_priv: driver private
 483  * @pipe: pipe whose interrupt to update
 484  * @interrupt_mask: mask of interrupt bits to update
 485  * @enabled_irq_mask: mask of interrupt bits to enable
 486  */
 487 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 488                          enum pipe pipe,
 489                          uint32_t interrupt_mask,
 490                          uint32_t enabled_irq_mask)
 491 {
 492         uint32_t new_val;
 493
 494         lockdep_assert_held(&dev_priv->irq_lock);
 495
 496         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 497
 498         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 499                 return;
 500
 501         new_val = dev_priv->de_irq_mask[pipe];
 502         new_val &= ~interrupt_mask;
 503         new_val |= (~enabled_irq_mask & interrupt_mask);
 504
 505         if (new_val != dev_priv->de_irq_mask[pipe]) {
 506                 dev_priv->de_irq_mask[pipe] = new_val;
 507                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 508                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 509         }
 510 }
 511
 512 /**
 513  * ibx_display_interrupt_update - update SDEIMR
 514  * @dev_priv: driver private
 515  * @interrupt_mask: mask of interrupt bits to update
 516  * @enabled_irq_mask: mask of interrupt bits to enable
 517  */
 518 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 519                                   uint32_t interrupt_mask,
 520                                   uint32_t enabled_irq_mask)
 521 {
 522         uint32_t sdeimr = I915_READ(SDEIMR);
 523         sdeimr &= ~interrupt_mask;
 524         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 525
 526         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 527
 528         lockdep_assert_held(&dev_priv->irq_lock);
 529
 530         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 531                 return;
 532
 533         I915_WRITE(SDEIMR, sdeimr);
 534         POSTING_READ(SDEIMR);
 535 }
 536
 537 static void
 538 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 539                        u32 enable_mask, u32 status_mask)
 540 {
 541         i915_reg_t reg = PIPESTAT(pipe);
 542         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 543
 544         lockdep_assert_held(&dev_priv->irq_lock);
 545         WARN_ON(!intel_irqs_enabled(dev_priv));
 546
 547         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 548                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 549                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 550                       pipe_name(pipe), enable_mask, status_mask))
 551                 return;
 552
 553         if ((pipestat & enable_mask) == enable_mask)
 554                 return;
 555
 556         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 557
 558         /* Enable the interrupt, clear any pending status */
 559         pipestat |= enable_mask | status_mask;
 560         I915_WRITE(reg, pipestat);
 561         POSTING_READ(reg);
 562 }
 563
 564 static void
 565 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 566                         u32 enable_mask, u32 status_mask)
 567 {
 568         i915_reg_t reg = PIPESTAT(pipe);
 569         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 570
 571         lockdep_assert_held(&dev_priv->irq_lock);
 572         WARN_ON(!intel_irqs_enabled(dev_priv));
 573
 574         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 575                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 576                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 577                       pipe_name(pipe), enable_mask, status_mask))
 578                 return;
 579
 580         if ((pipestat & enable_mask) == 0)
 581                 return;
 582
 583         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 584
 585         pipestat &= ~enable_mask;
 586         I915_WRITE(reg, pipestat);
 587         POSTING_READ(reg);
 588 }
 589
 590 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 591 {
 592         u32 enable_mask = status_mask << 16;
 593
 594         /*
 595          * On pipe A we don't support the PSR interrupt yet,
 596          * on pipe B and C the same bit MBZ.
 597          */
 598         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 599                 return 0;
 600         /*
 601          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 602          * A the same bit is for perf counters which we don't use either.
 603          */
 604         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 605                 return 0;
 606
 607         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 608                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 609                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 610         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 611                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 612         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 613                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 614
 615         return enable_mask;
 616 }
 617
 618 void
 619 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 620                      u32 status_mask)
 621 {
 622         u32 enable_mask;
 623
 624         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 625                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 626                                                            status_mask);
 627         else
 628                 enable_mask = status_mask << 16;
 629         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 630 }
 631
 632 void
 633 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 634                       u32 status_mask)
 635 {
 636         u32 enable_mask;
 637
 638         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 639                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 640                                                            status_mask);
 641         else
 642                 enable_mask = status_mask << 16;
 643         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 644 }
 645
 646 /**
 647  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 648  * @dev_priv: i915 device private
 649  */
 650 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 651 {
 652         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 653                 return;
 654
 655         spin_lock_irq(&dev_priv->irq_lock);
 656
 657         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 658         if (INTEL_GEN(dev_priv) >= 4)
 659                 i915_enable_pipestat(dev_priv, PIPE_A,
 660                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 661
 662         spin_unlock_irq(&dev_priv->irq_lock);
 663 }
 664
 665 /*
 666  * This timing diagram depicts the video signal in and
 667  * around the vertical blanking period.
 668  *
 669  * Assumptions about the fictitious mode used in this example:
 670  *  vblank_start >= 3
 671  *  vsync_start = vblank_start + 1
 672  *  vsync_end = vblank_start + 2
 673  *  vtotal = vblank_start + 3
 674  *
 675  *           start of vblank:
 676  *           latch double buffered registers
 677  *           increment frame counter (ctg+)
 678  *           generate start of vblank interrupt (gen4+)
 679  *           |
 680  *           |          frame start:
 681  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 682  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 683  *           |          |
 684  *           |          |  start of vsync:
 685  *           |          |  generate vsync interrupt
 686  *           |          |  |
 687  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 688  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 689  * ----va---> <-----------------vb--------------------> <--------va-------------
 690  *       |          |       <----vs----->                     |
 691  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 692  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 693  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 694  *       |          |                                         |
 695  *       last visible pixel                                   first visible pixel
 696  *                  |                                         increment frame counter (gen3/4)
 697  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 698  *
 699  * x  = horizontal active
 700  * _  = horizontal blanking
 701  * hs = horizontal sync
 702  * va = vertical active
 703  * vb = vertical blanking
 704  * vs = vertical sync
 705  * vbs = vblank_start (number)
 706  *
 707  * Summary:
 708  * - most events happen at the start of horizontal sync
 709  * - frame start happens at the start of horizontal blank, 1-4 lines
 710  *   (depending on PIPECONF settings) after the start of vblank
 711  * - gen3/4 pixel and frame counter are synchronized with the start
 712  *   of horizontal active on the first line of vertical active
 713  */
 714
 715 /* Called from drm generic code, passed a 'crtc', which
 716  * we use as a pipe index
 717  */
 718 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 719 {
 720         struct drm_i915_private *dev_priv = to_i915(dev);
 721         i915_reg_t high_frame, low_frame;
 722         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 723         const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode;
 724         unsigned long irqflags;
 725
 726         htotal = mode->crtc_htotal;
 727         hsync_start = mode->crtc_hsync_start;
 728         vbl_start = mode->crtc_vblank_start;
 729         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 730                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 731
 732         /* Convert to pixel count */
 733         vbl_start *= htotal;
 734
 735         /* Start of vblank event occurs at start of hsync */
 736         vbl_start -= htotal - hsync_start;
 737
 738         high_frame = PIPEFRAME(pipe);
 739         low_frame = PIPEFRAMEPIXEL(pipe);
 740
 741         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 742
 743         /*
 744          * High & low register fields aren't synchronized, so make sure
 745          * we get a low value that's stable across two reads of the high
 746          * register.
 747          */
 748         do {
 749                 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
 750                 low   = I915_READ_FW(low_frame);
 751                 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
 752         } while (high1 != high2);
 753
 754         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 755
 756         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 757         pixel = low & PIPE_PIXEL_MASK;
 758         low >>= PIPE_FRAME_LOW_SHIFT;
 759
 760         /*
 761          * The frame counter increments at beginning of active.
 762          * Cook up a vblank counter by also checking the pixel
 763          * counter against vblank start.
 764          */
 765         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 766 }
 767
 768 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 769 {
 770         struct drm_i915_private *dev_priv = to_i915(dev);
 771
 772         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 773 }
 774
 775 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 776 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 777 {
 778         struct drm_device *dev = crtc->base.dev;
 779         struct drm_i915_private *dev_priv = to_i915(dev);
 780         const struct drm_display_mode *mode;
 781         struct drm_vblank_crtc *vblank;
 782         enum pipe pipe = crtc->pipe;
 783         int position, vtotal;
 784
 785         if (!crtc->active)
 786                 return -1;
 787
 788         vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 789         mode = &vblank->hwmode;
 790
 791         vtotal = mode->crtc_vtotal;
 792         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 793                 vtotal /= 2;
 794
 795         if (IS_GEN2(dev_priv))
 796                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 797         else
 798                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 799
 800         /*
 801          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 802          * read it just before the start of vblank.  So try it again
 803          * so we don't accidentally end up spanning a vblank frame
 804          * increment, causing the pipe_update_end() code to squak at us.
 805          *
 806          * The nature of this problem means we can't simply check the ISR
 807          * bit and return the vblank start value; nor can we use the scanline
 808          * debug register in the transcoder as it appears to have the same
 809          * problem.  We may need to extend this to include other platforms,
 810          * but so far testing only shows the problem on HSW.
 811          */
 812         if (HAS_DDI(dev_priv) && !position) {
 813                 int i, temp;
 814
 815                 for (i = 0; i < 100; i++) {
 816                         udelay(1);
 817                         temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 818                         if (temp != position) {
 819                                 position = temp;
 820                                 break;
 821                         }
 822                 }
 823         }
 824
 825         /*
 826          * See update_scanline_offset() for the details on the
 827          * scanline_offset adjustment.
 828          */
 829         return (position + crtc->scanline_offset) % vtotal;
 830 }
 831
 832 static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 833                                      bool in_vblank_irq, int *vpos, int *hpos,
 834                                      ktime_t *stime, ktime_t *etime,
 835                                      const struct drm_display_mode *mode)
 836 {
 837         struct drm_i915_private *dev_priv = to_i915(dev);
 838         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 839                                                                 pipe);
 840         int position;
 841         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 842         unsigned long irqflags;
 843
 844         if (WARN_ON(!mode->crtc_clock)) {
 845                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 846                                  "pipe %c\n", pipe_name(pipe));
 847                 return false;
 848         }
 849
 850         htotal = mode->crtc_htotal;
 851         hsync_start = mode->crtc_hsync_start;
 852         vtotal = mode->crtc_vtotal;
 853         vbl_start = mode->crtc_vblank_start;
 854         vbl_end = mode->crtc_vblank_end;
 855
 856         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 857                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 858                 vbl_end /= 2;
 859                 vtotal /= 2;
 860         }
 861
 862         /*
 863          * Lock uncore.lock, as we will do multiple timing critical raw
 864          * register reads, potentially with preemption disabled, so the
 865          * following code must not block on uncore.lock.
 866          */
 867         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 868
 869         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 870
 871         /* Get optional system timestamp before query. */
 872         if (stime)
 873                 *stime = ktime_get();
 874
 875         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 876                 /* No obvious pixelcount register. Only query vertical
 877                  * scanout position from Display scan line register.
 878                  */
 879                 position = __intel_get_crtc_scanline(intel_crtc);
 880         } else {
 881                 /* Have access to pixelcount since start of frame.
 882                  * We can split this into vertical and horizontal
 883                  * scanout position.
 884                  */
 885                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 886
 887                 /* convert to pixel counts */
 888                 vbl_start *= htotal;
 889                 vbl_end *= htotal;
 890                 vtotal *= htotal;
 891
 892                 /*
 893                  * In interlaced modes, the pixel counter counts all pixels,
 894                  * so one field will have htotal more pixels. In order to avoid
 895                  * the reported position from jumping backwards when the pixel
 896                  * counter is beyond the length of the shorter field, just
 897                  * clamp the position the length of the shorter field. This
 898                  * matches how the scanline counter based position works since
 899                  * the scanline counter doesn't count the two half lines.
 900                  */
 901                 if (position >= vtotal)
 902                         position = vtotal - 1;
 903
 904                 /*
 905                  * Start of vblank interrupt is triggered at start of hsync,
 906                  * just prior to the first active line of vblank. However we
 907                  * consider lines to start at the leading edge of horizontal
 908                  * active. So, should we get here before we've crossed into
 909                  * the horizontal active of the first line in vblank, we would
 910                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 911                  * always add htotal-hsync_start to the current pixel position.
 912                  */
 913                 position = (position + htotal - hsync_start) % vtotal;
 914         }
 915
 916         /* Get optional system timestamp after query. */
 917         if (etime)
 918                 *etime = ktime_get();
 919
 920         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 921
 922         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 923
 924         /*
 925          * While in vblank, position will be negative
 926          * counting up towards 0 at vbl_end. And outside
 927          * vblank, position will be positive counting
 928          * up since vbl_end.
 929          */
 930         if (position >= vbl_start)
 931                 position -= vbl_end;
 932         else
 933                 position += vtotal - vbl_end;
 934
 935         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 936                 *vpos = position;
 937                 *hpos = 0;
 938         } else {
 939                 *vpos = position / htotal;
 940                 *hpos = position - (*vpos * htotal);
 941         }
 942
 943         return true;
 944 }
 945
 946 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 947 {
 948         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 949         unsigned long irqflags;
 950         int position;
 951
 952         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 953         position = __intel_get_crtc_scanline(crtc);
 954         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 955
 956         return position;
 957 }
 958
 959 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 960 {
 961         u32 busy_up, busy_down, max_avg, min_avg;
 962         u8 new_delay;
 963
 964         spin_lock(&mchdev_lock);
 965
 966         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 967
 968         new_delay = dev_priv->ips.cur_delay;
 969
 970         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 971         busy_up = I915_READ(RCPREVBSYTUPAVG);
 972         busy_down = I915_READ(RCPREVBSYTDNAVG);
 973         max_avg = I915_READ(RCBMAXAVG);
 974         min_avg = I915_READ(RCBMINAVG);
 975
 976         /* Handle RCS change request from hw */
 977         if (busy_up > max_avg) {
 978                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 979                         new_delay = dev_priv->ips.cur_delay - 1;
 980                 if (new_delay < dev_priv->ips.max_delay)
 981                         new_delay = dev_priv->ips.max_delay;
 982         } else if (busy_down < min_avg) {
 983                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 984                         new_delay = dev_priv->ips.cur_delay + 1;
 985                 if (new_delay > dev_priv->ips.min_delay)
 986                         new_delay = dev_priv->ips.min_delay;
 987         }
 988
 989         if (ironlake_set_drps(dev_priv, new_delay))
 990                 dev_priv->ips.cur_delay = new_delay;
 991
 992         spin_unlock(&mchdev_lock);
 993
 994         return;
 995 }
 996
 997 static void notify_ring(struct intel_engine_cs *engine)
 998 {
 999         struct drm_i915_gem_request *rq = NULL;
1000         struct intel_wait *wait;
1001
1002         atomic_inc(&engine->irq_count);
1003         set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
1004
1005         spin_lock(&engine->breadcrumbs.irq_lock);
1006         wait = engine->breadcrumbs.irq_wait;
1007         if (wait) {
1008                 /* We use a callback from the dma-fence to submit
1009                  * requests after waiting on our own requests. To
1010                  * ensure minimum delay in queuing the next request to
1011                  * hardware, signal the fence now rather than wait for
1012                  * the signaler to be woken up. We still wake up the
1013                  * waiter in order to handle the irq-seqno coherency
1014                  * issues (we may receive the interrupt before the
1015                  * seqno is written, see __i915_request_irq_complete())
1016                  * and to handle coalescing of multiple seqno updates
1017                  * and many waiters.
1018                  */
1019                 if (i915_seqno_passed(intel_engine_get_seqno(engine),
1020                                       wait->seqno) &&
1021                     !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1022                               &wait->request->fence.flags))
1023                         rq = i915_gem_request_get(wait->request);
1024
1025                 wake_up_process(wait->tsk);
1026         } else {
1027                 __intel_engine_disarm_breadcrumbs(engine);
1028         }
1029         spin_unlock(&engine->breadcrumbs.irq_lock);
1030
1031         if (rq) {
1032                 dma_fence_signal(&rq->fence);
1033                 i915_gem_request_put(rq);
1034         }
1035
1036         trace_intel_engine_notify(engine, wait);
1037 }
1038
1039 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1040                         struct intel_rps_ei *ei)
1041 {
1042         ei->ktime = ktime_get_raw();
1043         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1044         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1045 }
1046
1047 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1048 {
1049         memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
1050 }
1051
1052 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1053 {
1054         const struct intel_rps_ei *prev = &dev_priv->rps.ei;
1055         struct intel_rps_ei now;
1056         u32 events = 0;
1057
1058         if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1059                 return 0;
1060
1061         vlv_c0_read(dev_priv, &now);
1062
1063         if (prev->ktime) {
1064                 u64 time, c0;
1065                 u32 render, media;
1066
1067                 time = ktime_us_delta(now.ktime, prev->ktime);
1068
1069                 time *= dev_priv->czclk_freq;
1070
1071                 /* Workload can be split between render + media,
1072                  * e.g. SwapBuffers being blitted in X after being rendered in
1073                  * mesa. To account for this we need to combine both engines
1074                  * into our activity counter.
1075                  */
1076                 render = now.render_c0 - prev->render_c0;
1077                 media = now.media_c0 - prev->media_c0;
1078                 c0 = max(render, media);
1079                 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1080
1081                 if (c0 > time * dev_priv->rps.up_threshold)
1082                         events = GEN6_PM_RP_UP_THRESHOLD;
1083                 else if (c0 < time * dev_priv->rps.down_threshold)
1084                         events = GEN6_PM_RP_DOWN_THRESHOLD;
1085         }
1086
1087         dev_priv->rps.ei = now;
1088         return events;
1089 }
1090
1091 static void gen6_pm_rps_work(struct work_struct *work)
1092 {
1093         struct drm_i915_private *dev_priv =
1094                 container_of(work, struct drm_i915_private, rps.work);
1095         bool client_boost = false;
1096         int new_delay, adj, min, max;
1097         u32 pm_iir = 0;
1098
1099         spin_lock_irq(&dev_priv->irq_lock);
1100         if (dev_priv->rps.interrupts_enabled) {
1101                 pm_iir = fetch_and_zero(&dev_priv->rps.pm_iir);
1102                 client_boost = atomic_read(&dev_priv->rps.num_waiters);
1103         }
1104         spin_unlock_irq(&dev_priv->irq_lock);
1105
1106         /* Make sure we didn't queue anything we're not going to process. */
1107         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1108         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1109                 goto out;
1110
1111         mutex_lock(&dev_priv->rps.hw_lock);
1112
1113         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1114
1115         adj = dev_priv->rps.last_adj;
1116         new_delay = dev_priv->rps.cur_freq;
1117         min = dev_priv->rps.min_freq_softlimit;
1118         max = dev_priv->rps.max_freq_softlimit;
1119         if (client_boost)
1120                 max = dev_priv->rps.max_freq;
1121         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1122                 new_delay = dev_priv->rps.boost_freq;
1123                 adj = 0;
1124         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1125                 if (adj > 0)
1126                         adj *= 2;
1127                 else /* CHV needs even encode values */
1128                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1129
1130                 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1131                         adj = 0;
1132         } else if (client_boost) {
1133                 adj = 0;
1134         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1135                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1136                         new_delay = dev_priv->rps.efficient_freq;
1137                 else if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1138                         new_delay = dev_priv->rps.min_freq_softlimit;
1139                 adj = 0;
1140         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1141                 if (adj < 0)
1142                         adj *= 2;
1143                 else /* CHV needs even encode values */
1144                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1145
1146                 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1147                         adj = 0;
1148         } else { /* unknown event */
1149                 adj = 0;
1150         }
1151
1152         dev_priv->rps.last_adj = adj;
1153
1154         /* sysfs frequency interfaces may have snuck in while servicing the
1155          * interrupt
1156          */
1157         new_delay += adj;
1158         new_delay = clamp_t(int, new_delay, min, max);
1159
1160         if (intel_set_rps(dev_priv, new_delay)) {
1161                 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1162                 dev_priv->rps.last_adj = 0;
1163         }
1164
1165         mutex_unlock(&dev_priv->rps.hw_lock);
1166
1167 out:
1168         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1169         spin_lock_irq(&dev_priv->irq_lock);
1170         if (dev_priv->rps.interrupts_enabled)
1171                 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1172         spin_unlock_irq(&dev_priv->irq_lock);
1173 }
1174
1175
1176 /**
1177  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1178  * occurred.
1179  * @work: workqueue struct
1180  *
1181  * Doesn't actually do anything except notify userspace. As a consequence of
1182  * this event, userspace should try to remap the bad rows since statistically
1183  * it is likely the same row is more likely to go bad again.
1184  */
1185 static void ivybridge_parity_work(struct work_struct *work)
1186 {
1187         struct drm_i915_private *dev_priv =
1188                 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1189         u32 error_status, row, bank, subbank;
1190         char *parity_event[6];
1191         uint32_t misccpctl;
1192         uint8_t slice = 0;
1193
1194         /* We must turn off DOP level clock gating to access the L3 registers.
1195          * In order to prevent a get/put style interface, acquire struct mutex
1196          * any time we access those registers.
1197          */
1198         mutex_lock(&dev_priv->drm.struct_mutex);
1199
1200         /* If we've screwed up tracking, just let the interrupt fire again */
1201         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1202                 goto out;
1203
1204         misccpctl = I915_READ(GEN7_MISCCPCTL);
1205         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1206         POSTING_READ(GEN7_MISCCPCTL);
1207
1208         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1209                 i915_reg_t reg;
1210
1211                 slice--;
1212                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1213                         break;
1214
1215                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1216
1217                 reg = GEN7_L3CDERRST1(slice);
1218
1219                 error_status = I915_READ(reg);
1220                 row = GEN7_PARITY_ERROR_ROW(error_status);
1221                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1222                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1223
1224                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1225                 POSTING_READ(reg);
1226
1227                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1228                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1229                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1230                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1231                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1232                 parity_event[5] = NULL;
1233
1234                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1235                                    KOBJ_CHANGE, parity_event);
1236
1237                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1238                           slice, row, bank, subbank);
1239
1240                 kfree(parity_event[4]);
1241                 kfree(parity_event[3]);
1242                 kfree(parity_event[2]);
1243                 kfree(parity_event[1]);
1244         }
1245
1246         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1247
1248 out:
1249         WARN_ON(dev_priv->l3_parity.which_slice);
1250         spin_lock_irq(&dev_priv->irq_lock);
1251         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1252         spin_unlock_irq(&dev_priv->irq_lock);
1253
1254         mutex_unlock(&dev_priv->drm.struct_mutex);
1255 }
1256
1257 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1258                                                u32 iir)
1259 {
1260         if (!HAS_L3_DPF(dev_priv))
1261                 return;
1262
1263         spin_lock(&dev_priv->irq_lock);
1264         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1265         spin_unlock(&dev_priv->irq_lock);
1266
1267         iir &= GT_PARITY_ERROR(dev_priv);
1268         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1269                 dev_priv->l3_parity.which_slice |= 1 << 1;
1270
1271         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1272                 dev_priv->l3_parity.which_slice |= 1 << 0;
1273
1274         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1275 }
1276
1277 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1278                                u32 gt_iir)
1279 {
1280         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1281                 notify_ring(dev_priv->engine[RCS]);
1282         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1283                 notify_ring(dev_priv->engine[VCS]);
1284 }
1285
1286 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1287                                u32 gt_iir)
1288 {
1289         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1290                 notify_ring(dev_priv->engine[RCS]);
1291         if (gt_iir & GT_BSD_USER_INTERRUPT)
1292                 notify_ring(dev_priv->engine[VCS]);
1293         if (gt_iir & GT_BLT_USER_INTERRUPT)
1294                 notify_ring(dev_priv->engine[BCS]);
1295
1296         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1297                       GT_BSD_CS_ERROR_INTERRUPT |
1298                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1299                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1300
1301         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1302                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1303 }
1304
1305 static void
1306 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1307 {
1308         bool tasklet = false;
1309
1310         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
1311                 if (port_count(&engine->execlist_port[0])) {
1312                         __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1313                         tasklet = true;
1314                 }
1315         }
1316
1317         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
1318                 notify_ring(engine);
1319                 tasklet |= i915.enable_guc_submission;
1320         }
1321
1322         if (tasklet)
1323                 tasklet_hi_schedule(&engine->irq_tasklet);
1324 }
1325
1326 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1327                                    u32 master_ctl,
1328                                    u32 gt_iir[4])
1329 {
1330         irqreturn_t ret = IRQ_NONE;
1331
1332         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1333                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1334                 if (gt_iir[0]) {
1335                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1336                         ret = IRQ_HANDLED;
1337                 } else
1338                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1339         }
1340
1341         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1342                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1343                 if (gt_iir[1]) {
1344                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1345                         ret = IRQ_HANDLED;
1346                 } else
1347                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1348         }
1349
1350         if (master_ctl & GEN8_GT_VECS_IRQ) {
1351                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1352                 if (gt_iir[3]) {
1353                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1354                         ret = IRQ_HANDLED;
1355                 } else
1356                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1357         }
1358
1359         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1360                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1361                 if (gt_iir[2] & (dev_priv->pm_rps_events |
1362                                  dev_priv->pm_guc_events)) {
1363                         I915_WRITE_FW(GEN8_GT_IIR(2),
1364                                       gt_iir[2] & (dev_priv->pm_rps_events |
1365                                                    dev_priv->pm_guc_events));
1366                         ret = IRQ_HANDLED;
1367                 } else
1368                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1369         }
1370
1371         return ret;
1372 }
1373
1374 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1375                                 u32 gt_iir[4])
1376 {
1377         if (gt_iir[0]) {
1378                 gen8_cs_irq_handler(dev_priv->engine[RCS],
1379                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1380                 gen8_cs_irq_handler(dev_priv->engine[BCS],
1381                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1382         }
1383
1384         if (gt_iir[1]) {
1385                 gen8_cs_irq_handler(dev_priv->engine[VCS],
1386                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1387                 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1388                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1389         }
1390
1391         if (gt_iir[3])
1392                 gen8_cs_irq_handler(dev_priv->engine[VECS],
1393                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1394
1395         if (gt_iir[2] & dev_priv->pm_rps_events)
1396                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1397
1398         if (gt_iir[2] & dev_priv->pm_guc_events)
1399                 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1400 }
1401
1402 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1403 {
1404         switch (port) {
1405         case PORT_A:
1406                 return val & PORTA_HOTPLUG_LONG_DETECT;
1407         case PORT_B:
1408                 return val & PORTB_HOTPLUG_LONG_DETECT;
1409         case PORT_C:
1410                 return val & PORTC_HOTPLUG_LONG_DETECT;
1411         default:
1412                 return false;
1413         }
1414 }
1415
1416 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1417 {
1418         switch (port) {
1419         case PORT_E:
1420                 return val & PORTE_HOTPLUG_LONG_DETECT;
1421         default:
1422                 return false;
1423         }
1424 }
1425
1426 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1427 {
1428         switch (port) {
1429         case PORT_A:
1430                 return val & PORTA_HOTPLUG_LONG_DETECT;
1431         case PORT_B:
1432                 return val & PORTB_HOTPLUG_LONG_DETECT;
1433         case PORT_C:
1434                 return val & PORTC_HOTPLUG_LONG_DETECT;
1435         case PORT_D:
1436                 return val & PORTD_HOTPLUG_LONG_DETECT;
1437         default:
1438                 return false;
1439         }
1440 }
1441
1442 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1443 {
1444         switch (port) {
1445         case PORT_A:
1446                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1447         default:
1448                 return false;
1449         }
1450 }
1451
1452 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1453 {
1454         switch (port) {
1455         case PORT_B:
1456                 return val & PORTB_HOTPLUG_LONG_DETECT;
1457         case PORT_C:
1458                 return val & PORTC_HOTPLUG_LONG_DETECT;
1459         case PORT_D:
1460                 return val & PORTD_HOTPLUG_LONG_DETECT;
1461         default:
1462                 return false;
1463         }
1464 }
1465
1466 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1467 {
1468         switch (port) {
1469         case PORT_B:
1470                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1471         case PORT_C:
1472                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1473         case PORT_D:
1474                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1475         default:
1476                 return false;
1477         }
1478 }
1479
1480 /*
1481  * Get a bit mask of pins that have triggered, and which ones may be long.
1482  * This can be called multiple times with the same masks to accumulate
1483  * hotplug detection results from several registers.
1484  *
1485  * Note that the caller is expected to zero out the masks initially.
1486  */
1487 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1488                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1489                              const u32 hpd[HPD_NUM_PINS],
1490                              bool long_pulse_detect(enum port port, u32 val))
1491 {
1492         enum port port;
1493         int i;
1494
1495         for_each_hpd_pin(i) {
1496                 if ((hpd[i] & hotplug_trigger) == 0)
1497                         continue;
1498
1499                 *pin_mask |= BIT(i);
1500
1501                 port = intel_hpd_pin_to_port(i);
1502                 if (port == PORT_NONE)
1503                         continue;
1504
1505                 if (long_pulse_detect(port, dig_hotplug_reg))
1506                         *long_mask |= BIT(i);
1507         }
1508
1509         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1510                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1511
1512 }
1513
1514 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1515 {
1516         wake_up_all(&dev_priv->gmbus_wait_queue);
1517 }
1518
1519 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1520 {
1521         wake_up_all(&dev_priv->gmbus_wait_queue);
1522 }
1523
1524 #if defined(CONFIG_DEBUG_FS)
1525 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1526                                          enum pipe pipe,
1527                                          uint32_t crc0, uint32_t crc1,
1528                                          uint32_t crc2, uint32_t crc3,
1529                                          uint32_t crc4)
1530 {
1531         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1532         struct intel_pipe_crc_entry *entry;
1533         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1534         struct drm_driver *driver = dev_priv->drm.driver;
1535         uint32_t crcs[5];
1536         int head, tail;
1537
1538         spin_lock(&pipe_crc->lock);
1539         if (pipe_crc->source) {
1540                 if (!pipe_crc->entries) {
1541                         spin_unlock(&pipe_crc->lock);
1542                         DRM_DEBUG_KMS("spurious interrupt\n");
1543                         return;
1544                 }
1545
1546                 head = pipe_crc->head;
1547                 tail = pipe_crc->tail;
1548
1549                 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1550                         spin_unlock(&pipe_crc->lock);
1551                         DRM_ERROR("CRC buffer overflowing\n");
1552                         return;
1553                 }
1554
1555                 entry = &pipe_crc->entries[head];
1556
1557                 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1558                 entry->crc[0] = crc0;
1559                 entry->crc[1] = crc1;
1560                 entry->crc[2] = crc2;
1561                 entry->crc[3] = crc3;
1562                 entry->crc[4] = crc4;
1563
1564                 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1565                 pipe_crc->head = head;
1566
1567                 spin_unlock(&pipe_crc->lock);
1568
1569                 wake_up_interruptible(&pipe_crc->wq);
1570         } else {
1571                 /*
1572                  * For some not yet identified reason, the first CRC is
1573                  * bonkers. So let's just wait for the next vblank and read
1574                  * out the buggy result.
1575                  *
1576                  * On CHV sometimes the second CRC is bonkers as well, so
1577                  * don't trust that one either.
1578                  */
1579                 if (pipe_crc->skipped == 0 ||
1580                     (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1581                         pipe_crc->skipped++;
1582                         spin_unlock(&pipe_crc->lock);
1583                         return;
1584                 }
1585                 spin_unlock(&pipe_crc->lock);
1586                 crcs[0] = crc0;
1587                 crcs[1] = crc1;
1588                 crcs[2] = crc2;
1589                 crcs[3] = crc3;
1590                 crcs[4] = crc4;
1591                 drm_crtc_add_crc_entry(&crtc->base, true,
1592                                        drm_crtc_accurate_vblank_count(&crtc->base),
1593                                        crcs);
1594         }
1595 }
1596 #else
1597 static inline void
1598 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1599                              enum pipe pipe,
1600                              uint32_t crc0, uint32_t crc1,
1601                              uint32_t crc2, uint32_t crc3,
1602                              uint32_t crc4) {}
1603 #endif
1604
1605
1606 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1607                                      enum pipe pipe)
1608 {
1609         display_pipe_crc_irq_handler(dev_priv, pipe,
1610                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1611                                      0, 0, 0, 0);
1612 }
1613
1614 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1615                                      enum pipe pipe)
1616 {
1617         display_pipe_crc_irq_handler(dev_priv, pipe,
1618                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1619                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1620                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1621                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1622                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1623 }
1624
1625 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1626                                       enum pipe pipe)
1627 {
1628         uint32_t res1, res2;
1629
1630         if (INTEL_GEN(dev_priv) >= 3)
1631                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1632         else
1633                 res1 = 0;
1634
1635         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1636                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1637         else
1638                 res2 = 0;
1639
1640         display_pipe_crc_irq_handler(dev_priv, pipe,
1641                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1642                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1643                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1644                                      res1, res2);
1645 }
1646
1647 /* The RPS events need forcewake, so we add them to a work queue and mask their
1648  * IMR bits until the work is done. Other interrupts can be processed without
1649  * the work queue. */
1650 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1651 {
1652         if (pm_iir & dev_priv->pm_rps_events) {
1653                 spin_lock(&dev_priv->irq_lock);
1654                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1655                 if (dev_priv->rps.interrupts_enabled) {
1656                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1657                         schedule_work(&dev_priv->rps.work);
1658                 }
1659                 spin_unlock(&dev_priv->irq_lock);
1660         }
1661
1662         if (INTEL_GEN(dev_priv) >= 8)
1663                 return;
1664
1665         if (HAS_VEBOX(dev_priv)) {
1666                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1667                         notify_ring(dev_priv->engine[VECS]);
1668
1669                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1670                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1671         }
1672 }
1673
1674 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1675 {
1676         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1677                 /* Sample the log buffer flush related bits & clear them out now
1678                  * itself from the message identity register to minimize the
1679                  * probability of losing a flush interrupt, when there are back
1680                  * to back flush interrupts.
1681                  * There can be a new flush interrupt, for different log buffer
1682                  * type (like for ISR), whilst Host is handling one (for DPC).
1683                  * Since same bit is used in message register for ISR & DPC, it
1684                  * could happen that GuC sets the bit for 2nd interrupt but Host
1685                  * clears out the bit on handling the 1st interrupt.
1686                  */
1687                 u32 msg, flush;
1688
1689                 msg = I915_READ(SOFT_SCRATCH(15));
1690                 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1691                                INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1692                 if (flush) {
1693                         /* Clear the message bits that are handled */
1694                         I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1695
1696                         /* Handle flush interrupt in bottom half */
1697                         queue_work(dev_priv->guc.log.runtime.flush_wq,
1698                                    &dev_priv->guc.log.runtime.flush_work);
1699
1700                         dev_priv->guc.log.flush_interrupt_count++;
1701                 } else {
1702                         /* Not clearing of unhandled event bits won't result in
1703                          * re-triggering of the interrupt.
1704                          */
1705                 }
1706         }
1707 }
1708
1709 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1710                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1711 {
1712         int pipe;
1713
1714         spin_lock(&dev_priv->irq_lock);
1715
1716         if (!dev_priv->display_irqs_enabled) {
1717                 spin_unlock(&dev_priv->irq_lock);
1718                 return;
1719         }
1720
1721         for_each_pipe(dev_priv, pipe) {
1722                 i915_reg_t reg;
1723                 u32 mask, iir_bit = 0;
1724
1725                 /*
1726                  * PIPESTAT bits get signalled even when the interrupt is
1727                  * disabled with the mask bits, and some of the status bits do
1728                  * not generate interrupts at all (like the underrun bit). Hence
1729                  * we need to be careful that we only handle what we want to
1730                  * handle.
1731                  */
1732
1733                 /* fifo underruns are filterered in the underrun handler. */
1734                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1735
1736                 switch (pipe) {
1737                 case PIPE_A:
1738                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1739                         break;
1740                 case PIPE_B:
1741                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1742                         break;
1743                 case PIPE_C:
1744                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1745                         break;
1746                 }
1747                 if (iir & iir_bit)
1748                         mask |= dev_priv->pipestat_irq_mask[pipe];
1749
1750                 if (!mask)
1751                         continue;
1752
1753                 reg = PIPESTAT(pipe);
1754                 mask |= PIPESTAT_INT_ENABLE_MASK;
1755                 pipe_stats[pipe] = I915_READ(reg) & mask;
1756
1757                 /*
1758                  * Clear the PIPE*STAT regs before the IIR
1759                  */
1760                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1761                                         PIPESTAT_INT_STATUS_MASK))
1762                         I915_WRITE(reg, pipe_stats[pipe]);
1763         }
1764         spin_unlock(&dev_priv->irq_lock);
1765 }
1766
1767 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1768                                             u32 pipe_stats[I915_MAX_PIPES])
1769 {
1770         enum pipe pipe;
1771
1772         for_each_pipe(dev_priv, pipe) {
1773                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1774                         drm_handle_vblank(&dev_priv->drm, pipe);
1775
1776                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1777                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1778
1779                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1780                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1781         }
1782
1783         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1784                 gmbus_irq_handler(dev_priv);
1785 }
1786
1787 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1788 {
1789         u32 hotplug_status = 0, hotplug_status_mask;
1790         int i;
1791
1792         if (IS_G4X(dev_priv) ||
1793             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1794                 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1795                         DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1796         else
1797                 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1798
1799         /*
1800          * We absolutely have to clear all the pending interrupt
1801          * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1802          * interrupt bit won't have an edge, and the i965/g4x
1803          * edge triggered IIR will not notice that an interrupt
1804          * is still pending. We can't use PORT_HOTPLUG_EN to
1805          * guarantee the edge as the act of toggling the enable
1806          * bits can itself generate a new hotplug interrupt :(
1807          */
1808         for (i = 0; i < 10; i++) {
1809                 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1810
1811                 if (tmp == 0)
1812                         return hotplug_status;
1813
1814                 hotplug_status |= tmp;
1815                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1816         }
1817
1818         WARN_ONCE(1,
1819                   "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1820                   I915_READ(PORT_HOTPLUG_STAT));
1821
1822         return hotplug_status;
1823 }
1824
1825 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1826                                  u32 hotplug_status)
1827 {
1828         u32 pin_mask = 0, long_mask = 0;
1829
1830         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1831             IS_CHERRYVIEW(dev_priv)) {
1832                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1833
1834                 if (hotplug_trigger) {
1835                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1836                                            hotplug_trigger, hpd_status_g4x,
1837                                            i9xx_port_hotplug_long_detect);
1838
1839                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1840                 }
1841
1842                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1843                         dp_aux_irq_handler(dev_priv);
1844         } else {
1845                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1846
1847                 if (hotplug_trigger) {
1848                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1849                                            hotplug_trigger, hpd_status_i915,
1850                                            i9xx_port_hotplug_long_detect);
1851                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1852                 }
1853         }
1854 }
1855
1856 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1857 {
1858         struct drm_device *dev = arg;
1859         struct drm_i915_private *dev_priv = to_i915(dev);
1860         irqreturn_t ret = IRQ_NONE;
1861
1862         if (!intel_irqs_enabled(dev_priv))
1863                 return IRQ_NONE;
1864
1865         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1866         disable_rpm_wakeref_asserts(dev_priv);
1867
1868         do {
1869                 u32 iir, gt_iir, pm_iir;
1870                 u32 pipe_stats[I915_MAX_PIPES] = {};
1871                 u32 hotplug_status = 0;
1872                 u32 ier = 0;
1873
1874                 gt_iir = I915_READ(GTIIR);
1875                 pm_iir = I915_READ(GEN6_PMIIR);
1876                 iir = I915_READ(VLV_IIR);
1877
1878                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1879                         break;
1880
1881                 ret = IRQ_HANDLED;
1882
1883                 /*
1884                  * Theory on interrupt generation, based on empirical evidence:
1885                  *
1886                  * x = ((VLV_IIR & VLV_IER) ||
1887                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1888                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1889                  *
1890                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1891                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1892                  * guarantee the CPU interrupt will be raised again even if we
1893                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1894                  * bits this time around.
1895                  */
1896                 I915_WRITE(VLV_MASTER_IER, 0);
1897                 ier = I915_READ(VLV_IER);
1898                 I915_WRITE(VLV_IER, 0);
1899
1900                 if (gt_iir)
1901                         I915_WRITE(GTIIR, gt_iir);
1902                 if (pm_iir)
1903                         I915_WRITE(GEN6_PMIIR, pm_iir);
1904
1905                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1906                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1907
1908                 /* Call regardless, as some status bits might not be
1909                  * signalled in iir */
1910                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1911
1912                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1913                            I915_LPE_PIPE_B_INTERRUPT))
1914                         intel_lpe_audio_irq_handler(dev_priv);
1915
1916                 /*
1917                  * VLV_IIR is single buffered, and reflects the level
1918                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1919                  */
1920                 if (iir)
1921                         I915_WRITE(VLV_IIR, iir);
1922
1923                 I915_WRITE(VLV_IER, ier);
1924                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1925                 POSTING_READ(VLV_MASTER_IER);
1926
1927                 if (gt_iir)
1928                         snb_gt_irq_handler(dev_priv, gt_iir);
1929                 if (pm_iir)
1930                         gen6_rps_irq_handler(dev_priv, pm_iir);
1931
1932                 if (hotplug_status)
1933                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1934
1935                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1936         } while (0);
1937
1938         enable_rpm_wakeref_asserts(dev_priv);
1939
1940         return ret;
1941 }
1942
1943 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1944 {
1945         struct drm_device *dev = arg;
1946         struct drm_i915_private *dev_priv = to_i915(dev);
1947         irqreturn_t ret = IRQ_NONE;
1948
1949         if (!intel_irqs_enabled(dev_priv))
1950                 return IRQ_NONE;
1951
1952         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1953         disable_rpm_wakeref_asserts(dev_priv);
1954
1955         do {
1956                 u32 master_ctl, iir;
1957                 u32 gt_iir[4] = {};
1958                 u32 pipe_stats[I915_MAX_PIPES] = {};
1959                 u32 hotplug_status = 0;
1960                 u32 ier = 0;
1961
1962                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1963                 iir = I915_READ(VLV_IIR);
1964
1965                 if (master_ctl == 0 && iir == 0)
1966                         break;
1967
1968                 ret = IRQ_HANDLED;
1969
1970                 /*
1971                  * Theory on interrupt generation, based on empirical evidence:
1972                  *
1973                  * x = ((VLV_IIR & VLV_IER) ||
1974                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1975                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1976                  *
1977                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1978                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1979                  * guarantee the CPU interrupt will be raised again even if we
1980                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1981                  * bits this time around.
1982                  */
1983                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1984                 ier = I915_READ(VLV_IER);
1985                 I915_WRITE(VLV_IER, 0);
1986
1987                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1988
1989                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1990                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1991
1992                 /* Call regardless, as some status bits might not be
1993                  * signalled in iir */
1994                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1995
1996                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1997                            I915_LPE_PIPE_B_INTERRUPT |
1998                            I915_LPE_PIPE_C_INTERRUPT))
1999                         intel_lpe_audio_irq_handler(dev_priv);
2000
2001                 /*
2002                  * VLV_IIR is single buffered, and reflects the level
2003                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2004                  */
2005                 if (iir)
2006                         I915_WRITE(VLV_IIR, iir);
2007
2008                 I915_WRITE(VLV_IER, ier);
2009                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2010                 POSTING_READ(GEN8_MASTER_IRQ);
2011
2012                 gen8_gt_irq_handler(dev_priv, gt_iir);
2013
2014                 if (hotplug_status)
2015                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2016
2017                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2018         } while (0);
2019
2020         enable_rpm_wakeref_asserts(dev_priv);
2021
2022         return ret;
2023 }
2024
2025 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2026                                 u32 hotplug_trigger,
2027                                 const u32 hpd[HPD_NUM_PINS])
2028 {
2029         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2030
2031         /*
2032          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2033          * unless we touch the hotplug register, even if hotplug_trigger is
2034          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2035          * errors.
2036          */
2037         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2038         if (!hotplug_trigger) {
2039                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2040                         PORTD_HOTPLUG_STATUS_MASK |
2041                         PORTC_HOTPLUG_STATUS_MASK |
2042                         PORTB_HOTPLUG_STATUS_MASK;
2043                 dig_hotplug_reg &= ~mask;
2044         }
2045
2046         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2047         if (!hotplug_trigger)
2048                 return;
2049
2050         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2051                            dig_hotplug_reg, hpd,
2052                            pch_port_hotplug_long_detect);
2053
2054         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2055 }
2056
2057 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2058 {
2059         int pipe;
2060         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2061
2062         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2063
2064         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2065                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2066                                SDE_AUDIO_POWER_SHIFT);
2067                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2068                                  port_name(port));
2069         }
2070
2071         if (pch_iir & SDE_AUX_MASK)
2072                 dp_aux_irq_handler(dev_priv);
2073
2074         if (pch_iir & SDE_GMBUS)
2075                 gmbus_irq_handler(dev_priv);
2076
2077         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2078                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2079
2080         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2081                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2082
2083         if (pch_iir & SDE_POISON)
2084                 DRM_ERROR("PCH poison interrupt\n");
2085
2086         if (pch_iir & SDE_FDI_MASK)
2087                 for_each_pipe(dev_priv, pipe)
2088                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2089                                          pipe_name(pipe),
2090                                          I915_READ(FDI_RX_IIR(pipe)));
2091
2092         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2093                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2094
2095         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2096                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2097
2098         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2099                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2100
2101         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2102                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2103 }
2104
2105 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2106 {
2107         u32 err_int = I915_READ(GEN7_ERR_INT);
2108         enum pipe pipe;
2109
2110         if (err_int & ERR_INT_POISON)
2111                 DRM_ERROR("Poison interrupt\n");
2112
2113         for_each_pipe(dev_priv, pipe) {
2114                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2115                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2116
2117                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2118                         if (IS_IVYBRIDGE(dev_priv))
2119                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2120                         else
2121                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2122                 }
2123         }
2124
2125         I915_WRITE(GEN7_ERR_INT, err_int);
2126 }
2127
2128 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2129 {
2130         u32 serr_int = I915_READ(SERR_INT);
2131
2132         if (serr_int & SERR_INT_POISON)
2133                 DRM_ERROR("PCH poison interrupt\n");
2134
2135         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2136                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2137
2138         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2139                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2140
2141         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2142                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
2143
2144         I915_WRITE(SERR_INT, serr_int);
2145 }
2146
2147 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2148 {
2149         int pipe;
2150         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2151
2152         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2153
2154         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2155                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2156                                SDE_AUDIO_POWER_SHIFT_CPT);
2157                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2158                                  port_name(port));
2159         }
2160
2161         if (pch_iir & SDE_AUX_MASK_CPT)
2162                 dp_aux_irq_handler(dev_priv);
2163
2164         if (pch_iir & SDE_GMBUS_CPT)
2165                 gmbus_irq_handler(dev_priv);
2166
2167         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2168                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2169
2170         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2171                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2172
2173         if (pch_iir & SDE_FDI_MASK_CPT)
2174                 for_each_pipe(dev_priv, pipe)
2175                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2176                                          pipe_name(pipe),
2177                                          I915_READ(FDI_RX_IIR(pipe)));
2178
2179         if (pch_iir & SDE_ERROR_CPT)
2180                 cpt_serr_int_handler(dev_priv);
2181 }
2182
2183 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2184 {
2185         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2186                 ~SDE_PORTE_HOTPLUG_SPT;
2187         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2188         u32 pin_mask = 0, long_mask = 0;
2189
2190         if (hotplug_trigger) {
2191                 u32 dig_hotplug_reg;
2192
2193                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2194                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2195
2196                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2197                                    dig_hotplug_reg, hpd_spt,
2198                                    spt_port_hotplug_long_detect);
2199         }
2200
2201         if (hotplug2_trigger) {
2202                 u32 dig_hotplug_reg;
2203
2204                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2205                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2206
2207                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2208                                    dig_hotplug_reg, hpd_spt,
2209                                    spt_port_hotplug2_long_detect);
2210         }
2211
2212         if (pin_mask)
2213                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2214
2215         if (pch_iir & SDE_GMBUS_CPT)
2216                 gmbus_irq_handler(dev_priv);
2217 }
2218
2219 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2220                                 u32 hotplug_trigger,
2221                                 const u32 hpd[HPD_NUM_PINS])
2222 {
2223         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2224
2225         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2226         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2227
2228         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2229                            dig_hotplug_reg, hpd,
2230                            ilk_port_hotplug_long_detect);
2231
2232         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2233 }
2234
2235 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2236                                     u32 de_iir)
2237 {
2238         enum pipe pipe;
2239         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2240
2241         if (hotplug_trigger)
2242                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2243
2244         if (de_iir & DE_AUX_CHANNEL_A)
2245                 dp_aux_irq_handler(dev_priv);
2246
2247         if (de_iir & DE_GSE)
2248                 intel_opregion_asle_intr(dev_priv);
2249
2250         if (de_iir & DE_POISON)
2251                 DRM_ERROR("Poison interrupt\n");
2252
2253         for_each_pipe(dev_priv, pipe) {
2254                 if (de_iir & DE_PIPE_VBLANK(pipe))
2255                         drm_handle_vblank(&dev_priv->drm, pipe);
2256
2257                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2258                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2259
2260                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2261                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2262         }
2263
2264         /* check event from PCH */
2265         if (de_iir & DE_PCH_EVENT) {
2266                 u32 pch_iir = I915_READ(SDEIIR);
2267
2268                 if (HAS_PCH_CPT(dev_priv))
2269                         cpt_irq_handler(dev_priv, pch_iir);
2270                 else
2271                         ibx_irq_handler(dev_priv, pch_iir);
2272
2273                 /* should clear PCH hotplug event before clear CPU irq */
2274                 I915_WRITE(SDEIIR, pch_iir);
2275         }
2276
2277         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2278                 ironlake_rps_change_irq_handler(dev_priv);
2279 }
2280
2281 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2282                                     u32 de_iir)
2283 {
2284         enum pipe pipe;
2285         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2286
2287         if (hotplug_trigger)
2288                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2289
2290         if (de_iir & DE_ERR_INT_IVB)
2291                 ivb_err_int_handler(dev_priv);
2292
2293         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2294                 dp_aux_irq_handler(dev_priv);
2295
2296         if (de_iir & DE_GSE_IVB)
2297                 intel_opregion_asle_intr(dev_priv);
2298
2299         for_each_pipe(dev_priv, pipe) {
2300                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2301                         drm_handle_vblank(&dev_priv->drm, pipe);
2302         }
2303
2304         /* check event from PCH */
2305         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2306                 u32 pch_iir = I915_READ(SDEIIR);
2307
2308                 cpt_irq_handler(dev_priv, pch_iir);
2309
2310                 /* clear PCH hotplug event before clear CPU irq */
2311                 I915_WRITE(SDEIIR, pch_iir);
2312         }
2313 }
2314
2315 /*
2316  * To handle irqs with the minimum potential races with fresh interrupts, we:
2317  * 1 - Disable Master Interrupt Control.
2318  * 2 - Find the source(s) of the interrupt.
2319  * 3 - Clear the Interrupt Identity bits (IIR).
2320  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2321  * 5 - Re-enable Master Interrupt Control.
2322  */
2323 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2324 {
2325         struct drm_device *dev = arg;
2326         struct drm_i915_private *dev_priv = to_i915(dev);
2327         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2328         irqreturn_t ret = IRQ_NONE;
2329
2330         if (!intel_irqs_enabled(dev_priv))
2331                 return IRQ_NONE;
2332
2333         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2334         disable_rpm_wakeref_asserts(dev_priv);
2335
2336         /* disable master interrupt before clearing iir  */
2337         de_ier = I915_READ(DEIER);
2338         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2339         POSTING_READ(DEIER);
2340
2341         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2342          * interrupts will will be stored on its back queue, and then we'll be
2343          * able to process them after we restore SDEIER (as soon as we restore
2344          * it, we'll get an interrupt if SDEIIR still has something to process
2345          * due to its back queue). */
2346         if (!HAS_PCH_NOP(dev_priv)) {
2347                 sde_ier = I915_READ(SDEIER);
2348                 I915_WRITE(SDEIER, 0);
2349                 POSTING_READ(SDEIER);
2350         }
2351
2352         /* Find, clear, then process each source of interrupt */
2353
2354         gt_iir = I915_READ(GTIIR);
2355         if (gt_iir) {
2356                 I915_WRITE(GTIIR, gt_iir);
2357                 ret = IRQ_HANDLED;
2358                 if (INTEL_GEN(dev_priv) >= 6)
2359                         snb_gt_irq_handler(dev_priv, gt_iir);
2360                 else
2361                         ilk_gt_irq_handler(dev_priv, gt_iir);
2362         }
2363
2364         de_iir = I915_READ(DEIIR);
2365         if (de_iir) {
2366                 I915_WRITE(DEIIR, de_iir);
2367                 ret = IRQ_HANDLED;
2368                 if (INTEL_GEN(dev_priv) >= 7)
2369                         ivb_display_irq_handler(dev_priv, de_iir);
2370                 else
2371                         ilk_display_irq_handler(dev_priv, de_iir);
2372         }
2373
2374         if (INTEL_GEN(dev_priv) >= 6) {
2375                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2376                 if (pm_iir) {
2377                         I915_WRITE(GEN6_PMIIR, pm_iir);
2378                         ret = IRQ_HANDLED;
2379                         gen6_rps_irq_handler(dev_priv, pm_iir);
2380                 }
2381         }
2382
2383         I915_WRITE(DEIER, de_ier);
2384         POSTING_READ(DEIER);
2385         if (!HAS_PCH_NOP(dev_priv)) {
2386                 I915_WRITE(SDEIER, sde_ier);
2387                 POSTING_READ(SDEIER);
2388         }
2389
2390         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2391         enable_rpm_wakeref_asserts(dev_priv);
2392
2393         return ret;
2394 }
2395
2396 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2397                                 u32 hotplug_trigger,
2398                                 const u32 hpd[HPD_NUM_PINS])
2399 {
2400         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2401
2402         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2403         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2404
2405         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2406                            dig_hotplug_reg, hpd,
2407                            bxt_port_hotplug_long_detect);
2408
2409         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2410 }
2411
2412 static irqreturn_t
2413 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2414 {
2415         irqreturn_t ret = IRQ_NONE;
2416         u32 iir;
2417         enum pipe pipe;
2418
2419         if (master_ctl & GEN8_DE_MISC_IRQ) {
2420                 iir = I915_READ(GEN8_DE_MISC_IIR);
2421                 if (iir) {
2422                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2423                         ret = IRQ_HANDLED;
2424                         if (iir & GEN8_DE_MISC_GSE)
2425                                 intel_opregion_asle_intr(dev_priv);
2426                         else
2427                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2428                 }
2429                 else
2430                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2431         }
2432
2433         if (master_ctl & GEN8_DE_PORT_IRQ) {
2434                 iir = I915_READ(GEN8_DE_PORT_IIR);
2435                 if (iir) {
2436                         u32 tmp_mask;
2437                         bool found = false;
2438
2439                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2440                         ret = IRQ_HANDLED;
2441
2442                         tmp_mask = GEN8_AUX_CHANNEL_A;
2443                         if (INTEL_GEN(dev_priv) >= 9)
2444                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2445                                             GEN9_AUX_CHANNEL_C |
2446                                             GEN9_AUX_CHANNEL_D;
2447
2448                         if (iir & tmp_mask) {
2449                                 dp_aux_irq_handler(dev_priv);
2450                                 found = true;
2451                         }
2452
2453                         if (IS_GEN9_LP(dev_priv)) {
2454                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2455                                 if (tmp_mask) {
2456                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2457                                                             hpd_bxt);
2458                                         found = true;
2459                                 }
2460                         } else if (IS_BROADWELL(dev_priv)) {
2461                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2462                                 if (tmp_mask) {
2463                                         ilk_hpd_irq_handler(dev_priv,
2464                                                             tmp_mask, hpd_bdw);
2465                                         found = true;
2466                                 }
2467                         }
2468
2469                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2470                                 gmbus_irq_handler(dev_priv);
2471                                 found = true;
2472                         }
2473
2474                         if (!found)
2475                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2476                 }
2477                 else
2478                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2479         }
2480
2481         for_each_pipe(dev_priv, pipe) {
2482                 u32 fault_errors;
2483
2484                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2485                         continue;
2486
2487                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2488                 if (!iir) {
2489                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2490                         continue;
2491                 }
2492
2493                 ret = IRQ_HANDLED;
2494                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2495
2496                 if (iir & GEN8_PIPE_VBLANK)
2497                         drm_handle_vblank(&dev_priv->drm, pipe);
2498
2499                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2500                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2501
2502                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2503                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2504
2505                 fault_errors = iir;
2506                 if (INTEL_GEN(dev_priv) >= 9)
2507                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2508                 else
2509                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2510
2511                 if (fault_errors)
2512                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2513                                   pipe_name(pipe),
2514                                   fault_errors);
2515         }
2516
2517         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2518             master_ctl & GEN8_DE_PCH_IRQ) {
2519                 /*
2520                  * FIXME(BDW): Assume for now that the new interrupt handling
2521                  * scheme also closed the SDE interrupt handling race we've seen
2522                  * on older pch-split platforms. But this needs testing.
2523                  */
2524                 iir = I915_READ(SDEIIR);
2525                 if (iir) {
2526                         I915_WRITE(SDEIIR, iir);
2527                         ret = IRQ_HANDLED;
2528
2529                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
2530                             HAS_PCH_CNP(dev_priv))
2531                                 spt_irq_handler(dev_priv, iir);
2532                         else
2533                                 cpt_irq_handler(dev_priv, iir);
2534                 } else {
2535                         /*
2536                          * Like on previous PCH there seems to be something
2537                          * fishy going on with forwarding PCH interrupts.
2538                          */
2539                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2540                 }
2541         }
2542
2543         return ret;
2544 }
2545
2546 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2547 {
2548         struct drm_device *dev = arg;
2549         struct drm_i915_private *dev_priv = to_i915(dev);
2550         u32 master_ctl;
2551         u32 gt_iir[4] = {};
2552         irqreturn_t ret;
2553
2554         if (!intel_irqs_enabled(dev_priv))
2555                 return IRQ_NONE;
2556
2557         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2558         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2559         if (!master_ctl)
2560                 return IRQ_NONE;
2561
2562         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2563
2564         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2565         disable_rpm_wakeref_asserts(dev_priv);
2566
2567         /* Find, clear, then process each source of interrupt */
2568         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2569         gen8_gt_irq_handler(dev_priv, gt_iir);
2570         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2571
2572         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2573         POSTING_READ_FW(GEN8_MASTER_IRQ);
2574
2575         enable_rpm_wakeref_asserts(dev_priv);
2576
2577         return ret;
2578 }
2579
2580 struct wedge_me {
2581         struct delayed_work work;
2582         struct drm_i915_private *i915;
2583         const char *name;
2584 };
2585
2586 static void wedge_me(struct work_struct *work)
2587 {
2588         struct wedge_me *w = container_of(work, typeof(*w), work.work);
2589
2590         dev_err(w->i915->drm.dev,
2591                 "%s timed out, cancelling all in-flight rendering.\n",
2592                 w->name);
2593         i915_gem_set_wedged(w->i915);
2594 }
2595
2596 static void __init_wedge(struct wedge_me *w,
2597                          struct drm_i915_private *i915,
2598                          long timeout,
2599                          const char *name)
2600 {
2601         w->i915 = i915;
2602         w->name = name;
2603
2604         INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me);
2605         schedule_delayed_work(&w->work, timeout);
2606 }
2607
2608 static void __fini_wedge(struct wedge_me *w)
2609 {
2610         cancel_delayed_work_sync(&w->work);
2611         destroy_delayed_work_on_stack(&w->work);
2612         w->i915 = NULL;
2613 }
2614
2615 #define i915_wedge_on_timeout(W, DEV, TIMEOUT)                          \
2616         for (__init_wedge((W), (DEV), (TIMEOUT), __func__);             \
2617              (W)->i915;                                                 \
2618              __fini_wedge((W)))
2619
2620 /**
2621  * i915_reset_device - do process context error handling work
2622  * @dev_priv: i915 device private
2623  *
2624  * Fire an error uevent so userspace can see that a hang or error
2625  * was detected.
2626  */
2627 static void i915_reset_device(struct drm_i915_private *dev_priv)
2628 {
2629         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2630         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2631         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2632         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2633         struct wedge_me w;
2634
2635         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2636
2637         DRM_DEBUG_DRIVER("resetting chip\n");
2638         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2639
2640         /* Use a watchdog to ensure that our reset completes */
2641         i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
2642                 intel_prepare_reset(dev_priv);
2643
2644                 /* Signal that locked waiters should reset the GPU */
2645                 set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags);
2646                 wake_up_all(&dev_priv->gpu_error.wait_queue);
2647
2648                 /* Wait for anyone holding the lock to wakeup, without
2649                  * blocking indefinitely on struct_mutex.
2650                  */
2651                 do {
2652                         if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2653                                 i915_reset(dev_priv, 0);
2654                                 mutex_unlock(&dev_priv->drm.struct_mutex);
2655                         }
2656                 } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2657                                              I915_RESET_HANDOFF,
2658                                              TASK_UNINTERRUPTIBLE,
2659                                              1));
2660
2661                 intel_finish_reset(dev_priv);
2662         }
2663
2664         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2665                 kobject_uevent_env(kobj,
2666                                    KOBJ_CHANGE, reset_done_event);
2667 }
2668
2669 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2670 {
2671         u32 eir;
2672
2673         if (!IS_GEN2(dev_priv))
2674                 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2675
2676         if (INTEL_GEN(dev_priv) < 4)
2677                 I915_WRITE(IPEIR, I915_READ(IPEIR));
2678         else
2679                 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2680
2681         I915_WRITE(EIR, I915_READ(EIR));
2682         eir = I915_READ(EIR);
2683         if (eir) {
2684                 /*
2685                  * some errors might have become stuck,
2686                  * mask them.
2687                  */
2688                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2689                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2690                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2691         }
2692 }
2693
2694 /**
2695  * i915_handle_error - handle a gpu error
2696  * @dev_priv: i915 device private
2697  * @engine_mask: mask representing engines that are hung
2698  * @fmt: Error message format string
2699  *
2700  * Do some basic checking of register state at error time and
2701  * dump it to the syslog.  Also call i915_capture_error_state() to make
2702  * sure we get a record and make it available in debugfs.  Fire a uevent
2703  * so userspace knows something bad happened (should trigger collection
2704  * of a ring dump etc.).
2705  */
2706 void i915_handle_error(struct drm_i915_private *dev_priv,
2707                        u32 engine_mask,
2708                        const char *fmt, ...)
2709 {
2710         struct intel_engine_cs *engine;
2711         unsigned int tmp;
2712         va_list args;
2713         char error_msg[80];
2714
2715         va_start(args, fmt);
2716         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2717         va_end(args);
2718
2719         /*
2720          * In most cases it's guaranteed that we get here with an RPM
2721          * reference held, for example because there is a pending GPU
2722          * request that won't finish until the reset is done. This
2723          * isn't the case at least when we get here by doing a
2724          * simulated reset via debugfs, so get an RPM reference.
2725          */
2726         intel_runtime_pm_get(dev_priv);
2727
2728         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2729         i915_clear_error_registers(dev_priv);
2730
2731         /*
2732          * Try engine reset when available. We fall back to full reset if
2733          * single reset fails.
2734          */
2735         if (intel_has_reset_engine(dev_priv)) {
2736                 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
2737                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
2738                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
2739                                              &dev_priv->gpu_error.flags))
2740                                 continue;
2741
2742                         if (i915_reset_engine(engine, 0) == 0)
2743                                 engine_mask &= ~intel_engine_flag(engine);
2744
2745                         clear_bit(I915_RESET_ENGINE + engine->id,
2746                                   &dev_priv->gpu_error.flags);
2747                         wake_up_bit(&dev_priv->gpu_error.flags,
2748                                     I915_RESET_ENGINE + engine->id);
2749                 }
2750         }
2751
2752         if (!engine_mask)
2753                 goto out;
2754
2755         /* Full reset needs the mutex, stop any other user trying to do so. */
2756         if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) {
2757                 wait_event(dev_priv->gpu_error.reset_queue,
2758                            !test_bit(I915_RESET_BACKOFF,
2759                                      &dev_priv->gpu_error.flags));
2760                 goto out;
2761         }
2762
2763         /* Prevent any other reset-engine attempt. */
2764         for_each_engine(engine, dev_priv, tmp) {
2765                 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
2766                                         &dev_priv->gpu_error.flags))
2767                         wait_on_bit(&dev_priv->gpu_error.flags,
2768                                     I915_RESET_ENGINE + engine->id,
2769                                     TASK_UNINTERRUPTIBLE);
2770         }
2771
2772         i915_reset_device(dev_priv);
2773
2774         for_each_engine(engine, dev_priv, tmp) {
2775                 clear_bit(I915_RESET_ENGINE + engine->id,
2776                           &dev_priv->gpu_error.flags);
2777         }
2778
2779         clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags);
2780         wake_up_all(&dev_priv->gpu_error.reset_queue);
2781
2782 out:
2783         intel_runtime_pm_put(dev_priv);
2784 }
2785
2786 /* Called from drm generic code, passed 'crtc' which
2787  * we use as a pipe index
2788  */
2789 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2790 {
2791         struct drm_i915_private *dev_priv = to_i915(dev);
2792         unsigned long irqflags;
2793
2794         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2795         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2796         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2797
2798         return 0;
2799 }
2800
2801 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2802 {
2803         struct drm_i915_private *dev_priv = to_i915(dev);
2804         unsigned long irqflags;
2805
2806         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2807         i915_enable_pipestat(dev_priv, pipe,
2808                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2809         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2810
2811         return 0;
2812 }
2813
2814 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2815 {
2816         struct drm_i915_private *dev_priv = to_i915(dev);
2817         unsigned long irqflags;
2818         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2819                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2820
2821         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2822         ilk_enable_display_irq(dev_priv, bit);
2823         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2824
2825         return 0;
2826 }
2827
2828 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2829 {
2830         struct drm_i915_private *dev_priv = to_i915(dev);
2831         unsigned long irqflags;
2832
2833         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2834         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2835         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2836
2837         return 0;
2838 }
2839
2840 /* Called from drm generic code, passed 'crtc' which
2841  * we use as a pipe index
2842  */
2843 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2844 {
2845         struct drm_i915_private *dev_priv = to_i915(dev);
2846         unsigned long irqflags;
2847
2848         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2849         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2850         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2851 }
2852
2853 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2854 {
2855         struct drm_i915_private *dev_priv = to_i915(dev);
2856         unsigned long irqflags;
2857
2858         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2859         i915_disable_pipestat(dev_priv, pipe,
2860                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2861         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2862 }
2863
2864 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2865 {
2866         struct drm_i915_private *dev_priv = to_i915(dev);
2867         unsigned long irqflags;
2868         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2869                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2870
2871         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2872         ilk_disable_display_irq(dev_priv, bit);
2873         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2874 }
2875
2876 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2877 {
2878         struct drm_i915_private *dev_priv = to_i915(dev);
2879         unsigned long irqflags;
2880
2881         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2882         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2883         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2884 }
2885
2886 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2887 {
2888         if (HAS_PCH_NOP(dev_priv))
2889                 return;
2890
2891         GEN5_IRQ_RESET(SDE);
2892
2893         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2894                 I915_WRITE(SERR_INT, 0xffffffff);
2895 }
2896
2897 /*
2898  * SDEIER is also touched by the interrupt handler to work around missed PCH
2899  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2900  * instead we unconditionally enable all PCH interrupt sources here, but then
2901  * only unmask them as needed with SDEIMR.
2902  *
2903  * This function needs to be called before interrupts are enabled.
2904  */
2905 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2906 {
2907         struct drm_i915_private *dev_priv = to_i915(dev);
2908
2909         if (HAS_PCH_NOP(dev_priv))
2910                 return;
2911
2912         WARN_ON(I915_READ(SDEIER) != 0);
2913         I915_WRITE(SDEIER, 0xffffffff);
2914         POSTING_READ(SDEIER);
2915 }
2916
2917 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2918 {
2919         GEN5_IRQ_RESET(GT);
2920         if (INTEL_GEN(dev_priv) >= 6)
2921                 GEN5_IRQ_RESET(GEN6_PM);
2922 }
2923
2924 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2925 {
2926         enum pipe pipe;
2927
2928         if (IS_CHERRYVIEW(dev_priv))
2929                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2930         else
2931                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2932
2933         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2934         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2935
2936         for_each_pipe(dev_priv, pipe) {
2937                 I915_WRITE(PIPESTAT(pipe),
2938                            PIPE_FIFO_UNDERRUN_STATUS |
2939                            PIPESTAT_INT_STATUS_MASK);
2940                 dev_priv->pipestat_irq_mask[pipe] = 0;
2941         }
2942
2943         GEN5_IRQ_RESET(VLV_);
2944         dev_priv->irq_mask = ~0;
2945 }
2946
2947 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2948 {
2949         u32 pipestat_mask;
2950         u32 enable_mask;
2951         enum pipe pipe;
2952
2953         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2954                         PIPE_CRC_DONE_INTERRUPT_STATUS;
2955
2956         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2957         for_each_pipe(dev_priv, pipe)
2958                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2959
2960         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2961                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2962                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2963                 I915_LPE_PIPE_A_INTERRUPT |
2964                 I915_LPE_PIPE_B_INTERRUPT;
2965
2966         if (IS_CHERRYVIEW(dev_priv))
2967                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2968                         I915_LPE_PIPE_C_INTERRUPT;
2969
2970         WARN_ON(dev_priv->irq_mask != ~0);
2971
2972         dev_priv->irq_mask = ~enable_mask;
2973
2974         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
2975 }
2976
2977 /* drm_dma.h hooks
2978 */
2979 static void ironlake_irq_reset(struct drm_device *dev)
2980 {
2981         struct drm_i915_private *dev_priv = to_i915(dev);
2982
2983         I915_WRITE(HWSTAM, 0xffffffff);
2984
2985         GEN5_IRQ_RESET(DE);
2986         if (IS_GEN7(dev_priv))
2987                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2988
2989         gen5_gt_irq_reset(dev_priv);
2990
2991         ibx_irq_reset(dev_priv);
2992 }
2993
2994 static void valleyview_irq_preinstall(struct drm_device *dev)
2995 {
2996         struct drm_i915_private *dev_priv = to_i915(dev);
2997
2998         I915_WRITE(VLV_MASTER_IER, 0);
2999         POSTING_READ(VLV_MASTER_IER);
3000
3001         gen5_gt_irq_reset(dev_priv);
3002
3003         spin_lock_irq(&dev_priv->irq_lock);
3004         if (dev_priv->display_irqs_enabled)
3005                 vlv_display_irq_reset(dev_priv);
3006         spin_unlock_irq(&dev_priv->irq_lock);
3007 }
3008
3009 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3010 {
3011         GEN8_IRQ_RESET_NDX(GT, 0);
3012         GEN8_IRQ_RESET_NDX(GT, 1);
3013         GEN8_IRQ_RESET_NDX(GT, 2);
3014         GEN8_IRQ_RESET_NDX(GT, 3);
3015 }
3016
3017 static void gen8_irq_reset(struct drm_device *dev)
3018 {
3019         struct drm_i915_private *dev_priv = to_i915(dev);
3020         int pipe;
3021
3022         I915_WRITE(GEN8_MASTER_IRQ, 0);
3023         POSTING_READ(GEN8_MASTER_IRQ);
3024
3025         gen8_gt_irq_reset(dev_priv);
3026
3027         for_each_pipe(dev_priv, pipe)
3028                 if (intel_display_power_is_enabled(dev_priv,
3029                                                    POWER_DOMAIN_PIPE(pipe)))
3030                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3031
3032         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3033         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3034         GEN5_IRQ_RESET(GEN8_PCU_);
3035
3036         if (HAS_PCH_SPLIT(dev_priv))
3037                 ibx_irq_reset(dev_priv);
3038 }
3039
3040 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3041                                      u8 pipe_mask)
3042 {
3043         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3044         enum pipe pipe;
3045
3046         spin_lock_irq(&dev_priv->irq_lock);
3047         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3048                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3049                                   dev_priv->de_irq_mask[pipe],
3050                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3051         spin_unlock_irq(&dev_priv->irq_lock);
3052 }
3053
3054 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3055                                      u8 pipe_mask)
3056 {
3057         enum pipe pipe;
3058
3059         spin_lock_irq(&dev_priv->irq_lock);
3060         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3061                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3062         spin_unlock_irq(&dev_priv->irq_lock);
3063
3064         /* make sure we're done processing display irqs */
3065         synchronize_irq(dev_priv->drm.irq);
3066 }
3067
3068 static void cherryview_irq_preinstall(struct drm_device *dev)
3069 {
3070         struct drm_i915_private *dev_priv = to_i915(dev);
3071
3072         I915_WRITE(GEN8_MASTER_IRQ, 0);
3073         POSTING_READ(GEN8_MASTER_IRQ);
3074
3075         gen8_gt_irq_reset(dev_priv);
3076
3077         GEN5_IRQ_RESET(GEN8_PCU_);
3078
3079         spin_lock_irq(&dev_priv->irq_lock);
3080         if (dev_priv->display_irqs_enabled)
3081                 vlv_display_irq_reset(dev_priv);
3082         spin_unlock_irq(&dev_priv->irq_lock);
3083 }
3084
3085 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3086                                   const u32 hpd[HPD_NUM_PINS])
3087 {
3088         struct intel_encoder *encoder;
3089         u32 enabled_irqs = 0;
3090
3091         for_each_intel_encoder(&dev_priv->drm, encoder)
3092                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3093                         enabled_irqs |= hpd[encoder->hpd_pin];
3094
3095         return enabled_irqs;
3096 }
3097
3098 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3099 {
3100         u32 hotplug;
3101
3102         /*
3103          * Enable digital hotplug on the PCH, and configure the DP short pulse
3104          * duration to 2ms (which is the minimum in the Display Port spec).
3105          * The pulse duration bits are reserved on LPT+.
3106          */
3107         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3108         hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3109                      PORTC_PULSE_DURATION_MASK |
3110                      PORTD_PULSE_DURATION_MASK);
3111         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3112         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3113         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3114         /*
3115          * When CPU and PCH are on the same package, port A
3116          * HPD must be enabled in both north and south.
3117          */
3118         if (HAS_PCH_LPT_LP(dev_priv))
3119                 hotplug |= PORTA_HOTPLUG_ENABLE;
3120         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3121 }
3122
3123 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3124 {
3125         u32 hotplug_irqs, enabled_irqs;
3126
3127         if (HAS_PCH_IBX(dev_priv)) {
3128                 hotplug_irqs = SDE_HOTPLUG_MASK;
3129                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3130         } else {
3131                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3132                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3133         }
3134
3135         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3136
3137         ibx_hpd_detection_setup(dev_priv);
3138 }
3139
3140 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3141 {
3142         u32 hotplug;
3143
3144         /* Enable digital hotplug on the PCH */
3145         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3146         hotplug |= PORTA_HOTPLUG_ENABLE |
3147                    PORTB_HOTPLUG_ENABLE |
3148                    PORTC_HOTPLUG_ENABLE |
3149                    PORTD_HOTPLUG_ENABLE;
3150         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3151
3152         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3153         hotplug |= PORTE_HOTPLUG_ENABLE;
3154         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3155 }
3156
3157 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3158 {
3159         u32 hotplug_irqs, enabled_irqs;
3160
3161         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3162         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3163
3164         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3165
3166         spt_hpd_detection_setup(dev_priv);
3167 }
3168
3169 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3170 {
3171         u32 hotplug;
3172
3173         /*
3174          * Enable digital hotplug on the CPU, and configure the DP short pulse
3175          * duration to 2ms (which is the minimum in the Display Port spec)
3176          * The pulse duration bits are reserved on HSW+.
3177          */
3178         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3179         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3180         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3181                    DIGITAL_PORTA_PULSE_DURATION_2ms;
3182         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3183 }
3184
3185 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3186 {
3187         u32 hotplug_irqs, enabled_irqs;
3188
3189         if (INTEL_GEN(dev_priv) >= 8) {
3190                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3191                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3192
3193                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3194         } else if (INTEL_GEN(dev_priv) >= 7) {
3195                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3196                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3197
3198                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3199         } else {
3200                 hotplug_irqs = DE_DP_A_HOTPLUG;
3201                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3202
3203                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3204         }
3205
3206         ilk_hpd_detection_setup(dev_priv);
3207
3208         ibx_hpd_irq_setup(dev_priv);
3209 }
3210
3211 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3212                                       u32 enabled_irqs)
3213 {
3214         u32 hotplug;
3215
3216         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3217         hotplug |= PORTA_HOTPLUG_ENABLE |
3218                    PORTB_HOTPLUG_ENABLE |
3219                    PORTC_HOTPLUG_ENABLE;
3220
3221         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3222                       hotplug, enabled_irqs);
3223         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3224
3225         /*
3226          * For BXT invert bit has to be set based on AOB design
3227          * for HPD detection logic, update it based on VBT fields.
3228          */
3229         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3230             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3231                 hotplug |= BXT_DDIA_HPD_INVERT;
3232         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3233             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3234                 hotplug |= BXT_DDIB_HPD_INVERT;
3235         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3236             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3237                 hotplug |= BXT_DDIC_HPD_INVERT;
3238
3239         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3240 }
3241
3242 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3243 {
3244         __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3245 }
3246
3247 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3248 {
3249         u32 hotplug_irqs, enabled_irqs;
3250
3251         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3252         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3253
3254         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3255
3256         __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3257 }
3258
3259 static void ibx_irq_postinstall(struct drm_device *dev)
3260 {
3261         struct drm_i915_private *dev_priv = to_i915(dev);
3262         u32 mask;
3263
3264         if (HAS_PCH_NOP(dev_priv))
3265                 return;
3266
3267         if (HAS_PCH_IBX(dev_priv))
3268                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3269         else
3270                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3271
3272         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3273         I915_WRITE(SDEIMR, ~mask);
3274
3275         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3276             HAS_PCH_LPT(dev_priv))
3277                 ibx_hpd_detection_setup(dev_priv);
3278         else
3279                 spt_hpd_detection_setup(dev_priv);
3280 }
3281
3282 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3283 {
3284         struct drm_i915_private *dev_priv = to_i915(dev);
3285         u32 pm_irqs, gt_irqs;
3286
3287         pm_irqs = gt_irqs = 0;
3288
3289         dev_priv->gt_irq_mask = ~0;
3290         if (HAS_L3_DPF(dev_priv)) {
3291                 /* L3 parity interrupt is always unmasked. */
3292                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3293                 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3294         }
3295
3296         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3297         if (IS_GEN5(dev_priv)) {
3298                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3299         } else {
3300                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3301         }
3302
3303         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3304
3305         if (INTEL_GEN(dev_priv) >= 6) {
3306                 /*
3307                  * RPS interrupts will get enabled/disabled on demand when RPS
3308                  * itself is enabled/disabled.
3309                  */
3310                 if (HAS_VEBOX(dev_priv)) {
3311                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3312                         dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3313                 }
3314
3315                 dev_priv->pm_imr = 0xffffffff;
3316                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3317         }
3318 }
3319
3320 static int ironlake_irq_postinstall(struct drm_device *dev)
3321 {
3322         struct drm_i915_private *dev_priv = to_i915(dev);
3323         u32 display_mask, extra_mask;
3324
3325         if (INTEL_GEN(dev_priv) >= 7) {
3326                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3327                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3328                                 DE_PLANEB_FLIP_DONE_IVB |
3329                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3330                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3331                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3332                               DE_DP_A_HOTPLUG_IVB);
3333         } else {
3334                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3335                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3336                                 DE_AUX_CHANNEL_A |
3337                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3338                                 DE_POISON);
3339                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3340                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3341                               DE_DP_A_HOTPLUG);
3342         }
3343
3344         dev_priv->irq_mask = ~display_mask;
3345
3346         I915_WRITE(HWSTAM, 0xeffe);
3347
3348         ibx_irq_pre_postinstall(dev);
3349
3350         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3351
3352         gen5_gt_irq_postinstall(dev);
3353
3354         ilk_hpd_detection_setup(dev_priv);
3355
3356         ibx_irq_postinstall(dev);
3357
3358         if (IS_IRONLAKE_M(dev_priv)) {
3359                 /* Enable PCU event interrupts
3360                  *
3361                  * spinlocking not required here for correctness since interrupt
3362                  * setup is guaranteed to run in single-threaded context. But we
3363                  * need it to make the assert_spin_locked happy. */
3364                 spin_lock_irq(&dev_priv->irq_lock);
3365                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3366                 spin_unlock_irq(&dev_priv->irq_lock);
3367         }
3368
3369         return 0;
3370 }
3371
3372 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3373 {
3374         lockdep_assert_held(&dev_priv->irq_lock);
3375
3376         if (dev_priv->display_irqs_enabled)
3377                 return;
3378
3379         dev_priv->display_irqs_enabled = true;
3380
3381         if (intel_irqs_enabled(dev_priv)) {
3382                 vlv_display_irq_reset(dev_priv);
3383                 vlv_display_irq_postinstall(dev_priv);
3384         }
3385 }
3386
3387 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3388 {
3389         lockdep_assert_held(&dev_priv->irq_lock);
3390
3391         if (!dev_priv->display_irqs_enabled)
3392                 return;
3393
3394         dev_priv->display_irqs_enabled = false;
3395
3396         if (intel_irqs_enabled(dev_priv))
3397                 vlv_display_irq_reset(dev_priv);
3398 }
3399
3400
3401 static int valleyview_irq_postinstall(struct drm_device *dev)
3402 {
3403         struct drm_i915_private *dev_priv = to_i915(dev);
3404
3405         gen5_gt_irq_postinstall(dev);
3406
3407         spin_lock_irq(&dev_priv->irq_lock);
3408         if (dev_priv->display_irqs_enabled)
3409                 vlv_display_irq_postinstall(dev_priv);
3410         spin_unlock_irq(&dev_priv->irq_lock);
3411
3412         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3413         POSTING_READ(VLV_MASTER_IER);
3414
3415         return 0;
3416 }
3417
3418 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3419 {
3420         /* These are interrupts we'll toggle with the ring mask register */
3421         uint32_t gt_interrupts[] = {
3422                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3423                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3424                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3425                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3426                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3427                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3428                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3429                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3430                 0,
3431                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3432                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3433                 };
3434
3435         if (HAS_L3_DPF(dev_priv))
3436                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3437
3438         dev_priv->pm_ier = 0x0;
3439         dev_priv->pm_imr = ~dev_priv->pm_ier;
3440         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3441         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3442         /*
3443          * RPS interrupts will get enabled/disabled on demand when RPS itself
3444          * is enabled/disabled. Same wil be the case for GuC interrupts.
3445          */
3446         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3447         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3448 }
3449
3450 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3451 {
3452         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3453         uint32_t de_pipe_enables;
3454         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3455         u32 de_port_enables;
3456         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3457         enum pipe pipe;
3458
3459         if (INTEL_GEN(dev_priv) >= 9) {
3460                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3461                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3462                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3463                                   GEN9_AUX_CHANNEL_D;
3464                 if (IS_GEN9_LP(dev_priv))
3465                         de_port_masked |= BXT_DE_PORT_GMBUS;
3466         } else {
3467                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3468                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3469         }
3470
3471         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3472                                            GEN8_PIPE_FIFO_UNDERRUN;
3473
3474         de_port_enables = de_port_masked;
3475         if (IS_GEN9_LP(dev_priv))
3476                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3477         else if (IS_BROADWELL(dev_priv))
3478                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3479
3480         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3481         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3482         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3483
3484         for_each_pipe(dev_priv, pipe)
3485                 if (intel_display_power_is_enabled(dev_priv,
3486                                 POWER_DOMAIN_PIPE(pipe)))
3487                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3488                                           dev_priv->de_irq_mask[pipe],
3489                                           de_pipe_enables);
3490
3491         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3492         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3493
3494         if (IS_GEN9_LP(dev_priv))
3495                 bxt_hpd_detection_setup(dev_priv);
3496         else if (IS_BROADWELL(dev_priv))
3497                 ilk_hpd_detection_setup(dev_priv);
3498 }
3499
3500 static int gen8_irq_postinstall(struct drm_device *dev)
3501 {
3502         struct drm_i915_private *dev_priv = to_i915(dev);
3503
3504         if (HAS_PCH_SPLIT(dev_priv))
3505                 ibx_irq_pre_postinstall(dev);
3506
3507         gen8_gt_irq_postinstall(dev_priv);
3508         gen8_de_irq_postinstall(dev_priv);
3509
3510         if (HAS_PCH_SPLIT(dev_priv))
3511                 ibx_irq_postinstall(dev);
3512
3513         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3514         POSTING_READ(GEN8_MASTER_IRQ);
3515
3516         return 0;
3517 }
3518
3519 static int cherryview_irq_postinstall(struct drm_device *dev)
3520 {
3521         struct drm_i915_private *dev_priv = to_i915(dev);
3522
3523         gen8_gt_irq_postinstall(dev_priv);
3524
3525         spin_lock_irq(&dev_priv->irq_lock);
3526         if (dev_priv->display_irqs_enabled)
3527                 vlv_display_irq_postinstall(dev_priv);
3528         spin_unlock_irq(&dev_priv->irq_lock);
3529
3530         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3531         POSTING_READ(GEN8_MASTER_IRQ);
3532
3533         return 0;
3534 }
3535
3536 static void gen8_irq_uninstall(struct drm_device *dev)
3537 {
3538         struct drm_i915_private *dev_priv = to_i915(dev);
3539
3540         if (!dev_priv)
3541                 return;
3542
3543         gen8_irq_reset(dev);
3544 }
3545
3546 static void valleyview_irq_uninstall(struct drm_device *dev)
3547 {
3548         struct drm_i915_private *dev_priv = to_i915(dev);
3549
3550         if (!dev_priv)
3551                 return;
3552
3553         I915_WRITE(VLV_MASTER_IER, 0);
3554         POSTING_READ(VLV_MASTER_IER);
3555
3556         gen5_gt_irq_reset(dev_priv);
3557
3558         I915_WRITE(HWSTAM, 0xffffffff);
3559
3560         spin_lock_irq(&dev_priv->irq_lock);
3561         if (dev_priv->display_irqs_enabled)
3562                 vlv_display_irq_reset(dev_priv);
3563         spin_unlock_irq(&dev_priv->irq_lock);
3564 }
3565
3566 static void cherryview_irq_uninstall(struct drm_device *dev)
3567 {
3568         struct drm_i915_private *dev_priv = to_i915(dev);
3569
3570         if (!dev_priv)
3571                 return;
3572
3573         I915_WRITE(GEN8_MASTER_IRQ, 0);
3574         POSTING_READ(GEN8_MASTER_IRQ);
3575
3576         gen8_gt_irq_reset(dev_priv);
3577
3578         GEN5_IRQ_RESET(GEN8_PCU_);
3579
3580         spin_lock_irq(&dev_priv->irq_lock);
3581         if (dev_priv->display_irqs_enabled)
3582                 vlv_display_irq_reset(dev_priv);
3583         spin_unlock_irq(&dev_priv->irq_lock);
3584 }
3585
3586 static void ironlake_irq_uninstall(struct drm_device *dev)
3587 {
3588         struct drm_i915_private *dev_priv = to_i915(dev);
3589
3590         if (!dev_priv)
3591                 return;
3592
3593         ironlake_irq_reset(dev);
3594 }
3595
3596 static void i8xx_irq_preinstall(struct drm_device * dev)
3597 {
3598         struct drm_i915_private *dev_priv = to_i915(dev);
3599         int pipe;
3600
3601         for_each_pipe(dev_priv, pipe)
3602                 I915_WRITE(PIPESTAT(pipe), 0);
3603         I915_WRITE16(IMR, 0xffff);
3604         I915_WRITE16(IER, 0x0);
3605         POSTING_READ16(IER);
3606 }
3607
3608 static int i8xx_irq_postinstall(struct drm_device *dev)
3609 {
3610         struct drm_i915_private *dev_priv = to_i915(dev);
3611
3612         I915_WRITE16(EMR,
3613                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3614
3615         /* Unmask the interrupts that we always want on. */
3616         dev_priv->irq_mask =
3617                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3618                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3619                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3620                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3621         I915_WRITE16(IMR, dev_priv->irq_mask);
3622
3623         I915_WRITE16(IER,
3624                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3625                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3626                      I915_USER_INTERRUPT);
3627         POSTING_READ16(IER);
3628
3629         /* Interrupt setup is already guaranteed to be single-threaded, this is
3630          * just to make the assert_spin_locked check happy. */
3631         spin_lock_irq(&dev_priv->irq_lock);
3632         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3633         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3634         spin_unlock_irq(&dev_priv->irq_lock);
3635
3636         return 0;
3637 }
3638
3639 /*
3640  * Returns true when a page flip has completed.
3641  */
3642 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3643 {
3644         struct drm_device *dev = arg;
3645         struct drm_i915_private *dev_priv = to_i915(dev);
3646         u16 iir, new_iir;
3647         u32 pipe_stats[2];
3648         int pipe;
3649         irqreturn_t ret;
3650
3651         if (!intel_irqs_enabled(dev_priv))
3652                 return IRQ_NONE;
3653
3654         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3655         disable_rpm_wakeref_asserts(dev_priv);
3656
3657         ret = IRQ_NONE;
3658         iir = I915_READ16(IIR);
3659         if (iir == 0)
3660                 goto out;
3661
3662         while (iir) {
3663                 /* Can't rely on pipestat interrupt bit in iir as it might
3664                  * have been cleared after the pipestat interrupt was received.
3665                  * It doesn't set the bit in iir again, but it still produces
3666                  * interrupts (for non-MSI).
3667                  */
3668                 spin_lock(&dev_priv->irq_lock);
3669                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3670                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3671
3672                 for_each_pipe(dev_priv, pipe) {
3673                         i915_reg_t reg = PIPESTAT(pipe);
3674                         pipe_stats[pipe] = I915_READ(reg);
3675
3676                         /*
3677                          * Clear the PIPE*STAT regs before the IIR
3678                          */
3679                         if (pipe_stats[pipe] & 0x8000ffff)
3680                                 I915_WRITE(reg, pipe_stats[pipe]);
3681                 }
3682                 spin_unlock(&dev_priv->irq_lock);
3683
3684                 I915_WRITE16(IIR, iir);
3685                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3686
3687                 if (iir & I915_USER_INTERRUPT)
3688                         notify_ring(dev_priv->engine[RCS]);
3689
3690                 for_each_pipe(dev_priv, pipe) {
3691                         int plane = pipe;
3692                         if (HAS_FBC(dev_priv))
3693                                 plane = !plane;
3694
3695                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
3696                                 drm_handle_vblank(&dev_priv->drm, pipe);
3697
3698                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3699                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3700
3701                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3702                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3703                                                                     pipe);
3704                 }
3705
3706                 iir = new_iir;
3707         }
3708         ret = IRQ_HANDLED;
3709
3710 out:
3711         enable_rpm_wakeref_asserts(dev_priv);
3712
3713         return ret;
3714 }
3715
3716 static void i8xx_irq_uninstall(struct drm_device * dev)
3717 {
3718         struct drm_i915_private *dev_priv = to_i915(dev);
3719         int pipe;
3720
3721         for_each_pipe(dev_priv, pipe) {
3722                 /* Clear enable bits; then clear status bits */
3723                 I915_WRITE(PIPESTAT(pipe), 0);
3724                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3725         }
3726         I915_WRITE16(IMR, 0xffff);
3727         I915_WRITE16(IER, 0x0);
3728         I915_WRITE16(IIR, I915_READ16(IIR));
3729 }
3730
3731 static void i915_irq_preinstall(struct drm_device * dev)
3732 {
3733         struct drm_i915_private *dev_priv = to_i915(dev);
3734         int pipe;
3735
3736         if (I915_HAS_HOTPLUG(dev_priv)) {
3737                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3738                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3739         }
3740
3741         I915_WRITE16(HWSTAM, 0xeffe);
3742         for_each_pipe(dev_priv, pipe)
3743                 I915_WRITE(PIPESTAT(pipe), 0);
3744         I915_WRITE(IMR, 0xffffffff);
3745         I915_WRITE(IER, 0x0);
3746         POSTING_READ(IER);
3747 }
3748
3749 static int i915_irq_postinstall(struct drm_device *dev)
3750 {
3751         struct drm_i915_private *dev_priv = to_i915(dev);
3752         u32 enable_mask;
3753
3754         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3755
3756         /* Unmask the interrupts that we always want on. */
3757         dev_priv->irq_mask =
3758                 ~(I915_ASLE_INTERRUPT |
3759                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3760                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3761                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3762                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3763
3764         enable_mask =
3765                 I915_ASLE_INTERRUPT |
3766                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3767                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3768                 I915_USER_INTERRUPT;
3769
3770         if (I915_HAS_HOTPLUG(dev_priv)) {
3771                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3772                 POSTING_READ(PORT_HOTPLUG_EN);
3773
3774                 /* Enable in IER... */
3775                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3776                 /* and unmask in IMR */
3777                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3778         }
3779
3780         I915_WRITE(IMR, dev_priv->irq_mask);
3781         I915_WRITE(IER, enable_mask);
3782         POSTING_READ(IER);
3783
3784         i915_enable_asle_pipestat(dev_priv);
3785
3786         /* Interrupt setup is already guaranteed to be single-threaded, this is
3787          * just to make the assert_spin_locked check happy. */
3788         spin_lock_irq(&dev_priv->irq_lock);
3789         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3790         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3791         spin_unlock_irq(&dev_priv->irq_lock);
3792
3793         return 0;
3794 }
3795
3796 static irqreturn_t i915_irq_handler(int irq, void *arg)
3797 {
3798         struct drm_device *dev = arg;
3799         struct drm_i915_private *dev_priv = to_i915(dev);
3800         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3801         int pipe, ret = IRQ_NONE;
3802
3803         if (!intel_irqs_enabled(dev_priv))
3804                 return IRQ_NONE;
3805
3806         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3807         disable_rpm_wakeref_asserts(dev_priv);
3808
3809         iir = I915_READ(IIR);
3810         do {
3811                 bool irq_received = (iir) != 0;
3812                 bool blc_event = false;
3813
3814                 /* Can't rely on pipestat interrupt bit in iir as it might
3815                  * have been cleared after the pipestat interrupt was received.
3816                  * It doesn't set the bit in iir again, but it still produces
3817                  * interrupts (for non-MSI).
3818                  */
3819                 spin_lock(&dev_priv->irq_lock);
3820                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3821                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3822
3823                 for_each_pipe(dev_priv, pipe) {
3824                         i915_reg_t reg = PIPESTAT(pipe);
3825                         pipe_stats[pipe] = I915_READ(reg);
3826
3827                         /* Clear the PIPE*STAT regs before the IIR */
3828                         if (pipe_stats[pipe] & 0x8000ffff) {
3829                                 I915_WRITE(reg, pipe_stats[pipe]);
3830                                 irq_received = true;
3831                         }
3832                 }
3833                 spin_unlock(&dev_priv->irq_lock);
3834
3835                 if (!irq_received)
3836                         break;
3837
3838                 /* Consume port.  Then clear IIR or we'll miss events */
3839                 if (I915_HAS_HOTPLUG(dev_priv) &&
3840                     iir & I915_DISPLAY_PORT_INTERRUPT) {
3841                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3842                         if (hotplug_status)
3843                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3844                 }
3845
3846                 I915_WRITE(IIR, iir);
3847                 new_iir = I915_READ(IIR); /* Flush posted writes */
3848
3849                 if (iir & I915_USER_INTERRUPT)
3850                         notify_ring(dev_priv->engine[RCS]);
3851
3852                 for_each_pipe(dev_priv, pipe) {
3853                         int plane = pipe;
3854                         if (HAS_FBC(dev_priv))
3855                                 plane = !plane;
3856
3857                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
3858                                 drm_handle_vblank(&dev_priv->drm, pipe);
3859
3860                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3861                                 blc_event = true;
3862
3863                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3864                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3865
3866                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3867                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3868                                                                     pipe);
3869                 }
3870
3871                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3872                         intel_opregion_asle_intr(dev_priv);
3873
3874                 /* With MSI, interrupts are only generated when iir
3875                  * transitions from zero to nonzero.  If another bit got
3876                  * set while we were handling the existing iir bits, then
3877                  * we would never get another interrupt.
3878                  *
3879                  * This is fine on non-MSI as well, as if we hit this path
3880                  * we avoid exiting the interrupt handler only to generate
3881                  * another one.
3882                  *
3883                  * Note that for MSI this could cause a stray interrupt report
3884                  * if an interrupt landed in the time between writing IIR and
3885                  * the posting read.  This should be rare enough to never
3886                  * trigger the 99% of 100,000 interrupts test for disabling
3887                  * stray interrupts.
3888                  */
3889                 ret = IRQ_HANDLED;
3890                 iir = new_iir;
3891         } while (iir);
3892
3893         enable_rpm_wakeref_asserts(dev_priv);
3894
3895         return ret;
3896 }
3897
3898 static void i915_irq_uninstall(struct drm_device * dev)
3899 {
3900         struct drm_i915_private *dev_priv = to_i915(dev);
3901         int pipe;
3902
3903         if (I915_HAS_HOTPLUG(dev_priv)) {
3904                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3905                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3906         }
3907
3908         I915_WRITE16(HWSTAM, 0xffff);
3909         for_each_pipe(dev_priv, pipe) {
3910                 /* Clear enable bits; then clear status bits */
3911                 I915_WRITE(PIPESTAT(pipe), 0);
3912                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3913         }
3914         I915_WRITE(IMR, 0xffffffff);
3915         I915_WRITE(IER, 0x0);
3916
3917         I915_WRITE(IIR, I915_READ(IIR));
3918 }
3919
3920 static void i965_irq_preinstall(struct drm_device * dev)
3921 {
3922         struct drm_i915_private *dev_priv = to_i915(dev);
3923         int pipe;
3924
3925         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3926         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3927
3928         I915_WRITE(HWSTAM, 0xeffe);
3929         for_each_pipe(dev_priv, pipe)
3930                 I915_WRITE(PIPESTAT(pipe), 0);
3931         I915_WRITE(IMR, 0xffffffff);
3932         I915_WRITE(IER, 0x0);
3933         POSTING_READ(IER);
3934 }
3935
3936 static int i965_irq_postinstall(struct drm_device *dev)
3937 {
3938         struct drm_i915_private *dev_priv = to_i915(dev);
3939         u32 enable_mask;
3940         u32 error_mask;
3941
3942         /* Unmask the interrupts that we always want on. */
3943         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3944                                I915_DISPLAY_PORT_INTERRUPT |
3945                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3946                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3947                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3948                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3949                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3950
3951         enable_mask = ~dev_priv->irq_mask;
3952         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3953                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3954         enable_mask |= I915_USER_INTERRUPT;
3955
3956         if (IS_G4X(dev_priv))
3957                 enable_mask |= I915_BSD_USER_INTERRUPT;
3958
3959         /* Interrupt setup is already guaranteed to be single-threaded, this is
3960          * just to make the assert_spin_locked check happy. */
3961         spin_lock_irq(&dev_priv->irq_lock);
3962         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3963         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3964         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3965         spin_unlock_irq(&dev_priv->irq_lock);
3966
3967         /*
3968          * Enable some error detection, note the instruction error mask
3969          * bit is reserved, so we leave it masked.
3970          */
3971         if (IS_G4X(dev_priv)) {
3972                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3973                                GM45_ERROR_MEM_PRIV |
3974                                GM45_ERROR_CP_PRIV |
3975                                I915_ERROR_MEMORY_REFRESH);
3976         } else {
3977                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3978                                I915_ERROR_MEMORY_REFRESH);
3979         }
3980         I915_WRITE(EMR, error_mask);
3981
3982         I915_WRITE(IMR, dev_priv->irq_mask);
3983         I915_WRITE(IER, enable_mask);
3984         POSTING_READ(IER);
3985
3986         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3987         POSTING_READ(PORT_HOTPLUG_EN);
3988
3989         i915_enable_asle_pipestat(dev_priv);
3990
3991         return 0;
3992 }
3993
3994 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
3995 {
3996         u32 hotplug_en;
3997
3998         lockdep_assert_held(&dev_priv->irq_lock);
3999
4000         /* Note HDMI and DP share hotplug bits */
4001         /* enable bits are the same for all generations */
4002         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4003         /* Programming the CRT detection parameters tends
4004            to generate a spurious hotplug event about three
4005            seconds later.  So just do it once.
4006         */
4007         if (IS_G4X(dev_priv))
4008                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4009         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4010
4011         /* Ignore TV since it's buggy */
4012         i915_hotplug_interrupt_update_locked(dev_priv,
4013                                              HOTPLUG_INT_EN_MASK |
4014                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4015                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4016                                              hotplug_en);
4017 }
4018
4019 static irqreturn_t i965_irq_handler(int irq, void *arg)
4020 {
4021         struct drm_device *dev = arg;
4022         struct drm_i915_private *dev_priv = to_i915(dev);
4023         u32 iir, new_iir;
4024         u32 pipe_stats[I915_MAX_PIPES];
4025         int ret = IRQ_NONE, pipe;
4026
4027         if (!intel_irqs_enabled(dev_priv))
4028                 return IRQ_NONE;
4029
4030         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4031         disable_rpm_wakeref_asserts(dev_priv);
4032
4033         iir = I915_READ(IIR);
4034
4035         for (;;) {
4036                 bool irq_received = (iir) != 0;
4037                 bool blc_event = false;
4038
4039                 /* Can't rely on pipestat interrupt bit in iir as it might
4040                  * have been cleared after the pipestat interrupt was received.
4041                  * It doesn't set the bit in iir again, but it still produces
4042                  * interrupts (for non-MSI).
4043                  */
4044                 spin_lock(&dev_priv->irq_lock);
4045                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4046                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4047
4048                 for_each_pipe(dev_priv, pipe) {
4049                         i915_reg_t reg = PIPESTAT(pipe);
4050                         pipe_stats[pipe] = I915_READ(reg);
4051
4052                         /*
4053                          * Clear the PIPE*STAT regs before the IIR
4054                          */
4055                         if (pipe_stats[pipe] & 0x8000ffff) {
4056                                 I915_WRITE(reg, pipe_stats[pipe]);
4057                                 irq_received = true;
4058                         }
4059                 }
4060                 spin_unlock(&dev_priv->irq_lock);
4061
4062                 if (!irq_received)
4063                         break;
4064
4065                 ret = IRQ_HANDLED;
4066
4067                 /* Consume port.  Then clear IIR or we'll miss events */
4068                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4069                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4070                         if (hotplug_status)
4071                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4072                 }
4073
4074                 I915_WRITE(IIR, iir);
4075                 new_iir = I915_READ(IIR); /* Flush posted writes */
4076
4077                 if (iir & I915_USER_INTERRUPT)
4078                         notify_ring(dev_priv->engine[RCS]);
4079                 if (iir & I915_BSD_USER_INTERRUPT)
4080                         notify_ring(dev_priv->engine[VCS]);
4081
4082                 for_each_pipe(dev_priv, pipe) {
4083                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
4084                                 drm_handle_vblank(&dev_priv->drm, pipe);
4085
4086                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4087                                 blc_event = true;
4088
4089                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4090                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4091
4092                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4093                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4094                 }
4095
4096                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4097                         intel_opregion_asle_intr(dev_priv);
4098
4099                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4100                         gmbus_irq_handler(dev_priv);
4101
4102                 /* With MSI, interrupts are only generated when iir
4103                  * transitions from zero to nonzero.  If another bit got
4104                  * set while we were handling the existing iir bits, then
4105                  * we would never get another interrupt.
4106                  *
4107                  * This is fine on non-MSI as well, as if we hit this path
4108                  * we avoid exiting the interrupt handler only to generate
4109                  * another one.
4110                  *
4111                  * Note that for MSI this could cause a stray interrupt report
4112                  * if an interrupt landed in the time between writing IIR and
4113                  * the posting read.  This should be rare enough to never
4114                  * trigger the 99% of 100,000 interrupts test for disabling
4115                  * stray interrupts.
4116                  */
4117                 iir = new_iir;
4118         }
4119
4120         enable_rpm_wakeref_asserts(dev_priv);
4121
4122         return ret;
4123 }
4124
4125 static void i965_irq_uninstall(struct drm_device * dev)
4126 {
4127         struct drm_i915_private *dev_priv = to_i915(dev);
4128         int pipe;
4129
4130         if (!dev_priv)
4131                 return;
4132
4133         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4134         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4135
4136         I915_WRITE(HWSTAM, 0xffffffff);
4137         for_each_pipe(dev_priv, pipe)
4138                 I915_WRITE(PIPESTAT(pipe), 0);
4139         I915_WRITE(IMR, 0xffffffff);
4140         I915_WRITE(IER, 0x0);
4141
4142         for_each_pipe(dev_priv, pipe)
4143                 I915_WRITE(PIPESTAT(pipe),
4144                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4145         I915_WRITE(IIR, I915_READ(IIR));
4146 }
4147
4148 /**
4149  * intel_irq_init - initializes irq support
4150  * @dev_priv: i915 device instance
4151  *
4152  * This function initializes all the irq support including work items, timers
4153  * and all the vtables. It does not setup the interrupt itself though.
4154  */
4155 void intel_irq_init(struct drm_i915_private *dev_priv)
4156 {
4157         struct drm_device *dev = &dev_priv->drm;
4158         int i;
4159
4160         intel_hpd_init_work(dev_priv);
4161
4162         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4163
4164         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4165         for (i = 0; i < MAX_L3_SLICES; ++i)
4166                 dev_priv->l3_parity.remap_info[i] = NULL;
4167
4168         if (HAS_GUC_SCHED(dev_priv))
4169                 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4170
4171         /* Let's track the enabled rps events */
4172         if (IS_VALLEYVIEW(dev_priv))
4173                 /* WaGsvRC0ResidencyMethod:vlv */
4174                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4175         else
4176                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4177
4178         dev_priv->rps.pm_intrmsk_mbz = 0;
4179
4180         /*
4181          * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4182          * if GEN6_PM_UP_EI_EXPIRED is masked.
4183          *
4184          * TODO: verify if this can be reproduced on VLV,CHV.
4185          */
4186         if (INTEL_GEN(dev_priv) <= 7)
4187                 dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
4188
4189         if (INTEL_GEN(dev_priv) >= 8)
4190                 dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4191
4192         if (IS_GEN2(dev_priv)) {
4193                 /* Gen2 doesn't have a hardware frame counter */
4194                 dev->max_vblank_count = 0;
4195         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
4196                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4197                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4198         } else {
4199                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4200                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4201         }
4202
4203         /*
4204          * Opt out of the vblank disable timer on everything except gen2.
4205          * Gen2 doesn't have a hardware frame counter and so depends on
4206          * vblank interrupts to produce sane vblank seuquence numbers.
4207          */
4208         if (!IS_GEN2(dev_priv))
4209                 dev->vblank_disable_immediate = true;
4210
4211         /* Most platforms treat the display irq block as an always-on
4212          * power domain. vlv/chv can disable it at runtime and need
4213          * special care to avoid writing any of the display block registers
4214          * outside of the power domain. We defer setting up the display irqs
4215          * in this case to the runtime pm.
4216          */
4217         dev_priv->display_irqs_enabled = true;
4218         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4219                 dev_priv->display_irqs_enabled = false;
4220
4221         dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4222
4223         dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
4224         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4225
4226         if (IS_CHERRYVIEW(dev_priv)) {
4227                 dev->driver->irq_handler = cherryview_irq_handler;
4228                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4229                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4230                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4231                 dev->driver->enable_vblank = i965_enable_vblank;
4232                 dev->driver->disable_vblank = i965_disable_vblank;
4233                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4234         } else if (IS_VALLEYVIEW(dev_priv)) {
4235                 dev->driver->irq_handler = valleyview_irq_handler;
4236                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4237                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4238                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4239                 dev->driver->enable_vblank = i965_enable_vblank;
4240                 dev->driver->disable_vblank = i965_disable_vblank;
4241                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4242         } else if (INTEL_GEN(dev_priv) >= 8) {
4243                 dev->driver->irq_handler = gen8_irq_handler;
4244                 dev->driver->irq_preinstall = gen8_irq_reset;
4245                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4246                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4247                 dev->driver->enable_vblank = gen8_enable_vblank;
4248                 dev->driver->disable_vblank = gen8_disable_vblank;
4249                 if (IS_GEN9_LP(dev_priv))
4250                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4251                 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
4252                          HAS_PCH_CNP(dev_priv))
4253                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4254                 else
4255                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4256         } else if (HAS_PCH_SPLIT(dev_priv)) {
4257                 dev->driver->irq_handler = ironlake_irq_handler;
4258                 dev->driver->irq_preinstall = ironlake_irq_reset;
4259                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4260                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4261                 dev->driver->enable_vblank = ironlake_enable_vblank;
4262                 dev->driver->disable_vblank = ironlake_disable_vblank;
4263                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4264         } else {
4265                 if (IS_GEN2(dev_priv)) {
4266                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4267                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4268                         dev->driver->irq_handler = i8xx_irq_handler;
4269                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4270                         dev->driver->enable_vblank = i8xx_enable_vblank;
4271                         dev->driver->disable_vblank = i8xx_disable_vblank;
4272                 } else if (IS_GEN3(dev_priv)) {
4273                         dev->driver->irq_preinstall = i915_irq_preinstall;
4274                         dev->driver->irq_postinstall = i915_irq_postinstall;
4275                         dev->driver->irq_uninstall = i915_irq_uninstall;
4276                         dev->driver->irq_handler = i915_irq_handler;
4277                         dev->driver->enable_vblank = i8xx_enable_vblank;
4278                         dev->driver->disable_vblank = i8xx_disable_vblank;
4279                 } else {
4280                         dev->driver->irq_preinstall = i965_irq_preinstall;
4281                         dev->driver->irq_postinstall = i965_irq_postinstall;
4282                         dev->driver->irq_uninstall = i965_irq_uninstall;
4283                         dev->driver->irq_handler = i965_irq_handler;
4284                         dev->driver->enable_vblank = i965_enable_vblank;
4285                         dev->driver->disable_vblank = i965_disable_vblank;
4286                 }
4287                 if (I915_HAS_HOTPLUG(dev_priv))
4288                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4289         }
4290 }
4291
4292 /**
4293  * intel_irq_fini - deinitializes IRQ support
4294  * @i915: i915 device instance
4295  *
4296  * This function deinitializes all the IRQ support.
4297  */
4298 void intel_irq_fini(struct drm_i915_private *i915)
4299 {
4300         int i;
4301
4302         for (i = 0; i < MAX_L3_SLICES; ++i)
4303                 kfree(i915->l3_parity.remap_info[i]);
4304 }
4305
4306 /**
4307  * intel_irq_install - enables the hardware interrupt
4308  * @dev_priv: i915 device instance
4309  *
4310  * This function enables the hardware interrupt handling, but leaves the hotplug
4311  * handling still disabled. It is called after intel_irq_init().
4312  *
4313  * In the driver load and resume code we need working interrupts in a few places
4314  * but don't want to deal with the hassle of concurrent probe and hotplug
4315  * workers. Hence the split into this two-stage approach.
4316  */
4317 int intel_irq_install(struct drm_i915_private *dev_priv)
4318 {
4319         /*
4320          * We enable some interrupt sources in our postinstall hooks, so mark
4321          * interrupts as enabled _before_ actually enabling them to avoid
4322          * special cases in our ordering checks.
4323          */
4324         dev_priv->pm.irqs_enabled = true;
4325
4326         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4327 }
4328
4329 /**
4330  * intel_irq_uninstall - finilizes all irq handling
4331  * @dev_priv: i915 device instance
4332  *
4333  * This stops interrupt and hotplug handling and unregisters and frees all
4334  * resources acquired in the init functions.
4335  */
4336 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4337 {
4338         drm_irq_uninstall(&dev_priv->drm);
4339         intel_hpd_cancel_work(dev_priv);
4340         dev_priv->pm.irqs_enabled = false;
4341 }
4342
4343 /**
4344  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4345  * @dev_priv: i915 device instance
4346  *
4347  * This function is used to disable interrupts at runtime, both in the runtime
4348  * pm and the system suspend/resume code.
4349  */
4350 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4351 {
4352         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4353         dev_priv->pm.irqs_enabled = false;
4354         synchronize_irq(dev_priv->drm.irq);
4355 }
4356
4357 /**
4358  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4359  * @dev_priv: i915 device instance
4360  *
4361  * This function is used to enable interrupts at runtime, both in the runtime
4362  * pm and the system suspend/resume code.
4363  */
4364 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4365 {
4366         dev_priv->pm.irqs_enabled = true;
4367         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4368         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4369 }