2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
54 * The struct i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct i915_audio_component_ops *ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
63 } hdmi_audio_clock[] = {
64 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
67 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
69 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
72 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
76 /* HDMI N/CTS table */
77 #define TMDS_297M 297000
78 #define TMDS_296M 296703
79 #define TMDS_594M 594000
80 #define TMDS_593M 593407
88 { 44100, TMDS_296M, 4459, 234375 },
89 { 44100, TMDS_297M, 4704, 247500 },
90 { 48000, TMDS_296M, 5824, 281250 },
91 { 48000, TMDS_297M, 5120, 247500 },
92 { 32000, TMDS_296M, 5824, 421875 },
93 { 32000, TMDS_297M, 3072, 222750 },
94 { 88200, TMDS_296M, 8918, 234375 },
95 { 88200, TMDS_297M, 9408, 247500 },
96 { 96000, TMDS_296M, 11648, 281250 },
97 { 96000, TMDS_297M, 10240, 247500 },
98 { 176400, TMDS_296M, 17836, 234375 },
99 { 176400, TMDS_297M, 18816, 247500 },
100 { 192000, TMDS_296M, 23296, 281250 },
101 { 192000, TMDS_297M, 20480, 247500 },
102 { 44100, TMDS_593M, 8918, 937500 },
103 { 44100, TMDS_594M, 9408, 990000 },
104 { 48000, TMDS_593M, 5824, 562500 },
105 { 48000, TMDS_594M, 6144, 594000 },
106 { 32000, TMDS_593M, 5824, 843750 },
107 { 32000, TMDS_594M, 3072, 445500 },
108 { 88200, TMDS_593M, 17836, 937500 },
109 { 88200, TMDS_594M, 18816, 990000 },
110 { 96000, TMDS_593M, 11648, 562500 },
111 { 96000, TMDS_594M, 12288, 594000 },
112 { 176400, TMDS_593M, 35672, 937500 },
113 { 176400, TMDS_594M, 37632, 990000 },
114 { 192000, TMDS_593M, 23296, 562500 },
115 { 192000, TMDS_594M, 24576, 594000 },
118 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
119 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
123 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
124 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
128 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
129 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
130 adjusted_mode->crtc_clock);
134 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
135 hdmi_audio_clock[i].clock,
136 hdmi_audio_clock[i].config);
138 return hdmi_audio_clock[i].config;
141 static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
145 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
146 if ((rate == aud_ncts[i].sample_rate) &&
147 (mode->clock == aud_ncts[i].clock)) {
148 return aud_ncts[i].n;
154 static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
160 n_up = (n >> 12) & 0xff;
161 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
162 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
163 (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
164 AUD_CONFIG_N_PROG_ENABLE);
168 /* check whether N/CTS/M need be set manually */
169 static bool audio_rate_need_prog(struct intel_crtc *crtc,
170 const struct drm_display_mode *mode)
172 if (((mode->clock == TMDS_297M) ||
173 (mode->clock == TMDS_296M)) &&
174 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
180 static bool intel_eld_uptodate(struct drm_connector *connector,
181 int reg_eldv, uint32_t bits_eldv,
182 int reg_elda, uint32_t bits_elda,
185 struct drm_i915_private *dev_priv = connector->dev->dev_private;
186 uint8_t *eld = connector->eld;
190 tmp = I915_READ(reg_eldv);
196 tmp = I915_READ(reg_elda);
198 I915_WRITE(reg_elda, tmp);
200 for (i = 0; i < drm_eld_size(eld) / 4; i++)
201 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
207 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
209 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
212 DRM_DEBUG_KMS("Disable audio codec\n");
214 tmp = I915_READ(G4X_AUD_VID_DID);
215 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
216 eldv = G4X_ELDV_DEVCL_DEVBLC;
218 eldv = G4X_ELDV_DEVCTG;
221 tmp = I915_READ(G4X_AUD_CNTL_ST);
223 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
226 static void g4x_audio_codec_enable(struct drm_connector *connector,
227 struct intel_encoder *encoder,
228 const struct drm_display_mode *adjusted_mode)
230 struct drm_i915_private *dev_priv = connector->dev->dev_private;
231 uint8_t *eld = connector->eld;
236 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
238 tmp = I915_READ(G4X_AUD_VID_DID);
239 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
240 eldv = G4X_ELDV_DEVCL_DEVBLC;
242 eldv = G4X_ELDV_DEVCTG;
244 if (intel_eld_uptodate(connector,
245 G4X_AUD_CNTL_ST, eldv,
246 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
250 tmp = I915_READ(G4X_AUD_CNTL_ST);
251 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
252 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
253 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
255 len = min(drm_eld_size(eld) / 4, len);
256 DRM_DEBUG_DRIVER("ELD size %d\n", len);
257 for (i = 0; i < len; i++)
258 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
260 tmp = I915_READ(G4X_AUD_CNTL_ST);
262 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
265 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
267 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
268 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
269 enum pipe pipe = intel_crtc->pipe;
272 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
274 mutex_lock(&dev_priv->av_mutex);
276 /* Disable timestamps */
277 tmp = I915_READ(HSW_AUD_CFG(pipe));
278 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
279 tmp |= AUD_CONFIG_N_PROG_ENABLE;
280 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
281 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
282 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
283 tmp |= AUD_CONFIG_N_VALUE_INDEX;
284 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
287 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
288 tmp &= ~AUDIO_ELD_VALID(pipe);
289 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
290 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
292 mutex_unlock(&dev_priv->av_mutex);
295 static void hsw_audio_codec_enable(struct drm_connector *connector,
296 struct intel_encoder *encoder,
297 const struct drm_display_mode *adjusted_mode)
299 struct drm_i915_private *dev_priv = connector->dev->dev_private;
300 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
301 enum pipe pipe = intel_crtc->pipe;
302 struct i915_audio_component *acomp = dev_priv->audio_component;
303 const uint8_t *eld = connector->eld;
304 struct intel_digital_port *intel_dig_port =
305 enc_to_dig_port(&encoder->base);
306 enum port port = intel_dig_port->port;
311 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
312 pipe_name(pipe), drm_eld_size(eld));
314 mutex_lock(&dev_priv->av_mutex);
316 /* Enable audio presence detect, invalidate ELD */
317 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
318 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
319 tmp &= ~AUDIO_ELD_VALID(pipe);
320 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
323 * FIXME: We're supposed to wait for vblank here, but we have vblanks
324 * disabled during the mode set. The proper fix would be to push the
325 * rest of the setup into a vblank work item, queued here, but the
326 * infrastructure is not there yet.
329 /* Reset ELD write address */
330 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
331 tmp &= ~IBX_ELD_ADDRESS_MASK;
332 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
334 /* Up to 84 bytes of hw ELD buffer */
335 len = min(drm_eld_size(eld), 84);
336 for (i = 0; i < len / 4; i++)
337 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
340 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
341 tmp |= AUDIO_ELD_VALID(pipe);
342 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
344 /* Enable timestamps */
345 tmp = I915_READ(HSW_AUD_CFG(pipe));
346 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
347 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
348 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
349 tmp |= AUD_CONFIG_N_VALUE_INDEX;
351 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
353 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
354 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
357 else if (port >= PORT_A && port <= PORT_E)
358 rate = acomp->aud_sample_rate[port];
360 DRM_ERROR("invalid port: %d\n", port);
363 n = audio_config_get_n(adjusted_mode, rate);
365 tmp = audio_config_setup_n_reg(n, tmp);
367 DRM_DEBUG_KMS("no suitable N value is found\n");
370 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
372 mutex_unlock(&dev_priv->av_mutex);
375 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
377 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
378 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
379 struct intel_digital_port *intel_dig_port =
380 enc_to_dig_port(&encoder->base);
381 enum port port = intel_dig_port->port;
382 enum pipe pipe = intel_crtc->pipe;
387 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
388 port_name(port), pipe_name(pipe));
390 if (WARN_ON(port == PORT_A))
393 if (HAS_PCH_IBX(dev_priv->dev)) {
394 aud_config = IBX_AUD_CFG(pipe);
395 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
396 } else if (IS_VALLEYVIEW(dev_priv)) {
397 aud_config = VLV_AUD_CFG(pipe);
398 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
400 aud_config = CPT_AUD_CFG(pipe);
401 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
404 /* Disable timestamps */
405 tmp = I915_READ(aud_config);
406 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
407 tmp |= AUD_CONFIG_N_PROG_ENABLE;
408 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
409 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
410 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
411 tmp |= AUD_CONFIG_N_VALUE_INDEX;
412 I915_WRITE(aud_config, tmp);
414 eldv = IBX_ELD_VALID(port);
417 tmp = I915_READ(aud_cntrl_st2);
419 I915_WRITE(aud_cntrl_st2, tmp);
422 static void ilk_audio_codec_enable(struct drm_connector *connector,
423 struct intel_encoder *encoder,
424 const struct drm_display_mode *adjusted_mode)
426 struct drm_i915_private *dev_priv = connector->dev->dev_private;
427 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
428 struct intel_digital_port *intel_dig_port =
429 enc_to_dig_port(&encoder->base);
430 enum port port = intel_dig_port->port;
431 enum pipe pipe = intel_crtc->pipe;
432 uint8_t *eld = connector->eld;
441 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
442 port_name(port), pipe_name(pipe), drm_eld_size(eld));
444 if (WARN_ON(port == PORT_A))
448 * FIXME: We're supposed to wait for vblank here, but we have vblanks
449 * disabled during the mode set. The proper fix would be to push the
450 * rest of the setup into a vblank work item, queued here, but the
451 * infrastructure is not there yet.
454 if (HAS_PCH_IBX(connector->dev)) {
455 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
456 aud_config = IBX_AUD_CFG(pipe);
457 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
458 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
459 } else if (IS_VALLEYVIEW(connector->dev)) {
460 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
461 aud_config = VLV_AUD_CFG(pipe);
462 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
463 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
465 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
466 aud_config = CPT_AUD_CFG(pipe);
467 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
468 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
471 eldv = IBX_ELD_VALID(port);
474 tmp = I915_READ(aud_cntrl_st2);
476 I915_WRITE(aud_cntrl_st2, tmp);
478 /* Reset ELD write address */
479 tmp = I915_READ(aud_cntl_st);
480 tmp &= ~IBX_ELD_ADDRESS_MASK;
481 I915_WRITE(aud_cntl_st, tmp);
483 /* Up to 84 bytes of hw ELD buffer */
484 len = min(drm_eld_size(eld), 84);
485 for (i = 0; i < len / 4; i++)
486 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
489 tmp = I915_READ(aud_cntrl_st2);
491 I915_WRITE(aud_cntrl_st2, tmp);
493 /* Enable timestamps */
494 tmp = I915_READ(aud_config);
495 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
496 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
497 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
498 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
499 tmp |= AUD_CONFIG_N_VALUE_INDEX;
501 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
502 I915_WRITE(aud_config, tmp);
506 * intel_audio_codec_enable - Enable the audio codec for HD audio
507 * @intel_encoder: encoder on which to enable audio
509 * The enable sequences may only be performed after enabling the transcoder and
510 * port, and after completed link training.
512 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
514 struct drm_encoder *encoder = &intel_encoder->base;
515 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
516 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
517 struct drm_connector *connector;
518 struct drm_device *dev = encoder->dev;
519 struct drm_i915_private *dev_priv = dev->dev_private;
520 struct i915_audio_component *acomp = dev_priv->audio_component;
521 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
522 enum port port = intel_dig_port->port;
524 connector = drm_select_eld(encoder);
528 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
531 connector->encoder->base.id,
532 connector->encoder->name);
535 connector->eld[5] &= ~(3 << 2);
536 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
537 connector->eld[5] |= (1 << 2);
539 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
541 if (dev_priv->display.audio_codec_enable)
542 dev_priv->display.audio_codec_enable(connector, intel_encoder,
545 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
546 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
550 * intel_audio_codec_disable - Disable the audio codec for HD audio
551 * @intel_encoder: encoder on which to disable audio
553 * The disable sequences must be performed before disabling the transcoder or
556 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
558 struct drm_encoder *encoder = &intel_encoder->base;
559 struct drm_device *dev = encoder->dev;
560 struct drm_i915_private *dev_priv = dev->dev_private;
561 struct i915_audio_component *acomp = dev_priv->audio_component;
562 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
563 enum port port = intel_dig_port->port;
565 if (dev_priv->display.audio_codec_disable)
566 dev_priv->display.audio_codec_disable(intel_encoder);
568 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
569 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
573 * intel_init_audio - Set up chip specific audio functions
576 void intel_init_audio(struct drm_device *dev)
578 struct drm_i915_private *dev_priv = dev->dev_private;
581 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
582 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
583 } else if (IS_VALLEYVIEW(dev)) {
584 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
585 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
586 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
587 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
588 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
589 } else if (HAS_PCH_SPLIT(dev)) {
590 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
591 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
595 static void i915_audio_component_get_power(struct device *dev)
597 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
600 static void i915_audio_component_put_power(struct device *dev)
602 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
605 static void i915_audio_component_codec_wake_override(struct device *dev,
608 struct drm_i915_private *dev_priv = dev_to_i915(dev);
611 if (!IS_SKYLAKE(dev_priv))
615 * Enable/disable generating the codec wake signal, overriding the
616 * internal logic to generate the codec wake to controller.
618 tmp = I915_READ(HSW_AUD_CHICKENBIT);
619 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
620 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
621 usleep_range(1000, 1500);
624 tmp = I915_READ(HSW_AUD_CHICKENBIT);
625 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
626 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
627 usleep_range(1000, 1500);
631 /* Get CDCLK in kHz */
632 static int i915_audio_component_get_cdclk_freq(struct device *dev)
634 struct drm_i915_private *dev_priv = dev_to_i915(dev);
637 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
640 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
641 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
643 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
648 static int i915_audio_component_sync_audio_rate(struct device *dev,
651 struct drm_i915_private *dev_priv = dev_to_i915(dev);
652 struct drm_device *drm_dev = dev_priv->dev;
653 struct intel_encoder *intel_encoder;
654 struct intel_digital_port *intel_dig_port;
655 struct intel_crtc *crtc;
656 struct drm_display_mode *mode;
657 struct i915_audio_component *acomp = dev_priv->audio_component;
662 /* HSW, BDW SKL need this fix */
663 if (!IS_SKYLAKE(dev_priv) &&
664 !IS_BROADWELL(dev_priv) &&
665 !IS_HASWELL(dev_priv))
668 mutex_lock(&dev_priv->av_mutex);
669 /* 1. get the pipe */
670 for_each_intel_encoder(drm_dev, intel_encoder) {
671 if (intel_encoder->type != INTEL_OUTPUT_HDMI)
673 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
674 if (port == intel_dig_port->port) {
675 crtc = to_intel_crtc(intel_encoder->base.crtc);
677 DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__);
685 if (pipe == INVALID_PIPE) {
686 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
687 mutex_unlock(&dev_priv->av_mutex);
690 DRM_DEBUG_KMS("pipe %c connects port %c\n",
691 pipe_name(pipe), port_name(port));
692 mode = &crtc->config->base.adjusted_mode;
694 /* port must be valid now, otherwise the pipe will be invalid */
695 acomp->aud_sample_rate[port] = rate;
697 /* 2. check whether to set the N/CTS/M manually or not */
698 if (!audio_rate_need_prog(crtc, mode)) {
699 tmp = I915_READ(HSW_AUD_CFG(pipe));
700 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
701 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
702 mutex_unlock(&dev_priv->av_mutex);
706 n = audio_config_get_n(mode, rate);
708 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
710 tmp = I915_READ(HSW_AUD_CFG(pipe));
711 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
712 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
713 mutex_unlock(&dev_priv->av_mutex);
717 /* 3. set the N/CTS/M */
718 tmp = I915_READ(HSW_AUD_CFG(pipe));
719 tmp = audio_config_setup_n_reg(n, tmp);
720 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
722 mutex_unlock(&dev_priv->av_mutex);
726 static const struct i915_audio_component_ops i915_audio_component_ops = {
727 .owner = THIS_MODULE,
728 .get_power = i915_audio_component_get_power,
729 .put_power = i915_audio_component_put_power,
730 .codec_wake_override = i915_audio_component_codec_wake_override,
731 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
732 .sync_audio_rate = i915_audio_component_sync_audio_rate,
735 static int i915_audio_component_bind(struct device *i915_dev,
736 struct device *hda_dev, void *data)
738 struct i915_audio_component *acomp = data;
739 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
742 if (WARN_ON(acomp->ops || acomp->dev))
745 drm_modeset_lock_all(dev_priv->dev);
746 acomp->ops = &i915_audio_component_ops;
747 acomp->dev = i915_dev;
748 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
749 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
750 acomp->aud_sample_rate[i] = 0;
751 dev_priv->audio_component = acomp;
752 drm_modeset_unlock_all(dev_priv->dev);
757 static void i915_audio_component_unbind(struct device *i915_dev,
758 struct device *hda_dev, void *data)
760 struct i915_audio_component *acomp = data;
761 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
763 drm_modeset_lock_all(dev_priv->dev);
766 dev_priv->audio_component = NULL;
767 drm_modeset_unlock_all(dev_priv->dev);
770 static const struct component_ops i915_audio_component_bind_ops = {
771 .bind = i915_audio_component_bind,
772 .unbind = i915_audio_component_unbind,
776 * i915_audio_component_init - initialize and register the audio component
777 * @dev_priv: i915 device instance
779 * This will register with the component framework a child component which
780 * will bind dynamically to the snd_hda_intel driver's corresponding master
781 * component when the latter is registered. During binding the child
782 * initializes an instance of struct i915_audio_component which it receives
783 * from the master. The master can then start to use the interface defined by
784 * this struct. Each side can break the binding at any point by deregistering
785 * its own component after which each side's component unbind callback is
788 * We ignore any error during registration and continue with reduced
789 * functionality (i.e. without HDMI audio).
791 void i915_audio_component_init(struct drm_i915_private *dev_priv)
795 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
797 DRM_ERROR("failed to add audio component (%d)\n", ret);
798 /* continue with reduced functionality */
802 dev_priv->audio_component_registered = true;
806 * i915_audio_component_cleanup - deregister the audio component
807 * @dev_priv: i915 device instance
809 * Deregisters the audio component, breaking any existing binding to the
810 * corresponding snd_hda_intel driver's master component.
812 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
814 if (!dev_priv->audio_component_registered)
817 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
818 dev_priv->audio_component_registered = false;