drivers/gpu/drm/i915/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_drv.h"
  26
  27 #define CTM_COEFF_SIGN  (1ULL << 63)
  28
  29 #define CTM_COEFF_1_0   (1ULL << 32)
  30 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  31 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  32 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  33 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  34 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  36
  37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  38
  39 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  40 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  41
  42 #define LEGACY_LUT_LENGTH               256
  43
  44 /* Post offset values for RGB->YCBCR conversion */
  45 #define POSTOFF_RGB_TO_YUV_HI 0x800
  46 #define POSTOFF_RGB_TO_YUV_ME 0x100
  47 #define POSTOFF_RGB_TO_YUV_LO 0x800
  48
  49 /*
  50  * These values are direct register values specified in the Bspec,
  51  * for RGB->YUV conversion matrix (colorspace BT709)
  52  */
  53 #define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8
  54 #define CSC_RGB_TO_YUV_BU 0x37e80000
  55 #define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0
  56 #define CSC_RGB_TO_YUV_BY 0xb5280000
  57 #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
  58 #define CSC_RGB_TO_YUV_BV 0x1e080000
  59
  60 /*
  61  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  62  * format). This macro takes the coefficient we want transformed and the
  63  * number of fractional bits.
  64  *
  65  * We only have a 9 bits precision window which slides depending on the value
  66  * of the CTM coefficient and we write the value from bit 3. We also round the
  67  * value.
  68  */
  69 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  70         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  71
  72 #define ILK_CSC_COEFF_LIMITED_RANGE     \
  73         ILK_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
  74 #define ILK_CSC_COEFF_1_0               \
  75         ((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
  76
  77 static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
  78 {
  79         return !state->degamma_lut &&
  80                 !state->ctm &&
  81                 state->gamma_lut &&
  82                 drm_color_lut_size(state->gamma_lut) == LEGACY_LUT_LENGTH;
  83 }
  84
  85 /*
  86  * When using limited range, multiply the matrix given by userspace by
  87  * the matrix that we would use for the limited range.
  88  */
  89 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
  90 {
  91         int i;
  92
  93         for (i = 0; i < 9; i++) {
  94                 u64 user_coeff = input[i];
  95                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
  96                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
  97                                           CTM_COEFF_4_0 - 1) >> 2;
  98
  99                 /*
 100                  * By scaling every co-efficient with limited range (16-235)
 101                  * vs full range (0-255) the final o/p will be scaled down to
 102                  * fit in the limited range supported by the panel.
 103                  */
 104                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 105                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 106         }
 107
 108         return result;
 109 }
 110
 111 static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
 112 {
 113         int pipe = intel_crtc->pipe;
 114         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 115
 116         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 117         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 118         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 119
 120         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
 121         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
 122
 123         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
 124         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
 125
 126         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
 127         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
 128
 129         I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
 130         I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
 131         I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
 132         I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 133 }
 134
 135 static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
 136 {
 137         struct drm_crtc *crtc = crtc_state->crtc;
 138         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 140         int i, pipe = intel_crtc->pipe;
 141         uint16_t coeffs[9] = { 0, };
 142         struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
 143         bool limited_color_range = false;
 144
 145         /*
 146          * FIXME if there's a gamma LUT after the CSC, we should
 147          * do the range compression using the gamma LUT instead.
 148          */
 149         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
 150                 limited_color_range = intel_crtc_state->limited_color_range;
 151
 152         if (intel_crtc_state->ycbcr420) {
 153                 ilk_load_ycbcr_conversion_matrix(intel_crtc);
 154                 return;
 155         } else if (crtc_state->ctm) {
 156                 struct drm_color_ctm *ctm = crtc_state->ctm->data;
 157                 const u64 *input;
 158                 u64 temp[9];
 159
 160                 if (limited_color_range)
 161                         input = ctm_mult_by_limited(temp, ctm->matrix);
 162                 else
 163                         input = ctm->matrix;
 164
 165                 /*
 166                  * Convert fixed point S31.32 input to format supported by the
 167                  * hardware.
 168                  */
 169                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 170                         uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
 171
 172                         /*
 173                          * Clamp input value to min/max supported by
 174                          * hardware.
 175                          */
 176                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 177
 178                         /* sign bit */
 179                         if (CTM_COEFF_NEGATIVE(input[i]))
 180                                 coeffs[i] |= 1 << 15;
 181
 182                         if (abs_coeff < CTM_COEFF_0_125)
 183                                 coeffs[i] |= (3 << 12) |
 184                                         ILK_CSC_COEFF_FP(abs_coeff, 12);
 185                         else if (abs_coeff < CTM_COEFF_0_25)
 186                                 coeffs[i] |= (2 << 12) |
 187                                         ILK_CSC_COEFF_FP(abs_coeff, 11);
 188                         else if (abs_coeff < CTM_COEFF_0_5)
 189                                 coeffs[i] |= (1 << 12) |
 190                                         ILK_CSC_COEFF_FP(abs_coeff, 10);
 191                         else if (abs_coeff < CTM_COEFF_1_0)
 192                                 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 193                         else if (abs_coeff < CTM_COEFF_2_0)
 194                                 coeffs[i] |= (7 << 12) |
 195                                         ILK_CSC_COEFF_FP(abs_coeff, 8);
 196                         else
 197                                 coeffs[i] |= (6 << 12) |
 198                                         ILK_CSC_COEFF_FP(abs_coeff, 7);
 199                 }
 200         } else {
 201                 /*
 202                  * Load an identity matrix if no coefficients are provided.
 203                  *
 204                  * TODO: Check what kind of values actually come out of the
 205                  * pipe with these coeff/postoff values and adjust to get the
 206                  * best accuracy. Perhaps we even need to take the bpc value
 207                  * into consideration.
 208                  */
 209                 for (i = 0; i < 3; i++) {
 210                         if (limited_color_range)
 211                                 coeffs[i * 3 + i] =
 212                                         ILK_CSC_COEFF_LIMITED_RANGE;
 213                         else
 214                                 coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0;
 215                 }
 216         }
 217
 218         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
 219         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
 220
 221         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
 222         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
 223
 224         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
 225         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
 226
 227         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 228         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 229         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 230
 231         if (INTEL_GEN(dev_priv) > 6) {
 232                 uint16_t postoff = 0;
 233
 234                 if (limited_color_range)
 235                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
 236
 237                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
 238                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 239                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 240
 241                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 242         } else {
 243                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
 244
 245                 if (limited_color_range)
 246                         mode |= CSC_BLACK_SCREEN_OFFSET;
 247
 248                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
 249         }
 250 }
 251
 252 /*
 253  * Set up the pipe CSC unit on CherryView.
 254  */
 255 static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
 256 {
 257         struct drm_crtc *crtc = state->crtc;
 258         struct drm_device *dev = crtc->dev;
 259         struct drm_i915_private *dev_priv = to_i915(dev);
 260         int pipe = to_intel_crtc(crtc)->pipe;
 261         uint32_t mode;
 262
 263         if (state->ctm) {
 264                 struct drm_color_ctm *ctm = state->ctm->data;
 265                 uint16_t coeffs[9] = { 0, };
 266                 int i;
 267
 268                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 269                         uint64_t abs_coeff =
 270                                 ((1ULL << 63) - 1) & ctm->matrix[i];
 271
 272                         /* Round coefficient. */
 273                         abs_coeff += 1 << (32 - 13);
 274                         /* Clamp to hardware limits. */
 275                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 276
 277                         /* Write coefficients in S3.12 format. */
 278                         if (ctm->matrix[i] & (1ULL << 63))
 279                                 coeffs[i] = 1 << 15;
 280                         coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 281                         coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 282                 }
 283
 284                 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
 285                            coeffs[1] << 16 | coeffs[0]);
 286                 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
 287                            coeffs[3] << 16 | coeffs[2]);
 288                 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
 289                            coeffs[5] << 16 | coeffs[4]);
 290                 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
 291                            coeffs[7] << 16 | coeffs[6]);
 292                 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 293         }
 294
 295         mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
 296         if (!crtc_state_is_legacy_gamma(state)) {
 297                 mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
 298                         (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
 299         }
 300         I915_WRITE(CGM_PIPE_MODE(pipe), mode);
 301 }
 302
 303 void intel_color_set_csc(struct drm_crtc_state *crtc_state)
 304 {
 305         struct drm_device *dev = crtc_state->crtc->dev;
 306         struct drm_i915_private *dev_priv = to_i915(dev);
 307
 308         if (dev_priv->display.load_csc_matrix)
 309                 dev_priv->display.load_csc_matrix(crtc_state);
 310 }
 311
 312 /* Loads the legacy palette/gamma unit for the CRTC. */
 313 static void i9xx_load_luts_internal(struct drm_crtc *crtc,
 314                                     struct drm_property_blob *blob,
 315                                     struct intel_crtc_state *crtc_state)
 316 {
 317         struct drm_device *dev = crtc->dev;
 318         struct drm_i915_private *dev_priv = to_i915(dev);
 319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 320         enum pipe pipe = intel_crtc->pipe;
 321         int i;
 322
 323         if (HAS_GMCH_DISPLAY(dev_priv)) {
 324                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 325                         assert_dsi_pll_enabled(dev_priv);
 326                 else
 327                         assert_pll_enabled(dev_priv, pipe);
 328         }
 329
 330         if (blob) {
 331                 struct drm_color_lut *lut = blob->data;
 332                 for (i = 0; i < 256; i++) {
 333                         uint32_t word =
 334                                 (drm_color_lut_extract(lut[i].red, 8) << 16) |
 335                                 (drm_color_lut_extract(lut[i].green, 8) << 8) |
 336                                 drm_color_lut_extract(lut[i].blue, 8);
 337
 338                         if (HAS_GMCH_DISPLAY(dev_priv))
 339                                 I915_WRITE(PALETTE(pipe, i), word);
 340                         else
 341                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 342                 }
 343         } else {
 344                 for (i = 0; i < 256; i++) {
 345                         uint32_t word = (i << 16) | (i << 8) | i;
 346
 347                         if (HAS_GMCH_DISPLAY(dev_priv))
 348                                 I915_WRITE(PALETTE(pipe, i), word);
 349                         else
 350                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 351                 }
 352         }
 353 }
 354
 355 static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
 356 {
 357         i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
 358                                 to_intel_crtc_state(crtc_state));
 359 }
 360
 361 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
 362 static void haswell_load_luts(struct drm_crtc_state *crtc_state)
 363 {
 364         struct drm_crtc *crtc = crtc_state->crtc;
 365         struct drm_device *dev = crtc->dev;
 366         struct drm_i915_private *dev_priv = to_i915(dev);
 367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 368         struct intel_crtc_state *intel_crtc_state =
 369                 to_intel_crtc_state(crtc_state);
 370         bool reenable_ips = false;
 371
 372         /*
 373          * Workaround : Do not read or write the pipe palette/gamma data while
 374          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 375          */
 376         if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
 377             (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
 378                 hsw_disable_ips(intel_crtc_state);
 379                 reenable_ips = true;
 380         }
 381
 382         intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 383         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
 384
 385         i9xx_load_luts(crtc_state);
 386
 387         if (reenable_ips)
 388                 hsw_enable_ips(intel_crtc_state);
 389 }
 390
 391 static void bdw_load_degamma_lut(struct drm_crtc_state *state)
 392 {
 393         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 394         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 395         uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 396
 397         I915_WRITE(PREC_PAL_INDEX(pipe),
 398                    PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
 399
 400         if (state->degamma_lut) {
 401                 struct drm_color_lut *lut = state->degamma_lut->data;
 402
 403                 for (i = 0; i < lut_size; i++) {
 404                         uint32_t word =
 405                         drm_color_lut_extract(lut[i].red, 10) << 20 |
 406                         drm_color_lut_extract(lut[i].green, 10) << 10 |
 407                         drm_color_lut_extract(lut[i].blue, 10);
 408
 409                         I915_WRITE(PREC_PAL_DATA(pipe), word);
 410                 }
 411         } else {
 412                 for (i = 0; i < lut_size; i++) {
 413                         uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
 414
 415                         I915_WRITE(PREC_PAL_DATA(pipe),
 416                                    (v << 20) | (v << 10) | v);
 417                 }
 418         }
 419 }
 420
 421 static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
 422 {
 423         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 424         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 425         uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 426
 427         WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
 428
 429         I915_WRITE(PREC_PAL_INDEX(pipe),
 430                    (offset ? PAL_PREC_SPLIT_MODE : 0) |
 431                    PAL_PREC_AUTO_INCREMENT |
 432                    offset);
 433
 434         if (state->gamma_lut) {
 435                 struct drm_color_lut *lut = state->gamma_lut->data;
 436
 437                 for (i = 0; i < lut_size; i++) {
 438                         uint32_t word =
 439                         (drm_color_lut_extract(lut[i].red, 10) << 20) |
 440                         (drm_color_lut_extract(lut[i].green, 10) << 10) |
 441                         drm_color_lut_extract(lut[i].blue, 10);
 442
 443                         I915_WRITE(PREC_PAL_DATA(pipe), word);
 444                 }
 445
 446                 /* Program the max register to clamp values > 1.0. */
 447                 i = lut_size - 1;
 448                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
 449                            drm_color_lut_extract(lut[i].red, 16));
 450                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
 451                            drm_color_lut_extract(lut[i].green, 16));
 452                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
 453                            drm_color_lut_extract(lut[i].blue, 16));
 454         } else {
 455                 for (i = 0; i < lut_size; i++) {
 456                         uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
 457
 458                         I915_WRITE(PREC_PAL_DATA(pipe),
 459                                    (v << 20) | (v << 10) | v);
 460                 }
 461
 462                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
 463                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
 464                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
 465         }
 466 }
 467
 468 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
 469 static void broadwell_load_luts(struct drm_crtc_state *state)
 470 {
 471         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 472         struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 473         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 474
 475         if (crtc_state_is_legacy_gamma(state)) {
 476                 haswell_load_luts(state);
 477                 return;
 478         }
 479
 480         bdw_load_degamma_lut(state);
 481         bdw_load_gamma_lut(state,
 482                            INTEL_INFO(dev_priv)->color.degamma_lut_size);
 483
 484         intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
 485         I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
 486         POSTING_READ(GAMMA_MODE(pipe));
 487
 488         /*
 489          * Reset the index, otherwise it prevents the legacy palette to be
 490          * written properly.
 491          */
 492         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 493 }
 494
 495 static void glk_load_degamma_lut(struct drm_crtc_state *state)
 496 {
 497         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 498         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 499         const uint32_t lut_size = 33;
 500         uint32_t i;
 501
 502         /*
 503          * When setting the auto-increment bit, the hardware seems to
 504          * ignore the index bits, so we need to reset it to index 0
 505          * separately.
 506          */
 507         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 508         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 509
 510         /*
 511          *  FIXME: The pipe degamma table in geminilake doesn't support
 512          *  different values per channel, so this just loads a linear table.
 513          */
 514         for (i = 0; i < lut_size; i++) {
 515                 uint32_t v = (i * (1 << 16)) / (lut_size - 1);
 516
 517                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
 518         }
 519
 520         /* Clamp values > 1.0. */
 521         while (i++ < 35)
 522                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
 523 }
 524
 525 static void glk_load_luts(struct drm_crtc_state *state)
 526 {
 527         struct drm_crtc *crtc = state->crtc;
 528         struct drm_device *dev = crtc->dev;
 529         struct drm_i915_private *dev_priv = to_i915(dev);
 530         struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 531         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 532
 533         glk_load_degamma_lut(state);
 534
 535         if (crtc_state_is_legacy_gamma(state)) {
 536                 haswell_load_luts(state);
 537                 return;
 538         }
 539
 540         bdw_load_gamma_lut(state, 0);
 541
 542         intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
 543         I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
 544         POSTING_READ(GAMMA_MODE(pipe));
 545 }
 546
 547 /* Loads the palette/gamma unit for the CRTC on CherryView. */
 548 static void cherryview_load_luts(struct drm_crtc_state *state)
 549 {
 550         struct drm_crtc *crtc = state->crtc;
 551         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 552         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 553         struct drm_color_lut *lut;
 554         uint32_t i, lut_size;
 555         uint32_t word0, word1;
 556
 557         if (crtc_state_is_legacy_gamma(state)) {
 558                 /* Turn off degamma/gamma on CGM block. */
 559                 I915_WRITE(CGM_PIPE_MODE(pipe),
 560                            (state->ctm ? CGM_PIPE_MODE_CSC : 0));
 561                 i9xx_load_luts_internal(crtc, state->gamma_lut,
 562                                         to_intel_crtc_state(state));
 563                 return;
 564         }
 565
 566         if (state->degamma_lut) {
 567                 lut = state->degamma_lut->data;
 568                 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 569                 for (i = 0; i < lut_size; i++) {
 570                         /* Write LUT in U0.14 format. */
 571                         word0 =
 572                         (drm_color_lut_extract(lut[i].green, 14) << 16) |
 573                         drm_color_lut_extract(lut[i].blue, 14);
 574                         word1 = drm_color_lut_extract(lut[i].red, 14);
 575
 576                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
 577                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
 578                 }
 579         }
 580
 581         if (state->gamma_lut) {
 582                 lut = state->gamma_lut->data;
 583                 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 584                 for (i = 0; i < lut_size; i++) {
 585                         /* Write LUT in U0.10 format. */
 586                         word0 =
 587                         (drm_color_lut_extract(lut[i].green, 10) << 16) |
 588                         drm_color_lut_extract(lut[i].blue, 10);
 589                         word1 = drm_color_lut_extract(lut[i].red, 10);
 590
 591                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
 592                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
 593                 }
 594         }
 595
 596         I915_WRITE(CGM_PIPE_MODE(pipe),
 597                    (state->ctm ? CGM_PIPE_MODE_CSC : 0) |
 598                    (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
 599                    (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
 600
 601         /*
 602          * Also program a linear LUT in the legacy block (behind the
 603          * CGM block).
 604          */
 605         i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
 606 }
 607
 608 void intel_color_load_luts(struct drm_crtc_state *crtc_state)
 609 {
 610         struct drm_device *dev = crtc_state->crtc->dev;
 611         struct drm_i915_private *dev_priv = to_i915(dev);
 612
 613         dev_priv->display.load_luts(crtc_state);
 614 }
 615
 616 int intel_color_check(struct drm_crtc *crtc,
 617                       struct drm_crtc_state *crtc_state)
 618 {
 619         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 620         size_t gamma_length, degamma_length;
 621
 622         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 623         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 624
 625         /*
 626          * We allow both degamma & gamma luts at the right size or
 627          * NULL.
 628          */
 629         if ((!crtc_state->degamma_lut ||
 630              drm_color_lut_size(crtc_state->degamma_lut) == degamma_length) &&
 631             (!crtc_state->gamma_lut ||
 632              drm_color_lut_size(crtc_state->gamma_lut) == gamma_length))
 633                 return 0;
 634
 635         /*
 636          * We also allow no degamma lut/ctm and a gamma lut at the legacy
 637          * size (256 entries).
 638          */
 639         if (crtc_state_is_legacy_gamma(crtc_state))
 640                 return 0;
 641
 642         return -EINVAL;
 643 }
 644
 645 void intel_color_init(struct drm_crtc *crtc)
 646 {
 647         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 648
 649         drm_mode_crtc_set_gamma_size(crtc, 256);
 650
 651         if (IS_CHERRYVIEW(dev_priv)) {
 652                 dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
 653                 dev_priv->display.load_luts = cherryview_load_luts;
 654         } else if (IS_HASWELL(dev_priv)) {
 655                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 656                 dev_priv->display.load_luts = haswell_load_luts;
 657         } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
 658                    IS_BROXTON(dev_priv)) {
 659                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 660                 dev_priv->display.load_luts = broadwell_load_luts;
 661         } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 662                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 663                 dev_priv->display.load_luts = glk_load_luts;
 664         } else {
 665                 dev_priv->display.load_luts = i9xx_load_luts;
 666         }
 667
 668         /* Enable color management support when we have degamma & gamma LUTs. */
 669         if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
 670             INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
 671                 drm_crtc_enable_color_mgmt(crtc,
 672                                            INTEL_INFO(dev_priv)->color.degamma_lut_size,
 673                                            true,
 674                                            INTEL_INFO(dev_priv)->color.gamma_lut_size);
 675 }