drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 static const u8 index_to_dp_signal_levels[] = {
  38         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  39         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  40         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  41         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  42         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  43         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  44         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  45         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  46         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  47         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48 };
  49
  50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  51  * them for both DP and FDI transports, allowing those ports to
  52  * automatically adapt to HDMI connections as well
  53  */
  54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  55         { 0x00FFFFFF, 0x0006000E, 0x0 },
  56         { 0x00D75FFF, 0x0005000A, 0x0 },
  57         { 0x00C30FFF, 0x00040006, 0x0 },
  58         { 0x80AAAFFF, 0x000B0000, 0x0 },
  59         { 0x00FFFFFF, 0x0005000A, 0x0 },
  60         { 0x00D75FFF, 0x000C0004, 0x0 },
  61         { 0x80C30FFF, 0x000B0000, 0x0 },
  62         { 0x00FFFFFF, 0x00040006, 0x0 },
  63         { 0x80D75FFF, 0x000B0000, 0x0 },
  64 };
  65
  66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  67         { 0x00FFFFFF, 0x0007000E, 0x0 },
  68         { 0x00D75FFF, 0x000F000A, 0x0 },
  69         { 0x00C30FFF, 0x00060006, 0x0 },
  70         { 0x00AAAFFF, 0x001E0000, 0x0 },
  71         { 0x00FFFFFF, 0x000F000A, 0x0 },
  72         { 0x00D75FFF, 0x00160004, 0x0 },
  73         { 0x00C30FFF, 0x001E0000, 0x0 },
  74         { 0x00FFFFFF, 0x00060006, 0x0 },
  75         { 0x00D75FFF, 0x001E0000, 0x0 },
  76 };
  77
  78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  79                                         /* Idx  NT mV d T mV d  db      */
  80         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  81         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  82         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  83         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  84         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  85         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  86         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  87         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  88         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  89         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  90         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  91         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  92 };
  93
  94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  95         { 0x00FFFFFF, 0x00000012, 0x0 },
  96         { 0x00EBAFFF, 0x00020011, 0x0 },
  97         { 0x00C71FFF, 0x0006000F, 0x0 },
  98         { 0x00AAAFFF, 0x000E000A, 0x0 },
  99         { 0x00FFFFFF, 0x00020011, 0x0 },
 100         { 0x00DB6FFF, 0x0005000F, 0x0 },
 101         { 0x00BEEFFF, 0x000A000C, 0x0 },
 102         { 0x00FFFFFF, 0x0005000F, 0x0 },
 103         { 0x00DB6FFF, 0x000A000C, 0x0 },
 104 };
 105
 106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 107         { 0x00FFFFFF, 0x0007000E, 0x0 },
 108         { 0x00D75FFF, 0x000E000A, 0x0 },
 109         { 0x00BEFFFF, 0x00140006, 0x0 },
 110         { 0x80B2CFFF, 0x001B0002, 0x0 },
 111         { 0x00FFFFFF, 0x000E000A, 0x0 },
 112         { 0x00DB6FFF, 0x00160005, 0x0 },
 113         { 0x80C71FFF, 0x001A0002, 0x0 },
 114         { 0x00F7DFFF, 0x00180004, 0x0 },
 115         { 0x80D75FFF, 0x001B0002, 0x0 },
 116 };
 117
 118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 119         { 0x00FFFFFF, 0x0001000E, 0x0 },
 120         { 0x00D75FFF, 0x0004000A, 0x0 },
 121         { 0x00C30FFF, 0x00070006, 0x0 },
 122         { 0x00AAAFFF, 0x000C0000, 0x0 },
 123         { 0x00FFFFFF, 0x0004000A, 0x0 },
 124         { 0x00D75FFF, 0x00090004, 0x0 },
 125         { 0x00C30FFF, 0x000C0000, 0x0 },
 126         { 0x00FFFFFF, 0x00070006, 0x0 },
 127         { 0x00D75FFF, 0x000C0000, 0x0 },
 128 };
 129
 130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 131                                         /* Idx  NT mV d T mV df db      */
 132         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 133         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 134         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 135         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 136         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 137         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 138         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 139         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 140         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 141         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 142 };
 143
 144 /* Skylake H and S */
 145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 146         { 0x00002016, 0x000000A0, 0x0 },
 147         { 0x00005012, 0x0000009B, 0x0 },
 148         { 0x00007011, 0x00000088, 0x0 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x00002016, 0x0000009B, 0x0 },
 151         { 0x00005012, 0x00000088, 0x0 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x000000DF, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake U */
 158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 159         { 0x0000201B, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x1 },
 162         { 0x80009010, 0x000000C0, 0x1 },
 163         { 0x0000201B, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x1 },
 165         { 0x80007011, 0x000000C0, 0x1 },
 166         { 0x00002016, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x1 },
 168 };
 169
 170 /* Skylake Y */
 171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 172         { 0x00000018, 0x000000A2, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000CD, 0x3 },
 175         { 0x80009010, 0x000000C0, 0x3 },
 176         { 0x00000018, 0x0000009D, 0x0 },
 177         { 0x80005012, 0x000000C0, 0x3 },
 178         { 0x80007011, 0x000000C0, 0x3 },
 179         { 0x00000018, 0x00000088, 0x0 },
 180         { 0x80005012, 0x000000C0, 0x3 },
 181 };
 182
 183 /* Kabylake H and S */
 184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 185         { 0x00002016, 0x000000A0, 0x0 },
 186         { 0x00005012, 0x0000009B, 0x0 },
 187         { 0x00007011, 0x00000088, 0x0 },
 188         { 0x80009010, 0x000000C0, 0x1 },
 189         { 0x00002016, 0x0000009B, 0x0 },
 190         { 0x00005012, 0x00000088, 0x0 },
 191         { 0x80007011, 0x000000C0, 0x1 },
 192         { 0x00002016, 0x00000097, 0x0 },
 193         { 0x80005012, 0x000000C0, 0x1 },
 194 };
 195
 196 /* Kabylake U */
 197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 198         { 0x0000201B, 0x000000A1, 0x0 },
 199         { 0x00005012, 0x00000088, 0x0 },
 200         { 0x80007011, 0x000000CD, 0x3 },
 201         { 0x80009010, 0x000000C0, 0x3 },
 202         { 0x0000201B, 0x0000009D, 0x0 },
 203         { 0x80005012, 0x000000C0, 0x3 },
 204         { 0x80007011, 0x000000C0, 0x3 },
 205         { 0x00002016, 0x0000004F, 0x0 },
 206         { 0x80005012, 0x000000C0, 0x3 },
 207 };
 208
 209 /* Kabylake Y */
 210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 211         { 0x00001017, 0x000000A1, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000CD, 0x3 },
 214         { 0x8000800F, 0x000000C0, 0x3 },
 215         { 0x00001017, 0x0000009D, 0x0 },
 216         { 0x80005012, 0x000000C0, 0x3 },
 217         { 0x80007011, 0x000000C0, 0x3 },
 218         { 0x00001017, 0x0000004C, 0x0 },
 219         { 0x80005012, 0x000000C0, 0x3 },
 220 };
 221
 222 /*
 223  * Skylake/Kabylake H and S
 224  * eDP 1.4 low vswing translation parameters
 225  */
 226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 227         { 0x00000018, 0x000000A8, 0x0 },
 228         { 0x00004013, 0x000000A9, 0x0 },
 229         { 0x00007011, 0x000000A2, 0x0 },
 230         { 0x00009010, 0x0000009C, 0x0 },
 231         { 0x00000018, 0x000000A9, 0x0 },
 232         { 0x00006013, 0x000000A2, 0x0 },
 233         { 0x00007011, 0x000000A6, 0x0 },
 234         { 0x00000018, 0x000000AB, 0x0 },
 235         { 0x00007013, 0x0000009F, 0x0 },
 236         { 0x00000018, 0x000000DF, 0x0 },
 237 };
 238
 239 /*
 240  * Skylake/Kabylake U
 241  * eDP 1.4 low vswing translation parameters
 242  */
 243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 244         { 0x00000018, 0x000000A8, 0x0 },
 245         { 0x00004013, 0x000000A9, 0x0 },
 246         { 0x00007011, 0x000000A2, 0x0 },
 247         { 0x00009010, 0x0000009C, 0x0 },
 248         { 0x00000018, 0x000000A9, 0x0 },
 249         { 0x00006013, 0x000000A2, 0x0 },
 250         { 0x00007011, 0x000000A6, 0x0 },
 251         { 0x00002016, 0x000000AB, 0x0 },
 252         { 0x00005013, 0x0000009F, 0x0 },
 253         { 0x00000018, 0x000000DF, 0x0 },
 254 };
 255
 256 /*
 257  * Skylake/Kabylake Y
 258  * eDP 1.4 low vswing translation parameters
 259  */
 260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 261         { 0x00000018, 0x000000A8, 0x0 },
 262         { 0x00004013, 0x000000AB, 0x0 },
 263         { 0x00007011, 0x000000A4, 0x0 },
 264         { 0x00009010, 0x000000DF, 0x0 },
 265         { 0x00000018, 0x000000AA, 0x0 },
 266         { 0x00006013, 0x000000A4, 0x0 },
 267         { 0x00007011, 0x0000009D, 0x0 },
 268         { 0x00000018, 0x000000A0, 0x0 },
 269         { 0x00006012, 0x000000DF, 0x0 },
 270         { 0x00000018, 0x0000008A, 0x0 },
 271 };
 272
 273 /* Skylake/Kabylake U, H and S */
 274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 275         { 0x00000018, 0x000000AC, 0x0 },
 276         { 0x00005012, 0x0000009D, 0x0 },
 277         { 0x00007011, 0x00000088, 0x0 },
 278         { 0x00000018, 0x000000A1, 0x0 },
 279         { 0x00000018, 0x00000098, 0x0 },
 280         { 0x00004013, 0x00000088, 0x0 },
 281         { 0x80006012, 0x000000CD, 0x1 },
 282         { 0x00000018, 0x000000DF, 0x0 },
 283         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 284         { 0x80003015, 0x000000C0, 0x1 },
 285         { 0x80000018, 0x000000C0, 0x1 },
 286 };
 287
 288 /* Skylake/Kabylake Y */
 289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 290         { 0x00000018, 0x000000A1, 0x0 },
 291         { 0x00005012, 0x000000DF, 0x0 },
 292         { 0x80007011, 0x000000CB, 0x3 },
 293         { 0x00000018, 0x000000A4, 0x0 },
 294         { 0x00000018, 0x0000009D, 0x0 },
 295         { 0x00004013, 0x00000080, 0x0 },
 296         { 0x80006013, 0x000000C0, 0x3 },
 297         { 0x00000018, 0x0000008A, 0x0 },
 298         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 299         { 0x80003015, 0x000000C0, 0x3 },
 300         { 0x80000018, 0x000000C0, 0x3 },
 301 };
 302
 303 struct bxt_ddi_buf_trans {
 304         u32 margin;     /* swing value */
 305         u32 scale;      /* scale value */
 306         u32 enable;     /* scale enable */
 307         u32 deemphasis;
 308         bool default_index; /* true if the entry represents default value */
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 328         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 330         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 331         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 332         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 334         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 335         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u32 dw2_swing_sel;
 358         u32 dw7_n_scalar;
 359         u32 dw4_cursor_coeff;
 360         u32 dw4_post_cursor_2;
 361         u32 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 497 {
 498         switch (encoder->type) {
 499         case INTEL_OUTPUT_DP_MST:
 500                 return enc_to_mst(&encoder->base)->primary->port;
 501         case INTEL_OUTPUT_DP:
 502         case INTEL_OUTPUT_EDP:
 503         case INTEL_OUTPUT_HDMI:
 504         case INTEL_OUTPUT_UNKNOWN:
 505                 return enc_to_dig_port(&encoder->base)->port;
 506         case INTEL_OUTPUT_ANALOG:
 507                 return PORT_E;
 508         default:
 509                 MISSING_CASE(encoder->type);
 510                 return PORT_A;
 511         }
 512 }
 513
 514 static const struct ddi_buf_trans *
 515 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 516 {
 517         if (dev_priv->vbt.edp.low_vswing) {
 518                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 519                 return bdw_ddi_translations_edp;
 520         } else {
 521                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 522                 return bdw_ddi_translations_dp;
 523         }
 524 }
 525
 526 static const struct ddi_buf_trans *
 527 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 528 {
 529         if (IS_SKL_ULX(dev_priv)) {
 530                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 531                 return skl_y_ddi_translations_dp;
 532         } else if (IS_SKL_ULT(dev_priv)) {
 533                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 534                 return skl_u_ddi_translations_dp;
 535         } else {
 536                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 537                 return skl_ddi_translations_dp;
 538         }
 539 }
 540
 541 static const struct ddi_buf_trans *
 542 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 543 {
 544         if (IS_KBL_ULX(dev_priv)) {
 545                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 546                 return kbl_y_ddi_translations_dp;
 547         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 548                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 549                 return kbl_u_ddi_translations_dp;
 550         } else {
 551                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 552                 return kbl_ddi_translations_dp;
 553         }
 554 }
 555
 556 static const struct ddi_buf_trans *
 557 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 558 {
 559         if (dev_priv->vbt.edp.low_vswing) {
 560                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 561                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 562                         return skl_y_ddi_translations_edp;
 563                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 564                            IS_CFL_ULT(dev_priv)) {
 565                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 566                         return skl_u_ddi_translations_edp;
 567                 } else {
 568                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 569                         return skl_ddi_translations_edp;
 570                 }
 571         }
 572
 573         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 574                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 575         else
 576                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 577 }
 578
 579 static const struct ddi_buf_trans *
 580 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 581 {
 582         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 583                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 584                 return skl_y_ddi_translations_hdmi;
 585         } else {
 586                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 587                 return skl_ddi_translations_hdmi;
 588         }
 589 }
 590
 591 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 592 {
 593         int n_hdmi_entries;
 594         int hdmi_level;
 595         int hdmi_default_entry;
 596
 597         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 598
 599         if (IS_GEN9_LP(dev_priv))
 600                 return hdmi_level;
 601
 602         if (IS_GEN9_BC(dev_priv)) {
 603                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 604                 hdmi_default_entry = 8;
 605         } else if (IS_BROADWELL(dev_priv)) {
 606                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 607                 hdmi_default_entry = 7;
 608         } else if (IS_HASWELL(dev_priv)) {
 609                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 610                 hdmi_default_entry = 6;
 611         } else {
 612                 WARN(1, "ddi translation table missing\n");
 613                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 614                 hdmi_default_entry = 7;
 615         }
 616
 617         /* Choose a good default if VBT is badly populated */
 618         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 619             hdmi_level >= n_hdmi_entries)
 620                 hdmi_level = hdmi_default_entry;
 621
 622         return hdmi_level;
 623 }
 624
 625 static const struct ddi_buf_trans *
 626 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 627                            int *n_entries)
 628 {
 629         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 630                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 631         } else if (IS_SKYLAKE(dev_priv)) {
 632                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 633         } else if (IS_BROADWELL(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 635                 return  bdw_ddi_translations_dp;
 636         } else if (IS_HASWELL(dev_priv)) {
 637                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 638                 return hsw_ddi_translations_dp;
 639         }
 640
 641         *n_entries = 0;
 642         return NULL;
 643 }
 644
 645 static const struct ddi_buf_trans *
 646 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 647                             int *n_entries)
 648 {
 649         if (IS_GEN9_BC(dev_priv)) {
 650                 return skl_get_buf_trans_edp(dev_priv, n_entries);
 651         } else if (IS_BROADWELL(dev_priv)) {
 652                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 653         } else if (IS_HASWELL(dev_priv)) {
 654                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 655                 return hsw_ddi_translations_dp;
 656         }
 657
 658         *n_entries = 0;
 659         return NULL;
 660 }
 661
 662 static const struct ddi_buf_trans *
 663 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 664                             int *n_entries)
 665 {
 666         if (IS_BROADWELL(dev_priv)) {
 667                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 668                 return bdw_ddi_translations_fdi;
 669         } else if (IS_HASWELL(dev_priv)) {
 670                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 671                 return hsw_ddi_translations_fdi;
 672         }
 673
 674         *n_entries = 0;
 675         return NULL;
 676 }
 677
 678 /*
 679  * Starting with Haswell, DDI port buffers must be programmed with correct
 680  * values in advance. This function programs the correct values for
 681  * DP/eDP/FDI use cases.
 682  */
 683 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 684 {
 685         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 686         u32 iboost_bit = 0;
 687         int i, n_entries;
 688         enum port port = intel_ddi_get_encoder_port(encoder);
 689         const struct ddi_buf_trans *ddi_translations;
 690
 691         if (IS_GEN9_LP(dev_priv))
 692                 return;
 693
 694         switch (encoder->type) {
 695         case INTEL_OUTPUT_EDP:
 696                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
 697                                                                &n_entries);
 698                 break;
 699         case INTEL_OUTPUT_DP:
 700                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
 701                                                               &n_entries);
 702                 break;
 703         case INTEL_OUTPUT_ANALOG:
 704                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 705                                                                &n_entries);
 706                 break;
 707         default:
 708                 MISSING_CASE(encoder->type);
 709                 return;
 710         }
 711
 712         if (IS_GEN9_BC(dev_priv)) {
 713                 /* If we're boosting the current, set bit 31 of trans1 */
 714                 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 715                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 716
 717                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 718                             port != PORT_A && port != PORT_E &&
 719                             n_entries > 9))
 720                         n_entries = 9;
 721         }
 722
 723         for (i = 0; i < n_entries; i++) {
 724                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 725                            ddi_translations[i].trans1 | iboost_bit);
 726                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 727                            ddi_translations[i].trans2);
 728         }
 729 }
 730
 731 /*
 732  * Starting with Haswell, DDI port buffers must be programmed with correct
 733  * values in advance. This function programs the correct values for
 734  * HDMI/DVI use cases.
 735  */
 736 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 737 {
 738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 739         u32 iboost_bit = 0;
 740         int n_hdmi_entries, hdmi_level;
 741         enum port port = intel_ddi_get_encoder_port(encoder);
 742         const struct ddi_buf_trans *ddi_translations_hdmi;
 743
 744         if (IS_GEN9_LP(dev_priv))
 745                 return;
 746
 747         hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
 748
 749         if (IS_GEN9_BC(dev_priv)) {
 750                 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 751
 752                 /* If we're boosting the current, set bit 31 of trans1 */
 753                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 754                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 755         } else if (IS_BROADWELL(dev_priv)) {
 756                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 757                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 758         } else if (IS_HASWELL(dev_priv)) {
 759                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 760                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 761         } else {
 762                 WARN(1, "ddi translation table missing\n");
 763                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 764                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 765         }
 766
 767         /* Entry 9 is for HDMI: */
 768         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 769                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 770         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 771                    ddi_translations_hdmi[hdmi_level].trans2);
 772 }
 773
 774 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 775                                     enum port port)
 776 {
 777         i915_reg_t reg = DDI_BUF_CTL(port);
 778         int i;
 779
 780         for (i = 0; i < 16; i++) {
 781                 udelay(1);
 782                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 783                         return;
 784         }
 785         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 786 }
 787
 788 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
 789 {
 790         switch (pll->id) {
 791         case DPLL_ID_WRPLL1:
 792                 return PORT_CLK_SEL_WRPLL1;
 793         case DPLL_ID_WRPLL2:
 794                 return PORT_CLK_SEL_WRPLL2;
 795         case DPLL_ID_SPLL:
 796                 return PORT_CLK_SEL_SPLL;
 797         case DPLL_ID_LCPLL_810:
 798                 return PORT_CLK_SEL_LCPLL_810;
 799         case DPLL_ID_LCPLL_1350:
 800                 return PORT_CLK_SEL_LCPLL_1350;
 801         case DPLL_ID_LCPLL_2700:
 802                 return PORT_CLK_SEL_LCPLL_2700;
 803         default:
 804                 MISSING_CASE(pll->id);
 805                 return PORT_CLK_SEL_NONE;
 806         }
 807 }
 808
 809 /* Starting with Haswell, different DDI ports can work in FDI mode for
 810  * connection to the PCH-located connectors. For this, it is necessary to train
 811  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 812  *
 813  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 814  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 815  * DDI A (which is used for eDP)
 816  */
 817
 818 void hsw_fdi_link_train(struct intel_crtc *crtc,
 819                         const struct intel_crtc_state *crtc_state)
 820 {
 821         struct drm_device *dev = crtc->base.dev;
 822         struct drm_i915_private *dev_priv = to_i915(dev);
 823         struct intel_encoder *encoder;
 824         u32 temp, i, rx_ctl_val, ddi_pll_sel;
 825
 826         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 827                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 828                 intel_prepare_dp_ddi_buffers(encoder);
 829         }
 830
 831         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 832          * mode set "sequence for CRT port" document:
 833          * - TP1 to TP2 time with the default value
 834          * - FDI delay to 90h
 835          *
 836          * WaFDIAutoLinkSetTimingOverrride:hsw
 837          */
 838         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 839                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 840                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 841
 842         /* Enable the PCH Receiver FDI PLL */
 843         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 844                      FDI_RX_PLL_ENABLE |
 845                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
 846         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 847         POSTING_READ(FDI_RX_CTL(PIPE_A));
 848         udelay(220);
 849
 850         /* Switch from Rawclk to PCDclk */
 851         rx_ctl_val |= FDI_PCDCLK;
 852         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 853
 854         /* Configure Port Clock Select */
 855         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
 856         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
 857         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
 858
 859         /* Start the training iterating through available voltages and emphasis,
 860          * testing each value twice. */
 861         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 862                 /* Configure DP_TP_CTL with auto-training */
 863                 I915_WRITE(DP_TP_CTL(PORT_E),
 864                                         DP_TP_CTL_FDI_AUTOTRAIN |
 865                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 866                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 867                                         DP_TP_CTL_ENABLE);
 868
 869                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 870                  * DDI E does not support port reversal, the functionality is
 871                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 872                  * port reversal bit */
 873                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 874                            DDI_BUF_CTL_ENABLE |
 875                            ((crtc_state->fdi_lanes - 1) << 1) |
 876                            DDI_BUF_TRANS_SELECT(i / 2));
 877                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 878
 879                 udelay(600);
 880
 881                 /* Program PCH FDI Receiver TU */
 882                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 883
 884                 /* Enable PCH FDI Receiver with auto-training */
 885                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 886                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 887                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 888
 889                 /* Wait for FDI receiver lane calibration */
 890                 udelay(30);
 891
 892                 /* Unset FDI_RX_MISC pwrdn lanes */
 893                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 894                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 895                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 896                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 897
 898                 /* Wait for FDI auto training time */
 899                 udelay(5);
 900
 901                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 902                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 903                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 904                         break;
 905                 }
 906
 907                 /*
 908                  * Leave things enabled even if we failed to train FDI.
 909                  * Results in less fireworks from the state checker.
 910                  */
 911                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 912                         DRM_ERROR("FDI link training failed!\n");
 913                         break;
 914                 }
 915
 916                 rx_ctl_val &= ~FDI_RX_ENABLE;
 917                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 918                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 919
 920                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 921                 temp &= ~DDI_BUF_CTL_ENABLE;
 922                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 923                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 924
 925                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 926                 temp = I915_READ(DP_TP_CTL(PORT_E));
 927                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 928                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 929                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 930                 POSTING_READ(DP_TP_CTL(PORT_E));
 931
 932                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 933
 934                 /* Reset FDI_RX_MISC pwrdn lanes */
 935                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 936                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 937                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 938                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 939                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 940         }
 941
 942         /* Enable normal pixel sending for FDI */
 943         I915_WRITE(DP_TP_CTL(PORT_E),
 944                    DP_TP_CTL_FDI_AUTOTRAIN |
 945                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 946                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 947                    DP_TP_CTL_ENABLE);
 948 }
 949
 950 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 951 {
 952         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 953         struct intel_digital_port *intel_dig_port =
 954                 enc_to_dig_port(&encoder->base);
 955
 956         intel_dp->DP = intel_dig_port->saved_port_bits |
 957                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 958         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 959 }
 960
 961 static struct intel_encoder *
 962 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
 963 {
 964         struct drm_device *dev = crtc->base.dev;
 965         struct intel_encoder *encoder, *ret = NULL;
 966         int num_encoders = 0;
 967
 968         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 969                 ret = encoder;
 970                 num_encoders++;
 971         }
 972
 973         if (num_encoders != 1)
 974                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 975                      pipe_name(crtc->pipe));
 976
 977         BUG_ON(ret == NULL);
 978         return ret;
 979 }
 980
 981 /* Finds the only possible encoder associated with the given CRTC. */
 982 struct intel_encoder *
 983 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 986         struct intel_encoder *ret = NULL;
 987         struct drm_atomic_state *state;
 988         struct drm_connector *connector;
 989         struct drm_connector_state *connector_state;
 990         int num_encoders = 0;
 991         int i;
 992
 993         state = crtc_state->base.state;
 994
 995         for_each_new_connector_in_state(state, connector, connector_state, i) {
 996                 if (connector_state->crtc != crtc_state->base.crtc)
 997                         continue;
 998
 999                 ret = to_intel_encoder(connector_state->best_encoder);
1000                 num_encoders++;
1001         }
1002
1003         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1004              pipe_name(crtc->pipe));
1005
1006         BUG_ON(ret == NULL);
1007         return ret;
1008 }
1009
1010 #define LC_FREQ 2700
1011
1012 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1013                                    i915_reg_t reg)
1014 {
1015         int refclk = LC_FREQ;
1016         int n, p, r;
1017         u32 wrpll;
1018
1019         wrpll = I915_READ(reg);
1020         switch (wrpll & WRPLL_PLL_REF_MASK) {
1021         case WRPLL_PLL_SSC:
1022         case WRPLL_PLL_NON_SSC:
1023                 /*
1024                  * We could calculate spread here, but our checking
1025                  * code only cares about 5% accuracy, and spread is a max of
1026                  * 0.5% downspread.
1027                  */
1028                 refclk = 135;
1029                 break;
1030         case WRPLL_PLL_LCPLL:
1031                 refclk = LC_FREQ;
1032                 break;
1033         default:
1034                 WARN(1, "bad wrpll refclk\n");
1035                 return 0;
1036         }
1037
1038         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1039         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1040         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1041
1042         /* Convert to KHz, p & r have a fixed point portion */
1043         return (refclk * n * 100) / (p * r);
1044 }
1045
1046 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1047                                uint32_t dpll)
1048 {
1049         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1050         uint32_t cfgcr1_val, cfgcr2_val;
1051         uint32_t p0, p1, p2, dco_freq;
1052
1053         cfgcr1_reg = DPLL_CFGCR1(dpll);
1054         cfgcr2_reg = DPLL_CFGCR2(dpll);
1055
1056         cfgcr1_val = I915_READ(cfgcr1_reg);
1057         cfgcr2_val = I915_READ(cfgcr2_reg);
1058
1059         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1060         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1061
1062         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1063                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1064         else
1065                 p1 = 1;
1066
1067
1068         switch (p0) {
1069         case DPLL_CFGCR2_PDIV_1:
1070                 p0 = 1;
1071                 break;
1072         case DPLL_CFGCR2_PDIV_2:
1073                 p0 = 2;
1074                 break;
1075         case DPLL_CFGCR2_PDIV_3:
1076                 p0 = 3;
1077                 break;
1078         case DPLL_CFGCR2_PDIV_7:
1079                 p0 = 7;
1080                 break;
1081         }
1082
1083         switch (p2) {
1084         case DPLL_CFGCR2_KDIV_5:
1085                 p2 = 5;
1086                 break;
1087         case DPLL_CFGCR2_KDIV_2:
1088                 p2 = 2;
1089                 break;
1090         case DPLL_CFGCR2_KDIV_3:
1091                 p2 = 3;
1092                 break;
1093         case DPLL_CFGCR2_KDIV_1:
1094                 p2 = 1;
1095                 break;
1096         }
1097
1098         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1099
1100         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1101                 1000) / 0x8000;
1102
1103         return dco_freq / (p0 * p1 * p2 * 5);
1104 }
1105
1106 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1107                                uint32_t pll_id)
1108 {
1109         uint32_t cfgcr0, cfgcr1;
1110         uint32_t p0, p1, p2, dco_freq, ref_clock;
1111
1112         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1113         cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1114
1115         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1116         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1117
1118         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1119                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1120                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1121         else
1122                 p1 = 1;
1123
1124
1125         switch (p0) {
1126         case DPLL_CFGCR1_PDIV_2:
1127                 p0 = 2;
1128                 break;
1129         case DPLL_CFGCR1_PDIV_3:
1130                 p0 = 3;
1131                 break;
1132         case DPLL_CFGCR1_PDIV_5:
1133                 p0 = 5;
1134                 break;
1135         case DPLL_CFGCR1_PDIV_7:
1136                 p0 = 7;
1137                 break;
1138         }
1139
1140         switch (p2) {
1141         case DPLL_CFGCR1_KDIV_1:
1142                 p2 = 1;
1143                 break;
1144         case DPLL_CFGCR1_KDIV_2:
1145                 p2 = 2;
1146                 break;
1147         case DPLL_CFGCR1_KDIV_4:
1148                 p2 = 4;
1149                 break;
1150         }
1151
1152         ref_clock = dev_priv->cdclk.hw.ref;
1153
1154         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1155
1156         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1157                       DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
1158
1159         return dco_freq / (p0 * p1 * p2 * 5);
1160 }
1161
1162 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1163 {
1164         int dotclock;
1165
1166         if (pipe_config->has_pch_encoder)
1167                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1168                                                     &pipe_config->fdi_m_n);
1169         else if (intel_crtc_has_dp_encoder(pipe_config))
1170                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1171                                                     &pipe_config->dp_m_n);
1172         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1173                 dotclock = pipe_config->port_clock * 2 / 3;
1174         else
1175                 dotclock = pipe_config->port_clock;
1176
1177         if (pipe_config->ycbcr420)
1178                 dotclock *= 2;
1179
1180         if (pipe_config->pixel_multiplier)
1181                 dotclock /= pipe_config->pixel_multiplier;
1182
1183         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1184 }
1185
1186 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1187                               struct intel_crtc_state *pipe_config)
1188 {
1189         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1190         int link_clock = 0;
1191         uint32_t cfgcr0, pll_id;
1192
1193         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1194
1195         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1196
1197         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1198                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1199         } else {
1200                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1201
1202                 switch (link_clock) {
1203                 case DPLL_CFGCR0_LINK_RATE_810:
1204                         link_clock = 81000;
1205                         break;
1206                 case DPLL_CFGCR0_LINK_RATE_1080:
1207                         link_clock = 108000;
1208                         break;
1209                 case DPLL_CFGCR0_LINK_RATE_1350:
1210                         link_clock = 135000;
1211                         break;
1212                 case DPLL_CFGCR0_LINK_RATE_1620:
1213                         link_clock = 162000;
1214                         break;
1215                 case DPLL_CFGCR0_LINK_RATE_2160:
1216                         link_clock = 216000;
1217                         break;
1218                 case DPLL_CFGCR0_LINK_RATE_2700:
1219                         link_clock = 270000;
1220                         break;
1221                 case DPLL_CFGCR0_LINK_RATE_3240:
1222                         link_clock = 324000;
1223                         break;
1224                 case DPLL_CFGCR0_LINK_RATE_4050:
1225                         link_clock = 405000;
1226                         break;
1227                 default:
1228                         WARN(1, "Unsupported link rate\n");
1229                         break;
1230                 }
1231                 link_clock *= 2;
1232         }
1233
1234         pipe_config->port_clock = link_clock;
1235
1236         ddi_dotclock_get(pipe_config);
1237 }
1238
1239 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1240                                 struct intel_crtc_state *pipe_config)
1241 {
1242         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1243         int link_clock = 0;
1244         uint32_t dpll_ctl1, dpll;
1245
1246         dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1247
1248         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1249
1250         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1251                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1252         } else {
1253                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1254                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1255
1256                 switch (link_clock) {
1257                 case DPLL_CTRL1_LINK_RATE_810:
1258                         link_clock = 81000;
1259                         break;
1260                 case DPLL_CTRL1_LINK_RATE_1080:
1261                         link_clock = 108000;
1262                         break;
1263                 case DPLL_CTRL1_LINK_RATE_1350:
1264                         link_clock = 135000;
1265                         break;
1266                 case DPLL_CTRL1_LINK_RATE_1620:
1267                         link_clock = 162000;
1268                         break;
1269                 case DPLL_CTRL1_LINK_RATE_2160:
1270                         link_clock = 216000;
1271                         break;
1272                 case DPLL_CTRL1_LINK_RATE_2700:
1273                         link_clock = 270000;
1274                         break;
1275                 default:
1276                         WARN(1, "Unsupported link rate\n");
1277                         break;
1278                 }
1279                 link_clock *= 2;
1280         }
1281
1282         pipe_config->port_clock = link_clock;
1283
1284         ddi_dotclock_get(pipe_config);
1285 }
1286
1287 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1288                               struct intel_crtc_state *pipe_config)
1289 {
1290         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1291         int link_clock = 0;
1292         u32 val, pll;
1293
1294         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1295         switch (val & PORT_CLK_SEL_MASK) {
1296         case PORT_CLK_SEL_LCPLL_810:
1297                 link_clock = 81000;
1298                 break;
1299         case PORT_CLK_SEL_LCPLL_1350:
1300                 link_clock = 135000;
1301                 break;
1302         case PORT_CLK_SEL_LCPLL_2700:
1303                 link_clock = 270000;
1304                 break;
1305         case PORT_CLK_SEL_WRPLL1:
1306                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1307                 break;
1308         case PORT_CLK_SEL_WRPLL2:
1309                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1310                 break;
1311         case PORT_CLK_SEL_SPLL:
1312                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1313                 if (pll == SPLL_PLL_FREQ_810MHz)
1314                         link_clock = 81000;
1315                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1316                         link_clock = 135000;
1317                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1318                         link_clock = 270000;
1319                 else {
1320                         WARN(1, "bad spll freq\n");
1321                         return;
1322                 }
1323                 break;
1324         default:
1325                 WARN(1, "bad port clock sel\n");
1326                 return;
1327         }
1328
1329         pipe_config->port_clock = link_clock * 2;
1330
1331         ddi_dotclock_get(pipe_config);
1332 }
1333
1334 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1335                                 enum intel_dpll_id dpll)
1336 {
1337         struct intel_shared_dpll *pll;
1338         struct intel_dpll_hw_state *state;
1339         struct dpll clock;
1340
1341         /* For DDI ports we always use a shared PLL. */
1342         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1343                 return 0;
1344
1345         pll = &dev_priv->shared_dplls[dpll];
1346         state = &pll->state.hw_state;
1347
1348         clock.m1 = 2;
1349         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1350         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1351                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1352         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1353         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1354         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1355
1356         return chv_calc_dpll_params(100000, &clock);
1357 }
1358
1359 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1360                                 struct intel_crtc_state *pipe_config)
1361 {
1362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1363         enum port port = intel_ddi_get_encoder_port(encoder);
1364         uint32_t dpll = port;
1365
1366         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1367
1368         ddi_dotclock_get(pipe_config);
1369 }
1370
1371 void intel_ddi_clock_get(struct intel_encoder *encoder,
1372                          struct intel_crtc_state *pipe_config)
1373 {
1374         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1375
1376         if (INTEL_GEN(dev_priv) <= 8)
1377                 hsw_ddi_clock_get(encoder, pipe_config);
1378         else if (IS_GEN9_BC(dev_priv))
1379                 skl_ddi_clock_get(encoder, pipe_config);
1380         else if (IS_GEN9_LP(dev_priv))
1381                 bxt_ddi_clock_get(encoder, pipe_config);
1382         else if (IS_CANNONLAKE(dev_priv))
1383                 cnl_ddi_clock_get(encoder, pipe_config);
1384 }
1385
1386 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1387 {
1388         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1389         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1390         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1391         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1392         int type = encoder->type;
1393         uint32_t temp;
1394
1395         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1396                 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1397
1398                 temp = TRANS_MSA_SYNC_CLK;
1399
1400                 if (crtc_state->limited_color_range)
1401                         temp |= TRANS_MSA_CEA_RANGE;
1402
1403                 switch (crtc_state->pipe_bpp) {
1404                 case 18:
1405                         temp |= TRANS_MSA_6_BPC;
1406                         break;
1407                 case 24:
1408                         temp |= TRANS_MSA_8_BPC;
1409                         break;
1410                 case 30:
1411                         temp |= TRANS_MSA_10_BPC;
1412                         break;
1413                 case 36:
1414                         temp |= TRANS_MSA_12_BPC;
1415                         break;
1416                 default:
1417                         BUG();
1418                 }
1419                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1420         }
1421 }
1422
1423 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1424                                     bool state)
1425 {
1426         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1427         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1428         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1429         uint32_t temp;
1430         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1431         if (state == true)
1432                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1433         else
1434                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1435         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1436 }
1437
1438 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1439 {
1440         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1441         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1442         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1443         enum pipe pipe = crtc->pipe;
1444         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1445         enum port port = intel_ddi_get_encoder_port(encoder);
1446         int type = encoder->type;
1447         uint32_t temp;
1448
1449         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1450         temp = TRANS_DDI_FUNC_ENABLE;
1451         temp |= TRANS_DDI_SELECT_PORT(port);
1452
1453         switch (crtc_state->pipe_bpp) {
1454         case 18:
1455                 temp |= TRANS_DDI_BPC_6;
1456                 break;
1457         case 24:
1458                 temp |= TRANS_DDI_BPC_8;
1459                 break;
1460         case 30:
1461                 temp |= TRANS_DDI_BPC_10;
1462                 break;
1463         case 36:
1464                 temp |= TRANS_DDI_BPC_12;
1465                 break;
1466         default:
1467                 BUG();
1468         }
1469
1470         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1471                 temp |= TRANS_DDI_PVSYNC;
1472         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1473                 temp |= TRANS_DDI_PHSYNC;
1474
1475         if (cpu_transcoder == TRANSCODER_EDP) {
1476                 switch (pipe) {
1477                 case PIPE_A:
1478                         /* On Haswell, can only use the always-on power well for
1479                          * eDP when not using the panel fitter, and when not
1480                          * using motion blur mitigation (which we don't
1481                          * support). */
1482                         if (IS_HASWELL(dev_priv) &&
1483                             (crtc_state->pch_pfit.enabled ||
1484                              crtc_state->pch_pfit.force_thru))
1485                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1486                         else
1487                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1488                         break;
1489                 case PIPE_B:
1490                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1491                         break;
1492                 case PIPE_C:
1493                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1494                         break;
1495                 default:
1496                         BUG();
1497                         break;
1498                 }
1499         }
1500
1501         if (type == INTEL_OUTPUT_HDMI) {
1502                 if (crtc_state->has_hdmi_sink)
1503                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1504                 else
1505                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1506
1507                 if (crtc_state->hdmi_scrambling)
1508                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1509                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1510                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1511         } else if (type == INTEL_OUTPUT_ANALOG) {
1512                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1513                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1514         } else if (type == INTEL_OUTPUT_DP ||
1515                    type == INTEL_OUTPUT_EDP) {
1516                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1517                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1518         } else if (type == INTEL_OUTPUT_DP_MST) {
1519                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1520                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1521         } else {
1522                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1523                      encoder->type, pipe_name(pipe));
1524         }
1525
1526         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1527 }
1528
1529 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1530 {
1531         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1533         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1534         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1535         uint32_t val = I915_READ(reg);
1536
1537         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1538         val |= TRANS_DDI_PORT_NONE;
1539         I915_WRITE(reg, val);
1540
1541         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1542             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1543                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1544                 /* Quirk time at 100ms for reliable operation */
1545                 msleep(100);
1546         }
1547 }
1548
1549 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1550 {
1551         struct drm_device *dev = intel_connector->base.dev;
1552         struct drm_i915_private *dev_priv = to_i915(dev);
1553         struct intel_encoder *encoder = intel_connector->encoder;
1554         int type = intel_connector->base.connector_type;
1555         enum port port = intel_ddi_get_encoder_port(encoder);
1556         enum pipe pipe = 0;
1557         enum transcoder cpu_transcoder;
1558         uint32_t tmp;
1559         bool ret;
1560
1561         if (!intel_display_power_get_if_enabled(dev_priv,
1562                                                 encoder->power_domain))
1563                 return false;
1564
1565         if (!encoder->get_hw_state(encoder, &pipe)) {
1566                 ret = false;
1567                 goto out;
1568         }
1569
1570         if (port == PORT_A)
1571                 cpu_transcoder = TRANSCODER_EDP;
1572         else
1573                 cpu_transcoder = (enum transcoder) pipe;
1574
1575         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1576
1577         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1578         case TRANS_DDI_MODE_SELECT_HDMI:
1579         case TRANS_DDI_MODE_SELECT_DVI:
1580                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1581                 break;
1582
1583         case TRANS_DDI_MODE_SELECT_DP_SST:
1584                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1585                       type == DRM_MODE_CONNECTOR_DisplayPort;
1586                 break;
1587
1588         case TRANS_DDI_MODE_SELECT_DP_MST:
1589                 /* if the transcoder is in MST state then
1590                  * connector isn't connected */
1591                 ret = false;
1592                 break;
1593
1594         case TRANS_DDI_MODE_SELECT_FDI:
1595                 ret = type == DRM_MODE_CONNECTOR_VGA;
1596                 break;
1597
1598         default:
1599                 ret = false;
1600                 break;
1601         }
1602
1603 out:
1604         intel_display_power_put(dev_priv, encoder->power_domain);
1605
1606         return ret;
1607 }
1608
1609 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1610                             enum pipe *pipe)
1611 {
1612         struct drm_device *dev = encoder->base.dev;
1613         struct drm_i915_private *dev_priv = to_i915(dev);
1614         enum port port = intel_ddi_get_encoder_port(encoder);
1615         u32 tmp;
1616         int i;
1617         bool ret;
1618
1619         if (!intel_display_power_get_if_enabled(dev_priv,
1620                                                 encoder->power_domain))
1621                 return false;
1622
1623         ret = false;
1624
1625         tmp = I915_READ(DDI_BUF_CTL(port));
1626
1627         if (!(tmp & DDI_BUF_CTL_ENABLE))
1628                 goto out;
1629
1630         if (port == PORT_A) {
1631                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1632
1633                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1634                 case TRANS_DDI_EDP_INPUT_A_ON:
1635                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1636                         *pipe = PIPE_A;
1637                         break;
1638                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1639                         *pipe = PIPE_B;
1640                         break;
1641                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1642                         *pipe = PIPE_C;
1643                         break;
1644                 }
1645
1646                 ret = true;
1647
1648                 goto out;
1649         }
1650
1651         for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1652                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1653
1654                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1655                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1656                             TRANS_DDI_MODE_SELECT_DP_MST)
1657                                 goto out;
1658
1659                         *pipe = i;
1660                         ret = true;
1661
1662                         goto out;
1663                 }
1664         }
1665
1666         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1667
1668 out:
1669         if (ret && IS_GEN9_LP(dev_priv)) {
1670                 tmp = I915_READ(BXT_PHY_CTL(port));
1671                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1672                             BXT_PHY_LANE_POWERDOWN_ACK |
1673                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1674                         DRM_ERROR("Port %c enabled but PHY powered down? "
1675                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1676         }
1677
1678         intel_display_power_put(dev_priv, encoder->power_domain);
1679
1680         return ret;
1681 }
1682
1683 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1684 {
1685         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1686         enum pipe pipe;
1687
1688         if (intel_ddi_get_hw_state(encoder, &pipe))
1689                 return BIT_ULL(dig_port->ddi_io_power_domain);
1690
1691         return 0;
1692 }
1693
1694 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1695 {
1696         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1697         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1698         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1699         enum port port = intel_ddi_get_encoder_port(encoder);
1700         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1701
1702         if (cpu_transcoder != TRANSCODER_EDP)
1703                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1704                            TRANS_CLK_SEL_PORT(port));
1705 }
1706
1707 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1708 {
1709         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1710         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1711
1712         if (cpu_transcoder != TRANSCODER_EDP)
1713                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1714                            TRANS_CLK_SEL_DISABLED);
1715 }
1716
1717 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1718                                 enum port port, uint8_t iboost)
1719 {
1720         u32 tmp;
1721
1722         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1723         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1724         if (iboost)
1725                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1726         else
1727                 tmp |= BALANCE_LEG_DISABLE(port);
1728         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1729 }
1730
1731 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1732 {
1733         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1734         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1735         enum port port = intel_dig_port->port;
1736         int type = encoder->type;
1737         const struct ddi_buf_trans *ddi_translations;
1738         uint8_t iboost;
1739         uint8_t dp_iboost, hdmi_iboost;
1740         int n_entries;
1741
1742         /* VBT may override standard boost values */
1743         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1744         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1745
1746         if (type == INTEL_OUTPUT_DP) {
1747                 if (dp_iboost) {
1748                         iboost = dp_iboost;
1749                 } else {
1750                         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
1751                                 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1752                                                                         &n_entries);
1753                         else
1754                                 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1755                                                                         &n_entries);
1756                         iboost = ddi_translations[level].i_boost;
1757                 }
1758         } else if (type == INTEL_OUTPUT_EDP) {
1759                 if (dp_iboost) {
1760                         iboost = dp_iboost;
1761                 } else {
1762                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1763
1764                         if (WARN_ON(port != PORT_A &&
1765                                     port != PORT_E && n_entries > 9))
1766                                 n_entries = 9;
1767
1768                         iboost = ddi_translations[level].i_boost;
1769                 }
1770         } else if (type == INTEL_OUTPUT_HDMI) {
1771                 if (hdmi_iboost) {
1772                         iboost = hdmi_iboost;
1773                 } else {
1774                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1775                         iboost = ddi_translations[level].i_boost;
1776                 }
1777         } else {
1778                 return;
1779         }
1780
1781         /* Make sure that the requested I_boost is valid */
1782         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1783                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1784                 return;
1785         }
1786
1787         _skl_ddi_set_iboost(dev_priv, port, iboost);
1788
1789         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1790                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1791 }
1792
1793 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1794                                     u32 level, enum port port, int type)
1795 {
1796         const struct bxt_ddi_buf_trans *ddi_translations;
1797         u32 n_entries, i;
1798
1799         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1800                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1801                 ddi_translations = bxt_ddi_translations_edp;
1802         } else if (type == INTEL_OUTPUT_DP
1803                         || type == INTEL_OUTPUT_EDP) {
1804                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1805                 ddi_translations = bxt_ddi_translations_dp;
1806         } else if (type == INTEL_OUTPUT_HDMI) {
1807                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1808                 ddi_translations = bxt_ddi_translations_hdmi;
1809         } else {
1810                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1811                                 type);
1812                 return;
1813         }
1814
1815         /* Check if default value has to be used */
1816         if (level >= n_entries ||
1817             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1818                 for (i = 0; i < n_entries; i++) {
1819                         if (ddi_translations[i].default_index) {
1820                                 level = i;
1821                                 break;
1822                         }
1823                 }
1824         }
1825
1826         bxt_ddi_phy_set_signal_level(dev_priv, port,
1827                                      ddi_translations[level].margin,
1828                                      ddi_translations[level].scale,
1829                                      ddi_translations[level].enable,
1830                                      ddi_translations[level].deemphasis);
1831 }
1832
1833 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1834 {
1835         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1836         int n_entries;
1837
1838         if (encoder->type == INTEL_OUTPUT_EDP)
1839                 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1840         else
1841                 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1842
1843         if (WARN_ON(n_entries < 1))
1844                 n_entries = 1;
1845         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1846                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1847
1848         return index_to_dp_signal_levels[n_entries - 1] &
1849                 DP_TRAIN_VOLTAGE_SWING_MASK;
1850 }
1851
1852 static const struct cnl_ddi_buf_trans *
1853 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
1854                        u32 voltage, int *n_entries)
1855 {
1856         if (voltage == VOLTAGE_INFO_0_85V) {
1857                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1858                 return cnl_ddi_translations_hdmi_0_85V;
1859         } else if (voltage == VOLTAGE_INFO_0_95V) {
1860                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1861                 return cnl_ddi_translations_hdmi_0_95V;
1862         } else if (voltage == VOLTAGE_INFO_1_05V) {
1863                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1864                 return cnl_ddi_translations_hdmi_1_05V;
1865         }
1866         return NULL;
1867 }
1868
1869 static const struct cnl_ddi_buf_trans *
1870 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
1871                      u32 voltage, int *n_entries)
1872 {
1873         if (voltage == VOLTAGE_INFO_0_85V) {
1874                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1875                 return cnl_ddi_translations_dp_0_85V;
1876         } else if (voltage == VOLTAGE_INFO_0_95V) {
1877                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1878                 return cnl_ddi_translations_dp_0_95V;
1879         } else if (voltage == VOLTAGE_INFO_1_05V) {
1880                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1881                 return cnl_ddi_translations_dp_1_05V;
1882         }
1883         return NULL;
1884 }
1885
1886 static const struct cnl_ddi_buf_trans *
1887 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
1888                       u32 voltage, int *n_entries)
1889 {
1890         if (dev_priv->vbt.edp.low_vswing) {
1891                 if (voltage == VOLTAGE_INFO_0_85V) {
1892                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1893                         return cnl_ddi_translations_edp_0_85V;
1894                 } else if (voltage == VOLTAGE_INFO_0_95V) {
1895                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1896                         return cnl_ddi_translations_edp_0_95V;
1897                 } else if (voltage == VOLTAGE_INFO_1_05V) {
1898                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1899                         return cnl_ddi_translations_edp_1_05V;
1900                 }
1901                 return NULL;
1902         } else {
1903                 return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
1904         }
1905 }
1906
1907 static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1908                                     u32 level, enum port port, int type)
1909 {
1910         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1911         u32 n_entries, val, voltage;
1912         int ln;
1913
1914         /*
1915          * Values for each port type are listed in
1916          * voltage swing programming tables.
1917          * Vccio voltage found in PORT_COMP_DW3.
1918          */
1919         voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1920
1921         if (type == INTEL_OUTPUT_HDMI) {
1922                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
1923                                                           voltage, &n_entries);
1924         } else if (type == INTEL_OUTPUT_DP) {
1925                 ddi_translations = cnl_get_buf_trans_dp(dev_priv,
1926                                                         voltage, &n_entries);
1927         } else if (type == INTEL_OUTPUT_EDP) {
1928                 ddi_translations = cnl_get_buf_trans_edp(dev_priv,
1929                                                          voltage, &n_entries);
1930         }
1931
1932         if (ddi_translations == NULL) {
1933                 MISSING_CASE(voltage);
1934                 return;
1935         }
1936
1937         if (level >= n_entries) {
1938                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1939                 level = n_entries - 1;
1940         }
1941
1942         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1943         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1944         val &= ~SCALING_MODE_SEL_MASK;
1945         val |= SCALING_MODE_SEL(2);
1946         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1947
1948         /* Program PORT_TX_DW2 */
1949         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1950         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1951                  RCOMP_SCALAR_MASK);
1952         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1953         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1954         /* Rcomp scalar is fixed as 0x98 for every table entry */
1955         val |= RCOMP_SCALAR(0x98);
1956         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1957
1958         /* Program PORT_TX_DW4 */
1959         /* We cannot write to GRP. It would overrite individual loadgen */
1960         for (ln = 0; ln < 4; ln++) {
1961                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1962                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1963                          CURSOR_COEFF_MASK);
1964                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1965                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1966                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1967                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1968         }
1969
1970         /* Program PORT_TX_DW5 */
1971         /* All DW5 values are fixed for every table entry */
1972         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1973         val &= ~RTERM_SELECT_MASK;
1974         val |= RTERM_SELECT(6);
1975         val |= TAP3_DISABLE;
1976         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1977
1978         /* Program PORT_TX_DW7 */
1979         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1980         val &= ~N_SCALAR_MASK;
1981         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1982         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1983 }
1984
1985 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
1986 {
1987         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1988         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1989         enum port port = intel_ddi_get_encoder_port(encoder);
1990         int type = encoder->type;
1991         int width = 0;
1992         int rate = 0;
1993         u32 val;
1994         int ln = 0;
1995
1996         if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1997                 width = intel_dp->lane_count;
1998                 rate = intel_dp->link_rate;
1999         } else if (type == INTEL_OUTPUT_HDMI) {
2000                 width = 4;
2001                 /* Rate is always < than 6GHz for HDMI */
2002         } else {
2003                 MISSING_CASE(type);
2004                 return;
2005         }
2006
2007         /*
2008          * 1. If port type is eDP or DP,
2009          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2010          * else clear to 0b.
2011          */
2012         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2013         if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
2014                 val |= COMMON_KEEPER_EN;
2015         else
2016                 val &= ~COMMON_KEEPER_EN;
2017         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2018
2019         /* 2. Program loadgen select */
2020         /*
2021          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2022          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2023          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2024          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2025          */
2026         for (ln = 0; ln <= 3; ln++) {
2027                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2028                 val &= ~LOADGEN_SELECT;
2029
2030                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2031                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2032                         val |= LOADGEN_SELECT;
2033                 }
2034                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2035         }
2036
2037         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2038         val = I915_READ(CNL_PORT_CL1CM_DW5);
2039         val |= SUS_CLOCK_CONFIG;
2040         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2041
2042         /* 4. Clear training enable to change swing values */
2043         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2044         val &= ~TX_TRAINING_EN;
2045         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2046
2047         /* 5. Program swing and de-emphasis */
2048         cnl_ddi_vswing_program(dev_priv, level, port, type);
2049
2050         /* 6. Set training enable to trigger update */
2051         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2052         val |= TX_TRAINING_EN;
2053         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2054 }
2055
2056 static uint32_t translate_signal_level(int signal_levels)
2057 {
2058         int i;
2059
2060         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2061                 if (index_to_dp_signal_levels[i] == signal_levels)
2062                         return i;
2063         }
2064
2065         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2066              signal_levels);
2067
2068         return 0;
2069 }
2070
2071 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2072 {
2073         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2074         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2075         struct intel_encoder *encoder = &dport->base;
2076         uint8_t train_set = intel_dp->train_set[0];
2077         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2078                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2079         enum port port = dport->port;
2080         uint32_t level;
2081
2082         level = translate_signal_level(signal_levels);
2083
2084         if (IS_GEN9_BC(dev_priv))
2085                 skl_ddi_set_iboost(encoder, level);
2086         else if (IS_GEN9_LP(dev_priv))
2087                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2088         else if (IS_CANNONLAKE(dev_priv)) {
2089                 cnl_ddi_vswing_sequence(encoder, level);
2090                 /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
2091                 return 0;
2092         }
2093         return DDI_BUF_TRANS_SELECT(level);
2094 }
2095
2096 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2097                                  struct intel_shared_dpll *pll)
2098 {
2099         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2100         enum port port = intel_ddi_get_encoder_port(encoder);
2101         uint32_t val;
2102
2103         if (WARN_ON(!pll))
2104                 return;
2105
2106         if (IS_CANNONLAKE(dev_priv)) {
2107                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2108                 val = I915_READ(DPCLKA_CFGCR0);
2109                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2110                 I915_WRITE(DPCLKA_CFGCR0, val);
2111
2112                 /*
2113                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2114                  * This step and the step before must be done with separate
2115                  * register writes.
2116                  */
2117                 val = I915_READ(DPCLKA_CFGCR0);
2118                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2119                 I915_WRITE(DPCLKA_CFGCR0, val);
2120         } else if (IS_GEN9_BC(dev_priv)) {
2121                 /* DDI -> PLL mapping  */
2122                 val = I915_READ(DPLL_CTRL2);
2123
2124                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2125                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2126                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2127                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2128
2129                 I915_WRITE(DPLL_CTRL2, val);
2130
2131         } else if (INTEL_INFO(dev_priv)->gen < 9) {
2132                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2133         }
2134 }
2135
2136 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2137                                     int link_rate, uint32_t lane_count,
2138                                     struct intel_shared_dpll *pll,
2139                                     bool link_mst)
2140 {
2141         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2142         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2143         enum port port = intel_ddi_get_encoder_port(encoder);
2144         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2145
2146         WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2147
2148         intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2149                                  link_mst);
2150         if (encoder->type == INTEL_OUTPUT_EDP)
2151                 intel_edp_panel_on(intel_dp);
2152
2153         intel_ddi_clk_select(encoder, pll);
2154
2155         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2156
2157         intel_prepare_dp_ddi_buffers(encoder);
2158         intel_ddi_init_dp_buf_reg(encoder);
2159         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2160         intel_dp_start_link_train(intel_dp);
2161         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2162                 intel_dp_stop_link_train(intel_dp);
2163 }
2164
2165 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2166                                       bool has_hdmi_sink,
2167                                       const struct intel_crtc_state *crtc_state,
2168                                       const struct drm_connector_state *conn_state,
2169                                       struct intel_shared_dpll *pll)
2170 {
2171         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2172         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2173         struct drm_encoder *drm_encoder = &encoder->base;
2174         enum port port = intel_ddi_get_encoder_port(encoder);
2175         int level = intel_ddi_hdmi_level(dev_priv, port);
2176         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2177
2178         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2179         intel_ddi_clk_select(encoder, pll);
2180
2181         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2182
2183         intel_prepare_hdmi_ddi_buffers(encoder);
2184         if (IS_GEN9_BC(dev_priv))
2185                 skl_ddi_set_iboost(encoder, level);
2186         else if (IS_GEN9_LP(dev_priv))
2187                 bxt_ddi_vswing_sequence(dev_priv, level, port,
2188                                         INTEL_OUTPUT_HDMI);
2189         else if (IS_CANNONLAKE(dev_priv))
2190                 cnl_ddi_vswing_sequence(encoder, level);
2191
2192         intel_hdmi->set_infoframes(drm_encoder,
2193                                    has_hdmi_sink,
2194                                    crtc_state, conn_state);
2195 }
2196
2197 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2198                                  struct intel_crtc_state *pipe_config,
2199                                  struct drm_connector_state *conn_state)
2200 {
2201         int type = encoder->type;
2202
2203         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2204                 intel_ddi_pre_enable_dp(encoder,
2205                                         pipe_config->port_clock,
2206                                         pipe_config->lane_count,
2207                                         pipe_config->shared_dpll,
2208                                         intel_crtc_has_type(pipe_config,
2209                                                             INTEL_OUTPUT_DP_MST));
2210         }
2211         if (type == INTEL_OUTPUT_HDMI) {
2212                 intel_ddi_pre_enable_hdmi(encoder,
2213                                           pipe_config->has_hdmi_sink,
2214                                           pipe_config, conn_state,
2215                                           pipe_config->shared_dpll);
2216         }
2217 }
2218
2219 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2220                                    struct intel_crtc_state *old_crtc_state,
2221                                    struct drm_connector_state *old_conn_state)
2222 {
2223         struct drm_encoder *encoder = &intel_encoder->base;
2224         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2225         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2226         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2227         struct intel_dp *intel_dp = NULL;
2228         int type = intel_encoder->type;
2229         uint32_t val;
2230         bool wait = false;
2231
2232         /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2233
2234         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2235                 intel_dp = enc_to_intel_dp(encoder);
2236                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2237         }
2238
2239         val = I915_READ(DDI_BUF_CTL(port));
2240         if (val & DDI_BUF_CTL_ENABLE) {
2241                 val &= ~DDI_BUF_CTL_ENABLE;
2242                 I915_WRITE(DDI_BUF_CTL(port), val);
2243                 wait = true;
2244         }
2245
2246         val = I915_READ(DP_TP_CTL(port));
2247         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2248         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2249         I915_WRITE(DP_TP_CTL(port), val);
2250
2251         if (wait)
2252                 intel_wait_ddi_buf_idle(dev_priv, port);
2253
2254         if (intel_dp) {
2255                 intel_edp_panel_vdd_on(intel_dp);
2256                 intel_edp_panel_off(intel_dp);
2257         }
2258
2259         if (dig_port)
2260                 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2261
2262         if (IS_CANNONLAKE(dev_priv))
2263                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2264                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2265         else if (IS_GEN9_BC(dev_priv))
2266                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2267                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
2268         else if (INTEL_GEN(dev_priv) < 9)
2269                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2270
2271         if (type == INTEL_OUTPUT_HDMI) {
2272                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2273
2274                 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2275         }
2276 }
2277
2278 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2279                                 struct intel_crtc_state *old_crtc_state,
2280                                 struct drm_connector_state *old_conn_state)
2281 {
2282         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2283         uint32_t val;
2284
2285         /*
2286          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2287          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2288          * step 13 is the correct place for it. Step 18 is where it was
2289          * originally before the BUN.
2290          */
2291         val = I915_READ(FDI_RX_CTL(PIPE_A));
2292         val &= ~FDI_RX_ENABLE;
2293         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2294
2295         intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
2296
2297         val = I915_READ(FDI_RX_MISC(PIPE_A));
2298         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2299         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2300         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2301
2302         val = I915_READ(FDI_RX_CTL(PIPE_A));
2303         val &= ~FDI_PCDCLK;
2304         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2305
2306         val = I915_READ(FDI_RX_CTL(PIPE_A));
2307         val &= ~FDI_RX_PLL_ENABLE;
2308         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2309 }
2310
2311 static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2312                              struct intel_crtc_state *pipe_config,
2313                              struct drm_connector_state *conn_state)
2314 {
2315         struct drm_encoder *encoder = &intel_encoder->base;
2316         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2317         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2318         int type = intel_encoder->type;
2319
2320         if (type == INTEL_OUTPUT_HDMI) {
2321                 struct intel_digital_port *intel_dig_port =
2322                         enc_to_dig_port(encoder);
2323                 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2324                 bool scrambling = pipe_config->hdmi_scrambling;
2325
2326                 intel_hdmi_handle_sink_scrambling(intel_encoder,
2327                                                   conn_state->connector,
2328                                                   clock_ratio, scrambling);
2329
2330                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2331                  * are ignored so nothing special needs to be done besides
2332                  * enabling the port.
2333                  */
2334                 I915_WRITE(DDI_BUF_CTL(port),
2335                            intel_dig_port->saved_port_bits |
2336                            DDI_BUF_CTL_ENABLE);
2337         } else if (type == INTEL_OUTPUT_EDP) {
2338                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2339
2340                 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2341                         intel_dp_stop_link_train(intel_dp);
2342
2343                 intel_edp_backlight_on(pipe_config, conn_state);
2344                 intel_psr_enable(intel_dp);
2345                 intel_edp_drrs_enable(intel_dp, pipe_config);
2346         }
2347
2348         if (pipe_config->has_audio)
2349                 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
2350 }
2351
2352 static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2353                               struct intel_crtc_state *old_crtc_state,
2354                               struct drm_connector_state *old_conn_state)
2355 {
2356         struct drm_encoder *encoder = &intel_encoder->base;
2357         int type = intel_encoder->type;
2358
2359         if (old_crtc_state->has_audio)
2360                 intel_audio_codec_disable(intel_encoder);
2361
2362         if (type == INTEL_OUTPUT_HDMI) {
2363                 intel_hdmi_handle_sink_scrambling(intel_encoder,
2364                                                   old_conn_state->connector,
2365                                                   false, false);
2366         }
2367
2368         if (type == INTEL_OUTPUT_EDP) {
2369                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2370
2371                 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2372                 intel_psr_disable(intel_dp);
2373                 intel_edp_backlight_off(old_conn_state);
2374         }
2375 }
2376
2377 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2378                                    struct intel_crtc_state *pipe_config,
2379                                    struct drm_connector_state *conn_state)
2380 {
2381         uint8_t mask = pipe_config->lane_lat_optim_mask;
2382
2383         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2384 }
2385
2386 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2387 {
2388         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2389         struct drm_i915_private *dev_priv =
2390                 to_i915(intel_dig_port->base.base.dev);
2391         enum port port = intel_dig_port->port;
2392         uint32_t val;
2393         bool wait = false;
2394
2395         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2396                 val = I915_READ(DDI_BUF_CTL(port));
2397                 if (val & DDI_BUF_CTL_ENABLE) {
2398                         val &= ~DDI_BUF_CTL_ENABLE;
2399                         I915_WRITE(DDI_BUF_CTL(port), val);
2400                         wait = true;
2401                 }
2402
2403                 val = I915_READ(DP_TP_CTL(port));
2404                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2405                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2406                 I915_WRITE(DP_TP_CTL(port), val);
2407                 POSTING_READ(DP_TP_CTL(port));
2408
2409                 if (wait)
2410                         intel_wait_ddi_buf_idle(dev_priv, port);
2411         }
2412
2413         val = DP_TP_CTL_ENABLE |
2414               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2415         if (intel_dp->link_mst)
2416                 val |= DP_TP_CTL_MODE_MST;
2417         else {
2418                 val |= DP_TP_CTL_MODE_SST;
2419                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2420                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2421         }
2422         I915_WRITE(DP_TP_CTL(port), val);
2423         POSTING_READ(DP_TP_CTL(port));
2424
2425         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2426         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2427         POSTING_READ(DDI_BUF_CTL(port));
2428
2429         udelay(600);
2430 }
2431
2432 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2433                                  struct intel_crtc *intel_crtc)
2434 {
2435         u32 temp;
2436
2437         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2438                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2439                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2440                         return true;
2441         }
2442         return false;
2443 }
2444
2445 void intel_ddi_get_config(struct intel_encoder *encoder,
2446                           struct intel_crtc_state *pipe_config)
2447 {
2448         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2449         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2450         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2451         struct intel_hdmi *intel_hdmi;
2452         u32 temp, flags = 0;
2453
2454         /* XXX: DSI transcoder paranoia */
2455         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2456                 return;
2457
2458         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2459         if (temp & TRANS_DDI_PHSYNC)
2460                 flags |= DRM_MODE_FLAG_PHSYNC;
2461         else
2462                 flags |= DRM_MODE_FLAG_NHSYNC;
2463         if (temp & TRANS_DDI_PVSYNC)
2464                 flags |= DRM_MODE_FLAG_PVSYNC;
2465         else
2466                 flags |= DRM_MODE_FLAG_NVSYNC;
2467
2468         pipe_config->base.adjusted_mode.flags |= flags;
2469
2470         switch (temp & TRANS_DDI_BPC_MASK) {
2471         case TRANS_DDI_BPC_6:
2472                 pipe_config->pipe_bpp = 18;
2473                 break;
2474         case TRANS_DDI_BPC_8:
2475                 pipe_config->pipe_bpp = 24;
2476                 break;
2477         case TRANS_DDI_BPC_10:
2478                 pipe_config->pipe_bpp = 30;
2479                 break;
2480         case TRANS_DDI_BPC_12:
2481                 pipe_config->pipe_bpp = 36;
2482                 break;
2483         default:
2484                 break;
2485         }
2486
2487         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2488         case TRANS_DDI_MODE_SELECT_HDMI:
2489                 pipe_config->has_hdmi_sink = true;
2490                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2491
2492                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2493                         pipe_config->has_infoframe = true;
2494
2495                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2496                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
2497                         pipe_config->hdmi_scrambling = true;
2498                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2499                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2500                 /* fall through */
2501         case TRANS_DDI_MODE_SELECT_DVI:
2502                 pipe_config->lane_count = 4;
2503                 break;
2504         case TRANS_DDI_MODE_SELECT_FDI:
2505                 break;
2506         case TRANS_DDI_MODE_SELECT_DP_SST:
2507         case TRANS_DDI_MODE_SELECT_DP_MST:
2508                 pipe_config->lane_count =
2509                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2510                 intel_dp_get_m_n(intel_crtc, pipe_config);
2511                 break;
2512         default:
2513                 break;
2514         }
2515
2516         pipe_config->has_audio =
2517                 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2518
2519         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2520             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2521                 /*
2522                  * This is a big fat ugly hack.
2523                  *
2524                  * Some machines in UEFI boot mode provide us a VBT that has 18
2525                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2526                  * unknown we fail to light up. Yet the same BIOS boots up with
2527                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2528                  * max, not what it tells us to use.
2529                  *
2530                  * Note: This will still be broken if the eDP panel is not lit
2531                  * up by the BIOS, and thus we can't get the mode at module
2532                  * load.
2533                  */
2534                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2535                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2536                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2537         }
2538
2539         intel_ddi_clock_get(encoder, pipe_config);
2540
2541         if (IS_GEN9_LP(dev_priv))
2542                 pipe_config->lane_lat_optim_mask =
2543                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2544 }
2545
2546 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2547                                      struct intel_crtc_state *pipe_config,
2548                                      struct drm_connector_state *conn_state)
2549 {
2550         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2551         int type = encoder->type;
2552         int port = intel_ddi_get_encoder_port(encoder);
2553         int ret;
2554
2555         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2556
2557         if (port == PORT_A)
2558                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2559
2560         if (type == INTEL_OUTPUT_HDMI)
2561                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2562         else
2563                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2564
2565         if (IS_GEN9_LP(dev_priv) && ret)
2566                 pipe_config->lane_lat_optim_mask =
2567                         bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2568                                                              pipe_config->lane_count);
2569
2570         return ret;
2571
2572 }
2573
2574 static const struct drm_encoder_funcs intel_ddi_funcs = {
2575         .reset = intel_dp_encoder_reset,
2576         .destroy = intel_dp_encoder_destroy,
2577 };
2578
2579 static struct intel_connector *
2580 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2581 {
2582         struct intel_connector *connector;
2583         enum port port = intel_dig_port->port;
2584
2585         connector = intel_connector_alloc();
2586         if (!connector)
2587                 return NULL;
2588
2589         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2590         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2591                 kfree(connector);
2592                 return NULL;
2593         }
2594
2595         return connector;
2596 }
2597
2598 static struct intel_connector *
2599 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2600 {
2601         struct intel_connector *connector;
2602         enum port port = intel_dig_port->port;
2603
2604         connector = intel_connector_alloc();
2605         if (!connector)
2606                 return NULL;
2607
2608         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2609         intel_hdmi_init_connector(intel_dig_port, connector);
2610
2611         return connector;
2612 }
2613
2614 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2615 {
2616         struct intel_digital_port *intel_dig_port;
2617         struct intel_encoder *intel_encoder;
2618         struct drm_encoder *encoder;
2619         bool init_hdmi, init_dp, init_lspcon = false;
2620         int max_lanes;
2621
2622         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2623                 switch (port) {
2624                 case PORT_A:
2625                         max_lanes = 4;
2626                         break;
2627                 case PORT_E:
2628                         max_lanes = 0;
2629                         break;
2630                 default:
2631                         max_lanes = 4;
2632                         break;
2633                 }
2634         } else {
2635                 switch (port) {
2636                 case PORT_A:
2637                         max_lanes = 2;
2638                         break;
2639                 case PORT_E:
2640                         max_lanes = 2;
2641                         break;
2642                 default:
2643                         max_lanes = 4;
2644                         break;
2645                 }
2646         }
2647
2648         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2649                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2650         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2651
2652         if (intel_bios_is_lspcon_present(dev_priv, port)) {
2653                 /*
2654                  * Lspcon device needs to be driven with DP connector
2655                  * with special detection sequence. So make sure DP
2656                  * is initialized before lspcon.
2657                  */
2658                 init_dp = true;
2659                 init_lspcon = true;
2660                 init_hdmi = false;
2661                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2662         }
2663
2664         if (!init_dp && !init_hdmi) {
2665                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2666                               port_name(port));
2667                 return;
2668         }
2669
2670         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2671         if (!intel_dig_port)
2672                 return;
2673
2674         intel_encoder = &intel_dig_port->base;
2675         encoder = &intel_encoder->base;
2676
2677         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2678                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2679
2680         intel_encoder->compute_config = intel_ddi_compute_config;
2681         intel_encoder->enable = intel_enable_ddi;
2682         if (IS_GEN9_LP(dev_priv))
2683                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2684         intel_encoder->pre_enable = intel_ddi_pre_enable;
2685         intel_encoder->disable = intel_disable_ddi;
2686         intel_encoder->post_disable = intel_ddi_post_disable;
2687         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2688         intel_encoder->get_config = intel_ddi_get_config;
2689         intel_encoder->suspend = intel_dp_encoder_suspend;
2690         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2691
2692         intel_dig_port->port = port;
2693         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2694                                           (DDI_BUF_PORT_REVERSAL |
2695                                            DDI_A_4_LANES);
2696
2697         switch (port) {
2698         case PORT_A:
2699                 intel_dig_port->ddi_io_power_domain =
2700                         POWER_DOMAIN_PORT_DDI_A_IO;
2701                 break;
2702         case PORT_B:
2703                 intel_dig_port->ddi_io_power_domain =
2704                         POWER_DOMAIN_PORT_DDI_B_IO;
2705                 break;
2706         case PORT_C:
2707                 intel_dig_port->ddi_io_power_domain =
2708                         POWER_DOMAIN_PORT_DDI_C_IO;
2709                 break;
2710         case PORT_D:
2711                 intel_dig_port->ddi_io_power_domain =
2712                         POWER_DOMAIN_PORT_DDI_D_IO;
2713                 break;
2714         case PORT_E:
2715                 intel_dig_port->ddi_io_power_domain =
2716                         POWER_DOMAIN_PORT_DDI_E_IO;
2717                 break;
2718         default:
2719                 MISSING_CASE(port);
2720         }
2721
2722         /*
2723          * Bspec says that DDI_A_4_LANES is the only supported configuration
2724          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
2725          * wasn't lit up at boot.  Force this bit on in our internal
2726          * configuration so that we use the proper lane count for our
2727          * calculations.
2728          */
2729         if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2730                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2731                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2732                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2733                         max_lanes = 4;
2734                 }
2735         }
2736
2737         intel_dig_port->max_lanes = max_lanes;
2738
2739         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2740         intel_encoder->power_domain = intel_port_to_power_domain(port);
2741         intel_encoder->port = port;
2742         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2743         intel_encoder->cloneable = 0;
2744
2745         if (init_dp) {
2746                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2747                         goto err;
2748
2749                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2750                 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2751         }
2752
2753         /* In theory we don't need the encoder->type check, but leave it just in
2754          * case we have some really bad VBTs... */
2755         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2756                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2757                         goto err;
2758         }
2759
2760         if (init_lspcon) {
2761                 if (lspcon_init(intel_dig_port))
2762                         /* TODO: handle hdmi info frame part */
2763                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2764                                 port_name(port));
2765                 else
2766                         /*
2767                          * LSPCON init faied, but DP init was success, so
2768                          * lets try to drive as DP++ port.
2769                          */
2770                         DRM_ERROR("LSPCON init failed on port %c\n",
2771                                 port_name(port));
2772         }
2773
2774         return;
2775
2776 err:
2777         drm_encoder_cleanup(encoder);
2778         kfree(intel_dig_port);
2779 }