drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42 #include <media/cec-notifier.h>
  43
  44 /**
  45  * __wait_for - magic wait macro
  46  *
  47  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  48  * important that we check the condition again after having timed out, since the
  49  * timeout could be due to preemption or similar and we've never had a chance to
  50  * check the condition before the timeout.
  51  */
  52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  53         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  54         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  55         int ret__;                                                      \
  56         might_sleep();                                                  \
  57         for (;;) {                                                      \
  58                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  59                 OP;                                                     \
  60                 /* Guarantee COND check prior to timeout */             \
  61                 barrier();                                              \
  62                 if (COND) {                                             \
  63                         ret__ = 0;                                      \
  64                         break;                                          \
  65                 }                                                       \
  66                 if (expired__) {                                        \
  67                         ret__ = -ETIMEDOUT;                             \
  68                         break;                                          \
  69                 }                                                       \
  70                 usleep_range(wait__, wait__ * 2);                       \
  71                 if (wait__ < (Wmax))                                    \
  72                         wait__ <<= 1;                                   \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  78                                                    (Wmax))
  79 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  80
  81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  84 #else
  85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  86 #endif
  87
  88 #define _wait_for_atomic(COND, US, ATOMIC) \
  89 ({ \
  90         int cpu, ret, timeout = (US) * 1000; \
  91         u64 base; \
  92         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  93         if (!(ATOMIC)) { \
  94                 preempt_disable(); \
  95                 cpu = smp_processor_id(); \
  96         } \
  97         base = local_clock(); \
  98         for (;;) { \
  99                 u64 now = local_clock(); \
 100                 if (!(ATOMIC)) \
 101                         preempt_enable(); \
 102                 /* Guarantee COND check prior to timeout */ \
 103                 barrier(); \
 104                 if (COND) { \
 105                         ret = 0; \
 106                         break; \
 107                 } \
 108                 if (now - base >= timeout) { \
 109                         ret = -ETIMEDOUT; \
 110                         break; \
 111                 } \
 112                 cpu_relax(); \
 113                 if (!(ATOMIC)) { \
 114                         preempt_disable(); \
 115                         if (unlikely(cpu != smp_processor_id())) { \
 116                                 timeout -= now - base; \
 117                                 cpu = smp_processor_id(); \
 118                                 base = local_clock(); \
 119                         } \
 120                 } \
 121         } \
 122         ret; \
 123 })
 124
 125 #define wait_for_us(COND, US) \
 126 ({ \
 127         int ret__; \
 128         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 129         if ((US) > 10) \
 130                 ret__ = _wait_for((COND), (US), 10, 10); \
 131         else \
 132                 ret__ = _wait_for_atomic((COND), (US), 0); \
 133         ret__; \
 134 })
 135
 136 #define wait_for_atomic_us(COND, US) \
 137 ({ \
 138         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 139         BUILD_BUG_ON((US) > 50000); \
 140         _wait_for_atomic((COND), (US), 1); \
 141 })
 142
 143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 144
 145 #define KHz(x) (1000 * (x))
 146 #define MHz(x) KHz(1000 * (x))
 147
 148 #define KBps(x) (1000 * (x))
 149 #define MBps(x) KBps(1000 * (x))
 150 #define GBps(x) ((u64)1000 * MBps((x)))
 151
 152 /*
 153  * Display related stuff
 154  */
 155
 156 /* store information about an Ixxx DVO */
 157 /* The i830->i865 use multiple DVOs with multiple i2cs */
 158 /* the i915, i945 have a single sDVO i2c bus - which is different */
 159 #define MAX_OUTPUTS 6
 160 /* maximum connectors per crtcs in the mode set */
 161
 162 #define INTEL_I2C_BUS_DVO 1
 163 #define INTEL_I2C_BUS_SDVO 2
 164
 165 /* these are outputs from the chip - integrated only
 166    external chips are via DVO or SDVO output */
 167 enum intel_output_type {
 168         INTEL_OUTPUT_UNUSED = 0,
 169         INTEL_OUTPUT_ANALOG = 1,
 170         INTEL_OUTPUT_DVO = 2,
 171         INTEL_OUTPUT_SDVO = 3,
 172         INTEL_OUTPUT_LVDS = 4,
 173         INTEL_OUTPUT_TVOUT = 5,
 174         INTEL_OUTPUT_HDMI = 6,
 175         INTEL_OUTPUT_DP = 7,
 176         INTEL_OUTPUT_EDP = 8,
 177         INTEL_OUTPUT_DSI = 9,
 178         INTEL_OUTPUT_DDI = 10,
 179         INTEL_OUTPUT_DP_MST = 11,
 180 };
 181
 182 #define INTEL_DVO_CHIP_NONE 0
 183 #define INTEL_DVO_CHIP_LVDS 1
 184 #define INTEL_DVO_CHIP_TMDS 2
 185 #define INTEL_DVO_CHIP_TVOUT 4
 186
 187 #define INTEL_DSI_VIDEO_MODE    0
 188 #define INTEL_DSI_COMMAND_MODE  1
 189
 190 struct intel_framebuffer {
 191         struct drm_framebuffer base;
 192         struct intel_rotation_info rot_info;
 193
 194         /* for each plane in the normal GTT view */
 195         struct {
 196                 unsigned int x, y;
 197         } normal[2];
 198         /* for each plane in the rotated GTT view */
 199         struct {
 200                 unsigned int x, y;
 201                 unsigned int pitch; /* pixels */
 202         } rotated[2];
 203 };
 204
 205 struct intel_fbdev {
 206         struct drm_fb_helper helper;
 207         struct intel_framebuffer *fb;
 208         struct i915_vma *vma;
 209         unsigned long vma_flags;
 210         async_cookie_t cookie;
 211         int preferred_bpp;
 212
 213         /* Whether or not fbdev hpd processing is temporarily suspended */
 214         bool hpd_suspended : 1;
 215         /* Set when a hotplug was received while HPD processing was
 216          * suspended
 217          */
 218         bool hpd_waiting : 1;
 219
 220         /* Protects hpd_suspended */
 221         struct mutex hpd_lock;
 222 };
 223
 224 struct intel_encoder {
 225         struct drm_encoder base;
 226
 227         enum intel_output_type type;
 228         enum port port;
 229         unsigned int cloneable;
 230         bool (*hotplug)(struct intel_encoder *encoder,
 231                         struct intel_connector *connector);
 232         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 233                                                       struct intel_crtc_state *,
 234                                                       struct drm_connector_state *);
 235         bool (*compute_config)(struct intel_encoder *,
 236                                struct intel_crtc_state *,
 237                                struct drm_connector_state *);
 238         void (*pre_pll_enable)(struct intel_encoder *,
 239                                const struct intel_crtc_state *,
 240                                const struct drm_connector_state *);
 241         void (*pre_enable)(struct intel_encoder *,
 242                            const struct intel_crtc_state *,
 243                            const struct drm_connector_state *);
 244         void (*enable)(struct intel_encoder *,
 245                        const struct intel_crtc_state *,
 246                        const struct drm_connector_state *);
 247         void (*disable)(struct intel_encoder *,
 248                         const struct intel_crtc_state *,
 249                         const struct drm_connector_state *);
 250         void (*post_disable)(struct intel_encoder *,
 251                              const struct intel_crtc_state *,
 252                              const struct drm_connector_state *);
 253         void (*post_pll_disable)(struct intel_encoder *,
 254                                  const struct intel_crtc_state *,
 255                                  const struct drm_connector_state *);
 256         /* Read out the current hw state of this connector, returning true if
 257          * the encoder is active. If the encoder is enabled it also set the pipe
 258          * it is connected to in the pipe parameter. */
 259         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 260         /* Reconstructs the equivalent mode flags for the current hardware
 261          * state. This must be called _after_ display->get_pipe_config has
 262          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 263          * be set correctly before calling this function. */
 264         void (*get_config)(struct intel_encoder *,
 265                            struct intel_crtc_state *pipe_config);
 266         /* Returns a mask of power domains that need to be referenced as part
 267          * of the hardware state readout code. */
 268         u64 (*get_power_domains)(struct intel_encoder *encoder,
 269                                  struct intel_crtc_state *crtc_state);
 270         /*
 271          * Called during system suspend after all pending requests for the
 272          * encoder are flushed (for example for DP AUX transactions) and
 273          * device interrupts are disabled.
 274          */
 275         void (*suspend)(struct intel_encoder *);
 276         int crtc_mask;
 277         enum hpd_pin hpd_pin;
 278         enum intel_display_power_domain power_domain;
 279         /* for communication with audio component; protected by av_mutex */
 280         const struct drm_connector *audio_connector;
 281 };
 282
 283 struct intel_panel {
 284         struct drm_display_mode *fixed_mode;
 285         struct drm_display_mode *downclock_mode;
 286
 287         /* backlight */
 288         struct {
 289                 bool present;
 290                 u32 level;
 291                 u32 min;
 292                 u32 max;
 293                 bool enabled;
 294                 bool combination_mode;  /* gen 2/4 only */
 295                 bool active_low_pwm;
 296                 bool alternate_pwm_increment;   /* lpt+ */
 297
 298                 /* PWM chip */
 299                 bool util_pin_active_low;       /* bxt+ */
 300                 u8 controller;          /* bxt+ only */
 301                 struct pwm_device *pwm;
 302
 303                 struct backlight_device *device;
 304
 305                 /* Connector and platform specific backlight functions */
 306                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 307                 uint32_t (*get)(struct intel_connector *connector);
 308                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 309                 void (*disable)(const struct drm_connector_state *conn_state);
 310                 void (*enable)(const struct intel_crtc_state *crtc_state,
 311                                const struct drm_connector_state *conn_state);
 312                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 313                                       uint32_t hz);
 314                 void (*power)(struct intel_connector *, bool enable);
 315         } backlight;
 316 };
 317
 318 struct intel_digital_port;
 319
 320 /*
 321  * This structure serves as a translation layer between the generic HDCP code
 322  * and the bus-specific code. What that means is that HDCP over HDMI differs
 323  * from HDCP over DP, so to account for these differences, we need to
 324  * communicate with the receiver through this shim.
 325  *
 326  * For completeness, the 2 buses differ in the following ways:
 327  *      - DP AUX vs. DDC
 328  *              HDCP registers on the receiver are set via DP AUX for DP, and
 329  *              they are set via DDC for HDMI.
 330  *      - Receiver register offsets
 331  *              The offsets of the registers are different for DP vs. HDMI
 332  *      - Receiver register masks/offsets
 333  *              For instance, the ready bit for the KSV fifo is in a different
 334  *              place on DP vs HDMI
 335  *      - Receiver register names
 336  *              Seriously. In the DP spec, the 16-bit register containing
 337  *              downstream information is called BINFO, on HDMI it's called
 338  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 339  *              with a completely different definition.
 340  *      - KSV FIFO
 341  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 342  *              be read 3 keys at a time
 343  *      - Aksv output
 344  *              Since Aksv is hidden in hardware, there's different procedures
 345  *              to send it over DP AUX vs DDC
 346  */
 347 struct intel_hdcp_shim {
 348         /* Outputs the transmitter's An and Aksv values to the receiver. */
 349         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 350
 351         /* Reads the receiver's key selection vector */
 352         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 353
 354         /*
 355          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 356          * definitions are the same in the respective specs, but the names are
 357          * different. Call it BSTATUS since that's the name the HDMI spec
 358          * uses and it was there first.
 359          */
 360         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 361                             u8 *bstatus);
 362
 363         /* Determines whether a repeater is present downstream */
 364         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 365                                 bool *repeater_present);
 366
 367         /* Reads the receiver's Ri' value */
 368         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 369
 370         /* Determines if the receiver's KSV FIFO is ready for consumption */
 371         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 372                               bool *ksv_ready);
 373
 374         /* Reads the ksv fifo for num_downstream devices */
 375         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 376                              int num_downstream, u8 *ksv_fifo);
 377
 378         /* Reads a 32-bit part of V' from the receiver */
 379         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 380                                  int i, u32 *part);
 381
 382         /* Enables HDCP signalling on the port */
 383         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 384                                  bool enable);
 385
 386         /* Ensures the link is still protected */
 387         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 388
 389         /* Detects panel's hdcp capability. This is optional for HDMI. */
 390         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 391                             bool *hdcp_capable);
 392 };
 393
 394 struct intel_connector {
 395         struct drm_connector base;
 396         /*
 397          * The fixed encoder this connector is connected to.
 398          */
 399         struct intel_encoder *encoder;
 400
 401         /* ACPI device id for ACPI and driver cooperation */
 402         u32 acpi_device_id;
 403
 404         /* Reads out the current hw, returning true if the connector is enabled
 405          * and active (i.e. dpms ON state). */
 406         bool (*get_hw_state)(struct intel_connector *);
 407
 408         /* Panel info for eDP and LVDS */
 409         struct intel_panel panel;
 410
 411         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 412         struct edid *edid;
 413         struct edid *detect_edid;
 414
 415         /* since POLL and HPD connectors may use the same HPD line keep the native
 416            state of connector->polled in case hotplug storm detection changes it */
 417         u8 polled;
 418
 419         void *port; /* store this opaque as its illegal to dereference it */
 420
 421         struct intel_dp *mst_port;
 422
 423         /* Work struct to schedule a uevent on link train failure */
 424         struct work_struct modeset_retry_work;
 425
 426         const struct intel_hdcp_shim *hdcp_shim;
 427         struct mutex hdcp_mutex;
 428         uint64_t hdcp_value; /* protected by hdcp_mutex */
 429         struct delayed_work hdcp_check_work;
 430         struct work_struct hdcp_prop_work;
 431 };
 432
 433 struct intel_digital_connector_state {
 434         struct drm_connector_state base;
 435
 436         enum hdmi_force_audio force_audio;
 437         int broadcast_rgb;
 438 };
 439
 440 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 441
 442 struct dpll {
 443         /* given values */
 444         int n;
 445         int m1, m2;
 446         int p1, p2;
 447         /* derived values */
 448         int     dot;
 449         int     vco;
 450         int     m;
 451         int     p;
 452 };
 453
 454 struct intel_atomic_state {
 455         struct drm_atomic_state base;
 456
 457         struct {
 458                 /*
 459                  * Logical state of cdclk (used for all scaling, watermark,
 460                  * etc. calculations and checks). This is computed as if all
 461                  * enabled crtcs were active.
 462                  */
 463                 struct intel_cdclk_state logical;
 464
 465                 /*
 466                  * Actual state of cdclk, can be different from the logical
 467                  * state only when all crtc's are DPMS off.
 468                  */
 469                 struct intel_cdclk_state actual;
 470         } cdclk;
 471
 472         bool dpll_set, modeset;
 473
 474         /*
 475          * Does this transaction change the pipes that are active?  This mask
 476          * tracks which CRTC's have changed their active state at the end of
 477          * the transaction (not counting the temporary disable during modesets).
 478          * This mask should only be non-zero when intel_state->modeset is true,
 479          * but the converse is not necessarily true; simply changing a mode may
 480          * not flip the final active status of any CRTC's
 481          */
 482         unsigned int active_pipe_changes;
 483
 484         unsigned int active_crtcs;
 485         /* minimum acceptable cdclk for each pipe */
 486         int min_cdclk[I915_MAX_PIPES];
 487         /* minimum acceptable voltage level for each pipe */
 488         u8 min_voltage_level[I915_MAX_PIPES];
 489
 490         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 491
 492         /*
 493          * Current watermarks can't be trusted during hardware readout, so
 494          * don't bother calculating intermediate watermarks.
 495          */
 496         bool skip_intermediate_wm;
 497
 498         bool rps_interactive;
 499
 500         /* Gen9+ only */
 501         struct skl_ddb_values wm_results;
 502
 503         struct i915_sw_fence commit_ready;
 504
 505         struct llist_node freed;
 506 };
 507
 508 struct intel_plane_state {
 509         struct drm_plane_state base;
 510         struct i915_vma *vma;
 511         unsigned long flags;
 512 #define PLANE_HAS_FENCE BIT(0)
 513
 514         struct {
 515                 u32 offset;
 516                 int x, y;
 517         } main;
 518         struct {
 519                 u32 offset;
 520                 int x, y;
 521         } aux;
 522
 523         /* plane control register */
 524         u32 ctl;
 525
 526         /* plane color control register */
 527         u32 color_ctl;
 528
 529         /*
 530          * scaler_id
 531          *    = -1 : not using a scaler
 532          *    >=  0 : using a scalers
 533          *
 534          * plane requiring a scaler:
 535          *   - During check_plane, its bit is set in
 536          *     crtc_state->scaler_state.scaler_users by calling helper function
 537          *     update_scaler_plane.
 538          *   - scaler_id indicates the scaler it got assigned.
 539          *
 540          * plane doesn't require a scaler:
 541          *   - this can happen when scaling is no more required or plane simply
 542          *     got disabled.
 543          *   - During check_plane, corresponding bit is reset in
 544          *     crtc_state->scaler_state.scaler_users by calling helper function
 545          *     update_scaler_plane.
 546          */
 547         int scaler_id;
 548
 549         struct drm_intel_sprite_colorkey ckey;
 550 };
 551
 552 struct intel_initial_plane_config {
 553         struct intel_framebuffer *fb;
 554         unsigned int tiling;
 555         int size;
 556         u32 base;
 557 };
 558
 559 #define SKL_MIN_SRC_W 8
 560 #define SKL_MAX_SRC_W 4096
 561 #define SKL_MIN_SRC_H 8
 562 #define SKL_MAX_SRC_H 4096
 563 #define SKL_MIN_DST_W 8
 564 #define SKL_MAX_DST_W 4096
 565 #define SKL_MIN_DST_H 8
 566 #define SKL_MAX_DST_H 4096
 567 #define ICL_MAX_SRC_W 5120
 568 #define ICL_MAX_SRC_H 4096
 569 #define ICL_MAX_DST_W 5120
 570 #define ICL_MAX_DST_H 4096
 571 #define SKL_MIN_YUV_420_SRC_W 16
 572 #define SKL_MIN_YUV_420_SRC_H 16
 573
 574 struct intel_scaler {
 575         int in_use;
 576         uint32_t mode;
 577 };
 578
 579 struct intel_crtc_scaler_state {
 580 #define SKL_NUM_SCALERS 2
 581         struct intel_scaler scalers[SKL_NUM_SCALERS];
 582
 583         /*
 584          * scaler_users: keeps track of users requesting scalers on this crtc.
 585          *
 586          *     If a bit is set, a user is using a scaler.
 587          *     Here user can be a plane or crtc as defined below:
 588          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 589          *       bit 31    - crtc
 590          *
 591          * Instead of creating a new index to cover planes and crtc, using
 592          * existing drm_plane_index for planes which is well less than 31
 593          * planes and bit 31 for crtc. This should be fine to cover all
 594          * our platforms.
 595          *
 596          * intel_atomic_setup_scalers will setup available scalers to users
 597          * requesting scalers. It will gracefully fail if request exceeds
 598          * avilability.
 599          */
 600 #define SKL_CRTC_INDEX 31
 601         unsigned scaler_users;
 602
 603         /* scaler used by crtc for panel fitting purpose */
 604         int scaler_id;
 605 };
 606
 607 /* drm_mode->private_flags */
 608 #define I915_MODE_FLAG_INHERITED 1
 609 /* Flag to get scanline using frame time stamps */
 610 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 611
 612 struct intel_pipe_wm {
 613         struct intel_wm_level wm[5];
 614         uint32_t linetime;
 615         bool fbc_wm_enabled;
 616         bool pipe_enabled;
 617         bool sprites_enabled;
 618         bool sprites_scaled;
 619 };
 620
 621 struct skl_plane_wm {
 622         struct skl_wm_level wm[8];
 623         struct skl_wm_level uv_wm[8];
 624         struct skl_wm_level trans_wm;
 625         bool is_planar;
 626 };
 627
 628 struct skl_pipe_wm {
 629         struct skl_plane_wm planes[I915_MAX_PLANES];
 630         uint32_t linetime;
 631 };
 632
 633 enum vlv_wm_level {
 634         VLV_WM_LEVEL_PM2,
 635         VLV_WM_LEVEL_PM5,
 636         VLV_WM_LEVEL_DDR_DVFS,
 637         NUM_VLV_WM_LEVELS,
 638 };
 639
 640 struct vlv_wm_state {
 641         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 642         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 643         uint8_t num_levels;
 644         bool cxsr;
 645 };
 646
 647 struct vlv_fifo_state {
 648         u16 plane[I915_MAX_PLANES];
 649 };
 650
 651 enum g4x_wm_level {
 652         G4X_WM_LEVEL_NORMAL,
 653         G4X_WM_LEVEL_SR,
 654         G4X_WM_LEVEL_HPLL,
 655         NUM_G4X_WM_LEVELS,
 656 };
 657
 658 struct g4x_wm_state {
 659         struct g4x_pipe_wm wm;
 660         struct g4x_sr_wm sr;
 661         struct g4x_sr_wm hpll;
 662         bool cxsr;
 663         bool hpll_en;
 664         bool fbc_en;
 665 };
 666
 667 struct intel_crtc_wm_state {
 668         union {
 669                 struct {
 670                         /*
 671                          * Intermediate watermarks; these can be
 672                          * programmed immediately since they satisfy
 673                          * both the current configuration we're
 674                          * switching away from and the new
 675                          * configuration we're switching to.
 676                          */
 677                         struct intel_pipe_wm intermediate;
 678
 679                         /*
 680                          * Optimal watermarks, programmed post-vblank
 681                          * when this state is committed.
 682                          */
 683                         struct intel_pipe_wm optimal;
 684                 } ilk;
 685
 686                 struct {
 687                         /* gen9+ only needs 1-step wm programming */
 688                         struct skl_pipe_wm optimal;
 689                         struct skl_ddb_entry ddb;
 690                 } skl;
 691
 692                 struct {
 693                         /* "raw" watermarks (not inverted) */
 694                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 695                         /* intermediate watermarks (inverted) */
 696                         struct vlv_wm_state intermediate;
 697                         /* optimal watermarks (inverted) */
 698                         struct vlv_wm_state optimal;
 699                         /* display FIFO split */
 700                         struct vlv_fifo_state fifo_state;
 701                 } vlv;
 702
 703                 struct {
 704                         /* "raw" watermarks */
 705                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 706                         /* intermediate watermarks */
 707                         struct g4x_wm_state intermediate;
 708                         /* optimal watermarks */
 709                         struct g4x_wm_state optimal;
 710                 } g4x;
 711         };
 712
 713         /*
 714          * Platforms with two-step watermark programming will need to
 715          * update watermark programming post-vblank to switch from the
 716          * safe intermediate watermarks to the optimal final
 717          * watermarks.
 718          */
 719         bool need_postvbl_update;
 720 };
 721
 722 struct intel_crtc_state {
 723         struct drm_crtc_state base;
 724
 725         /**
 726          * quirks - bitfield with hw state readout quirks
 727          *
 728          * For various reasons the hw state readout code might not be able to
 729          * completely faithfully read out the current state. These cases are
 730          * tracked with quirk flags so that fastboot and state checker can act
 731          * accordingly.
 732          */
 733 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 734         unsigned long quirks;
 735
 736         unsigned fb_bits; /* framebuffers to flip */
 737         bool update_pipe; /* can a fast modeset be performed? */
 738         bool disable_cxsr;
 739         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 740         bool fb_changed; /* fb on any of the planes is changed */
 741         bool fifo_changed; /* FIFO split is changed */
 742
 743         /* Pipe source size (ie. panel fitter input size)
 744          * All planes will be positioned inside this space,
 745          * and get clipped at the edges. */
 746         int pipe_src_w, pipe_src_h;
 747
 748         /*
 749          * Pipe pixel rate, adjusted for
 750          * panel fitter/pipe scaler downscaling.
 751          */
 752         unsigned int pixel_rate;
 753
 754         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 755          * between pch encoders and cpu encoders. */
 756         bool has_pch_encoder;
 757
 758         /* Are we sending infoframes on the attached port */
 759         bool has_infoframe;
 760
 761         /* CPU Transcoder for the pipe. Currently this can only differ from the
 762          * pipe on Haswell and later (where we have a special eDP transcoder)
 763          * and Broxton (where we have special DSI transcoders). */
 764         enum transcoder cpu_transcoder;
 765
 766         /*
 767          * Use reduced/limited/broadcast rbg range, compressing from the full
 768          * range fed into the crtcs.
 769          */
 770         bool limited_color_range;
 771
 772         /* Bitmask of encoder types (enum intel_output_type)
 773          * driven by the pipe.
 774          */
 775         unsigned int output_types;
 776
 777         /* Whether we should send NULL infoframes. Required for audio. */
 778         bool has_hdmi_sink;
 779
 780         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 781          * has_dp_encoder is set. */
 782         bool has_audio;
 783
 784         /*
 785          * Enable dithering, used when the selected pipe bpp doesn't match the
 786          * plane bpp.
 787          */
 788         bool dither;
 789
 790         /*
 791          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 792          * compliance video pattern tests.
 793          * Disable dither only if it is a compliance test request for
 794          * 18bpp.
 795          */
 796         bool dither_force_disable;
 797
 798         /* Controls for the clock computation, to override various stages. */
 799         bool clock_set;
 800
 801         /* SDVO TV has a bunch of special case. To make multifunction encoders
 802          * work correctly, we need to track this at runtime.*/
 803         bool sdvo_tv_clock;
 804
 805         /*
 806          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 807          * required. This is set in the 2nd loop of calling encoder's
 808          * ->compute_config if the first pick doesn't work out.
 809          */
 810         bool bw_constrained;
 811
 812         /* Settings for the intel dpll used on pretty much everything but
 813          * haswell. */
 814         struct dpll dpll;
 815
 816         /* Selected dpll when shared or NULL. */
 817         struct intel_shared_dpll *shared_dpll;
 818
 819         /* Actual register state of the dpll, for shared dpll cross-checking. */
 820         struct intel_dpll_hw_state dpll_hw_state;
 821
 822         /* DSI PLL registers */
 823         struct {
 824                 u32 ctrl, div;
 825         } dsi_pll;
 826
 827         int pipe_bpp;
 828         struct intel_link_m_n dp_m_n;
 829
 830         /* m2_n2 for eDP downclock */
 831         struct intel_link_m_n dp_m2_n2;
 832         bool has_drrs;
 833
 834         bool has_psr;
 835         bool has_psr2;
 836
 837         /*
 838          * Frequence the dpll for the port should run at. Differs from the
 839          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 840          * already multiplied by pixel_multiplier.
 841          */
 842         int port_clock;
 843
 844         /* Used by SDVO (and if we ever fix it, HDMI). */
 845         unsigned pixel_multiplier;
 846
 847         uint8_t lane_count;
 848
 849         /*
 850          * Used by platforms having DP/HDMI PHY with programmable lane
 851          * latency optimization.
 852          */
 853         uint8_t lane_lat_optim_mask;
 854
 855         /* minimum acceptable voltage level */
 856         u8 min_voltage_level;
 857
 858         /* Panel fitter controls for gen2-gen4 + VLV */
 859         struct {
 860                 u32 control;
 861                 u32 pgm_ratios;
 862                 u32 lvds_border_bits;
 863         } gmch_pfit;
 864
 865         /* Panel fitter placement and size for Ironlake+ */
 866         struct {
 867                 u32 pos;
 868                 u32 size;
 869                 bool enabled;
 870                 bool force_thru;
 871         } pch_pfit;
 872
 873         /* FDI configuration, only valid if has_pch_encoder is set. */
 874         int fdi_lanes;
 875         struct intel_link_m_n fdi_m_n;
 876
 877         bool ips_enabled;
 878         bool ips_force_disable;
 879
 880         bool enable_fbc;
 881
 882         bool double_wide;
 883
 884         int pbn;
 885
 886         struct intel_crtc_scaler_state scaler_state;
 887
 888         /* w/a for waiting 2 vblanks during crtc enable */
 889         enum pipe hsw_workaround_pipe;
 890
 891         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 892         bool disable_lp_wm;
 893
 894         struct intel_crtc_wm_state wm;
 895
 896         /* Gamma mode programmed on the pipe */
 897         uint32_t gamma_mode;
 898
 899         /* bitmask of visible planes (enum plane_id) */
 900         u8 active_planes;
 901         u8 nv12_planes;
 902
 903         /* HDMI scrambling status */
 904         bool hdmi_scrambling;
 905
 906         /* HDMI High TMDS char rate ratio */
 907         bool hdmi_high_tmds_clock_ratio;
 908
 909         /* output format is YCBCR 4:2:0 */
 910         bool ycbcr420;
 911 };
 912
 913 struct intel_crtc {
 914         struct drm_crtc base;
 915         enum pipe pipe;
 916         /*
 917          * Whether the crtc and the connected output pipeline is active. Implies
 918          * that crtc->enabled is set, i.e. the current mode configuration has
 919          * some outputs connected to this crtc.
 920          */
 921         bool active;
 922         u8 plane_ids_mask;
 923         unsigned long long enabled_power_domains;
 924         struct intel_overlay *overlay;
 925
 926         struct intel_crtc_state *config;
 927
 928         /* global reset count when the last flip was submitted */
 929         unsigned int reset_count;
 930
 931         /* Access to these should be protected by dev_priv->irq_lock. */
 932         bool cpu_fifo_underrun_disabled;
 933         bool pch_fifo_underrun_disabled;
 934
 935         /* per-pipe watermark state */
 936         struct {
 937                 /* watermarks currently being used  */
 938                 union {
 939                         struct intel_pipe_wm ilk;
 940                         struct vlv_wm_state vlv;
 941                         struct g4x_wm_state g4x;
 942                 } active;
 943         } wm;
 944
 945         int scanline_offset;
 946
 947         struct {
 948                 unsigned start_vbl_count;
 949                 ktime_t start_vbl_time;
 950                 int min_vbl, max_vbl;
 951                 int scanline_start;
 952         } debug;
 953
 954         /* scalers available on this crtc */
 955         int num_scalers;
 956 };
 957
 958 struct intel_plane {
 959         struct drm_plane base;
 960         enum i9xx_plane_id i9xx_plane;
 961         enum plane_id id;
 962         enum pipe pipe;
 963         bool can_scale;
 964         bool has_fbc;
 965         bool has_ccs;
 966         int max_downscale;
 967         uint32_t frontbuffer_bit;
 968
 969         struct {
 970                 u32 base, cntl, size;
 971         } cursor;
 972
 973         /*
 974          * NOTE: Do not place new plane state fields here (e.g., when adding
 975          * new plane properties).  New runtime state should now be placed in
 976          * the intel_plane_state structure and accessed via plane_state.
 977          */
 978
 979         void (*update_plane)(struct intel_plane *plane,
 980                              const struct intel_crtc_state *crtc_state,
 981                              const struct intel_plane_state *plane_state);
 982         void (*disable_plane)(struct intel_plane *plane,
 983                               struct intel_crtc *crtc);
 984         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
 985         int (*check_plane)(struct intel_plane *plane,
 986                            struct intel_crtc_state *crtc_state,
 987                            struct intel_plane_state *state);
 988 };
 989
 990 struct intel_watermark_params {
 991         u16 fifo_size;
 992         u16 max_wm;
 993         u8 default_wm;
 994         u8 guard_size;
 995         u8 cacheline_size;
 996 };
 997
 998 struct cxsr_latency {
 999         bool is_desktop : 1;
1000         bool is_ddr3 : 1;
1001         u16 fsb_freq;
1002         u16 mem_freq;
1003         u16 display_sr;
1004         u16 display_hpll_disable;
1005         u16 cursor_sr;
1006         u16 cursor_hpll_disable;
1007 };
1008
1009 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1010 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1011 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1012 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1013 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1014 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1015 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1016 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1017 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1018
1019 struct intel_hdmi {
1020         i915_reg_t hdmi_reg;
1021         int ddc_bus;
1022         struct {
1023                 enum drm_dp_dual_mode_type type;
1024                 int max_tmds_clock;
1025         } dp_dual_mode;
1026         bool has_hdmi_sink;
1027         bool has_audio;
1028         bool rgb_quant_range_selectable;
1029         struct intel_connector *attached_connector;
1030         struct cec_notifier *cec_notifier;
1031 };
1032
1033 struct intel_dp_mst_encoder;
1034 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1035
1036 /*
1037  * enum link_m_n_set:
1038  *      When platform provides two set of M_N registers for dp, we can
1039  *      program them and switch between them incase of DRRS.
1040  *      But When only one such register is provided, we have to program the
1041  *      required divider value on that registers itself based on the DRRS state.
1042  *
1043  * M1_N1        : Program dp_m_n on M1_N1 registers
1044  *                        dp_m2_n2 on M2_N2 registers (If supported)
1045  *
1046  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1047  *                        M2_N2 registers are not supported
1048  */
1049
1050 enum link_m_n_set {
1051         /* Sets the m1_n1 and m2_n2 */
1052         M1_N1 = 0,
1053         M2_N2
1054 };
1055
1056 struct intel_dp_compliance_data {
1057         unsigned long edid;
1058         uint8_t video_pattern;
1059         uint16_t hdisplay, vdisplay;
1060         uint8_t bpc;
1061 };
1062
1063 struct intel_dp_compliance {
1064         unsigned long test_type;
1065         struct intel_dp_compliance_data test_data;
1066         bool test_active;
1067         int test_link_rate;
1068         u8 test_lane_count;
1069 };
1070
1071 struct intel_dp {
1072         i915_reg_t output_reg;
1073         uint32_t DP;
1074         int link_rate;
1075         uint8_t lane_count;
1076         uint8_t sink_count;
1077         bool link_mst;
1078         bool link_trained;
1079         bool has_audio;
1080         bool detect_done;
1081         bool reset_link_params;
1082         enum aux_ch aux_ch;
1083         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1084         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1085         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1086         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1087         /* source rates */
1088         int num_source_rates;
1089         const int *source_rates;
1090         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1091         int num_sink_rates;
1092         int sink_rates[DP_MAX_SUPPORTED_RATES];
1093         bool use_rate_select;
1094         /* intersection of source and sink rates */
1095         int num_common_rates;
1096         int common_rates[DP_MAX_SUPPORTED_RATES];
1097         /* Max lane count for the current link */
1098         int max_link_lane_count;
1099         /* Max rate for the current link */
1100         int max_link_rate;
1101         /* sink or branch descriptor */
1102         struct drm_dp_desc desc;
1103         struct drm_dp_aux aux;
1104         enum intel_display_power_domain aux_power_domain;
1105         uint8_t train_set[4];
1106         int panel_power_up_delay;
1107         int panel_power_down_delay;
1108         int panel_power_cycle_delay;
1109         int backlight_on_delay;
1110         int backlight_off_delay;
1111         struct delayed_work panel_vdd_work;
1112         bool want_panel_vdd;
1113         unsigned long last_power_on;
1114         unsigned long last_backlight_off;
1115         ktime_t panel_power_off_time;
1116
1117         struct notifier_block edp_notifier;
1118
1119         /*
1120          * Pipe whose power sequencer is currently locked into
1121          * this port. Only relevant on VLV/CHV.
1122          */
1123         enum pipe pps_pipe;
1124         /*
1125          * Pipe currently driving the port. Used for preventing
1126          * the use of the PPS for any pipe currentrly driving
1127          * external DP as that will mess things up on VLV.
1128          */
1129         enum pipe active_pipe;
1130         /*
1131          * Set if the sequencer may be reset due to a power transition,
1132          * requiring a reinitialization. Only relevant on BXT.
1133          */
1134         bool pps_reset;
1135         struct edp_power_seq pps_delays;
1136
1137         bool can_mst; /* this port supports mst */
1138         bool is_mst;
1139         int active_mst_links;
1140         /* connector directly attached - won't be use for modeset in mst world */
1141         struct intel_connector *attached_connector;
1142
1143         /* mst connector list */
1144         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1145         struct drm_dp_mst_topology_mgr mst_mgr;
1146
1147         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1148         /*
1149          * This function returns the value we have to program the AUX_CTL
1150          * register with to kick off an AUX transaction.
1151          */
1152         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1153                                      int send_bytes,
1154                                      uint32_t aux_clock_divider);
1155
1156         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1157         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1158
1159         /* This is called before a link training is starterd */
1160         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1161
1162         /* Displayport compliance testing */
1163         struct intel_dp_compliance compliance;
1164 };
1165
1166 struct intel_lspcon {
1167         bool active;
1168         enum drm_lspcon_mode mode;
1169 };
1170
1171 struct intel_digital_port {
1172         struct intel_encoder base;
1173         u32 saved_port_bits;
1174         struct intel_dp dp;
1175         struct intel_hdmi hdmi;
1176         struct intel_lspcon lspcon;
1177         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1178         bool release_cl2_override;
1179         uint8_t max_lanes;
1180         enum intel_display_power_domain ddi_io_power_domain;
1181
1182         void (*write_infoframe)(struct drm_encoder *encoder,
1183                                 const struct intel_crtc_state *crtc_state,
1184                                 unsigned int type,
1185                                 const void *frame, ssize_t len);
1186         void (*set_infoframes)(struct drm_encoder *encoder,
1187                                bool enable,
1188                                const struct intel_crtc_state *crtc_state,
1189                                const struct drm_connector_state *conn_state);
1190         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1191                                   const struct intel_crtc_state *pipe_config);
1192 };
1193
1194 struct intel_dp_mst_encoder {
1195         struct intel_encoder base;
1196         enum pipe pipe;
1197         struct intel_digital_port *primary;
1198         struct intel_connector *connector;
1199 };
1200
1201 static inline enum dpio_channel
1202 vlv_dport_to_channel(struct intel_digital_port *dport)
1203 {
1204         switch (dport->base.port) {
1205         case PORT_B:
1206         case PORT_D:
1207                 return DPIO_CH0;
1208         case PORT_C:
1209                 return DPIO_CH1;
1210         default:
1211                 BUG();
1212         }
1213 }
1214
1215 static inline enum dpio_phy
1216 vlv_dport_to_phy(struct intel_digital_port *dport)
1217 {
1218         switch (dport->base.port) {
1219         case PORT_B:
1220         case PORT_C:
1221                 return DPIO_PHY0;
1222         case PORT_D:
1223                 return DPIO_PHY1;
1224         default:
1225                 BUG();
1226         }
1227 }
1228
1229 static inline enum dpio_channel
1230 vlv_pipe_to_channel(enum pipe pipe)
1231 {
1232         switch (pipe) {
1233         case PIPE_A:
1234         case PIPE_C:
1235                 return DPIO_CH0;
1236         case PIPE_B:
1237                 return DPIO_CH1;
1238         default:
1239                 BUG();
1240         }
1241 }
1242
1243 static inline struct intel_crtc *
1244 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1245 {
1246         return dev_priv->pipe_to_crtc_mapping[pipe];
1247 }
1248
1249 static inline struct intel_crtc *
1250 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1251 {
1252         return dev_priv->plane_to_crtc_mapping[plane];
1253 }
1254
1255 struct intel_load_detect_pipe {
1256         struct drm_atomic_state *restore_state;
1257 };
1258
1259 static inline struct intel_encoder *
1260 intel_attached_encoder(struct drm_connector *connector)
1261 {
1262         return to_intel_connector(connector)->encoder;
1263 }
1264
1265 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1266 {
1267         switch (encoder->type) {
1268         case INTEL_OUTPUT_DDI:
1269         case INTEL_OUTPUT_DP:
1270         case INTEL_OUTPUT_EDP:
1271         case INTEL_OUTPUT_HDMI:
1272                 return true;
1273         default:
1274                 return false;
1275         }
1276 }
1277
1278 static inline struct intel_digital_port *
1279 enc_to_dig_port(struct drm_encoder *encoder)
1280 {
1281         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1282
1283         if (intel_encoder_is_dig_port(intel_encoder))
1284                 return container_of(encoder, struct intel_digital_port,
1285                                     base.base);
1286         else
1287                 return NULL;
1288 }
1289
1290 static inline struct intel_dp_mst_encoder *
1291 enc_to_mst(struct drm_encoder *encoder)
1292 {
1293         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1294 }
1295
1296 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1297 {
1298         return &enc_to_dig_port(encoder)->dp;
1299 }
1300
1301 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1302 {
1303         switch (encoder->type) {
1304         case INTEL_OUTPUT_DP:
1305         case INTEL_OUTPUT_EDP:
1306                 return true;
1307         case INTEL_OUTPUT_DDI:
1308                 /* Skip pure HDMI/DVI DDI encoders */
1309                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1310         default:
1311                 return false;
1312         }
1313 }
1314
1315 static inline struct intel_digital_port *
1316 dp_to_dig_port(struct intel_dp *intel_dp)
1317 {
1318         return container_of(intel_dp, struct intel_digital_port, dp);
1319 }
1320
1321 static inline struct intel_lspcon *
1322 dp_to_lspcon(struct intel_dp *intel_dp)
1323 {
1324         return &dp_to_dig_port(intel_dp)->lspcon;
1325 }
1326
1327 static inline struct intel_digital_port *
1328 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1329 {
1330         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1331 }
1332
1333 static inline struct intel_plane_state *
1334 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1335                                  struct intel_plane *plane)
1336 {
1337         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1338                                                                    &plane->base));
1339 }
1340
1341 static inline struct intel_crtc_state *
1342 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1343                                 struct intel_crtc *crtc)
1344 {
1345         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1346                                                                  &crtc->base));
1347 }
1348
1349 static inline struct intel_crtc_state *
1350 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1351                                 struct intel_crtc *crtc)
1352 {
1353         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1354                                                                  &crtc->base));
1355 }
1356
1357 /* intel_fifo_underrun.c */
1358 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1359                                            enum pipe pipe, bool enable);
1360 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1361                                            enum pipe pch_transcoder,
1362                                            bool enable);
1363 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1364                                          enum pipe pipe);
1365 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1366                                          enum pipe pch_transcoder);
1367 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1368 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1369
1370 /* i915_irq.c */
1371 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1372 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1373 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1374 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1375 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1376 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1377 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1378 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1379
1380 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1381                                             u32 mask)
1382 {
1383         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1384 }
1385
1386 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1387 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1388 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1389 {
1390         /*
1391          * We only use drm_irq_uninstall() at unload and VT switch, so
1392          * this is the only thing we need to check.
1393          */
1394         return dev_priv->runtime_pm.irqs_enabled;
1395 }
1396
1397 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1398 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1399                                      u8 pipe_mask);
1400 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1401                                      u8 pipe_mask);
1402 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1403 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1404 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1405
1406 /* intel_crt.c */
1407 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1408                             i915_reg_t adpa_reg, enum pipe *pipe);
1409 void intel_crt_init(struct drm_i915_private *dev_priv);
1410 void intel_crt_reset(struct drm_encoder *encoder);
1411
1412 /* intel_ddi.c */
1413 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1414                                 const struct intel_crtc_state *old_crtc_state,
1415                                 const struct drm_connector_state *old_conn_state);
1416 void hsw_fdi_link_train(struct intel_crtc *crtc,
1417                         const struct intel_crtc_state *crtc_state);
1418 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1419 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1420 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1421 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1422 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1423 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1424 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1425 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1426 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1427 void intel_ddi_get_config(struct intel_encoder *encoder,
1428                           struct intel_crtc_state *pipe_config);
1429
1430 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1431                                     bool state);
1432 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1433                                          struct intel_crtc_state *crtc_state);
1434 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1435 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1436 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1437 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1438                                  u8 voltage_swing);
1439 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1440                                      bool enable);
1441 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1442                            struct intel_crtc_state *crtc_state,
1443                            struct drm_atomic_state *old_state);
1444 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1445                              struct intel_crtc_state *crtc_state,
1446                              struct drm_atomic_state *old_state);
1447
1448 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1449                                    int plane, unsigned int height);
1450
1451 /* intel_audio.c */
1452 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1453 void intel_audio_codec_enable(struct intel_encoder *encoder,
1454                               const struct intel_crtc_state *crtc_state,
1455                               const struct drm_connector_state *conn_state);
1456 void intel_audio_codec_disable(struct intel_encoder *encoder,
1457                                const struct intel_crtc_state *old_crtc_state,
1458                                const struct drm_connector_state *old_conn_state);
1459 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1460 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1461 void intel_audio_init(struct drm_i915_private *dev_priv);
1462 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1463
1464 /* intel_cdclk.c */
1465 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1466 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1467 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1468 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1469 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1470 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1471 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1472 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1473 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1474 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1475 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1476 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1477 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1478 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1479                                const struct intel_cdclk_state *b);
1480 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1481                          const struct intel_cdclk_state *b);
1482 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1483                      const struct intel_cdclk_state *cdclk_state);
1484 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1485                             const char *context);
1486
1487 /* intel_display.c */
1488 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1489 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1490 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1491 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1492 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1493 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1494                       const char *name, u32 reg, int ref_freq);
1495 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1496                            const char *name, u32 reg);
1497 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1498 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1499 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1500 unsigned int intel_fb_xy_to_linear(int x, int y,
1501                                    const struct intel_plane_state *state,
1502                                    int plane);
1503 void intel_add_fb_offsets(int *x, int *y,
1504                           const struct intel_plane_state *state, int plane);
1505 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1506 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1507 void intel_mark_busy(struct drm_i915_private *dev_priv);
1508 void intel_mark_idle(struct drm_i915_private *dev_priv);
1509 int intel_display_suspend(struct drm_device *dev);
1510 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1511 void intel_encoder_destroy(struct drm_encoder *encoder);
1512 int intel_connector_init(struct intel_connector *);
1513 struct intel_connector *intel_connector_alloc(void);
1514 void intel_connector_free(struct intel_connector *connector);
1515 bool intel_connector_get_hw_state(struct intel_connector *connector);
1516 void intel_connector_attach_encoder(struct intel_connector *connector,
1517                                     struct intel_encoder *encoder);
1518 struct drm_display_mode *
1519 intel_encoder_current_mode(struct intel_encoder *encoder);
1520 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1521 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1522                               enum port port);
1523
1524 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1525 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1526                                       struct drm_file *file_priv);
1527 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1528                                              enum pipe pipe);
1529 static inline bool
1530 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1531                     enum intel_output_type type)
1532 {
1533         return crtc_state->output_types & (1 << type);
1534 }
1535 static inline bool
1536 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1537 {
1538         return crtc_state->output_types &
1539                 ((1 << INTEL_OUTPUT_DP) |
1540                  (1 << INTEL_OUTPUT_DP_MST) |
1541                  (1 << INTEL_OUTPUT_EDP));
1542 }
1543 static inline void
1544 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1545 {
1546         drm_wait_one_vblank(&dev_priv->drm, pipe);
1547 }
1548 static inline void
1549 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1550 {
1551         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1552
1553         if (crtc->active)
1554                 intel_wait_for_vblank(dev_priv, pipe);
1555 }
1556
1557 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1558
1559 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1560 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1561                          struct intel_digital_port *dport,
1562                          unsigned int expected_mask);
1563 int intel_get_load_detect_pipe(struct drm_connector *connector,
1564                                const struct drm_display_mode *mode,
1565                                struct intel_load_detect_pipe *old,
1566                                struct drm_modeset_acquire_ctx *ctx);
1567 void intel_release_load_detect_pipe(struct drm_connector *connector,
1568                                     struct intel_load_detect_pipe *old,
1569                                     struct drm_modeset_acquire_ctx *ctx);
1570 struct i915_vma *
1571 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1572                            unsigned int rotation,
1573                            bool uses_fence,
1574                            unsigned long *out_flags);
1575 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1576 struct drm_framebuffer *
1577 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1578                          struct drm_mode_fb_cmd2 *mode_cmd);
1579 int intel_prepare_plane_fb(struct drm_plane *plane,
1580                            struct drm_plane_state *new_state);
1581 void intel_cleanup_plane_fb(struct drm_plane *plane,
1582                             struct drm_plane_state *old_state);
1583 int intel_plane_atomic_get_property(struct drm_plane *plane,
1584                                     const struct drm_plane_state *state,
1585                                     struct drm_property *property,
1586                                     uint64_t *val);
1587 int intel_plane_atomic_set_property(struct drm_plane *plane,
1588                                     struct drm_plane_state *state,
1589                                     struct drm_property *property,
1590                                     uint64_t val);
1591 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1592                                     struct drm_crtc_state *crtc_state,
1593                                     const struct intel_plane_state *old_plane_state,
1594                                     struct drm_plane_state *plane_state);
1595
1596 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1597                                     enum pipe pipe);
1598
1599 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1600                      const struct dpll *dpll);
1601 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1602 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1603
1604 /* modesetting asserts */
1605 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1606                            enum pipe pipe);
1607 void assert_pll(struct drm_i915_private *dev_priv,
1608                 enum pipe pipe, bool state);
1609 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1610 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1611 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1612 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1613 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1614 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1615                        enum pipe pipe, bool state);
1616 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1617 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1618 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1619 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1620 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1621 u32 intel_compute_tile_offset(int *x, int *y,
1622                               const struct intel_plane_state *state, int plane);
1623 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1624 void intel_finish_reset(struct drm_i915_private *dev_priv);
1625 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1626 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1627 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1628 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1629 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1630 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1631 unsigned int skl_cdclk_get_vco(unsigned int freq);
1632 void intel_dp_get_m_n(struct intel_crtc *crtc,
1633                       struct intel_crtc_state *pipe_config);
1634 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1635 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1636 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1637                         struct dpll *best_clock);
1638 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1639
1640 bool intel_crtc_active(struct intel_crtc *crtc);
1641 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1642 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1643 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1644 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1645 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1646                                  struct intel_crtc_state *pipe_config);
1647 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1648                                   struct intel_crtc_state *crtc_state);
1649
1650 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1651 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1652 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1653                   uint32_t pixel_format);
1654
1655 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1656 {
1657         return i915_ggtt_offset(state->vma);
1658 }
1659
1660 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1661                         const struct intel_plane_state *plane_state);
1662 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1663                   const struct intel_plane_state *plane_state);
1664 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1665 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1666                      unsigned int rotation);
1667 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1668                             struct intel_plane_state *plane_state);
1669 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1670 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1671
1672 /* intel_csr.c */
1673 void intel_csr_ucode_init(struct drm_i915_private *);
1674 void intel_csr_load_program(struct drm_i915_private *);
1675 void intel_csr_ucode_fini(struct drm_i915_private *);
1676 void intel_csr_ucode_suspend(struct drm_i915_private *);
1677 void intel_csr_ucode_resume(struct drm_i915_private *);
1678
1679 /* intel_dp.c */
1680 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1681                            i915_reg_t dp_reg, enum port port,
1682                            enum pipe *pipe);
1683 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1684                    enum port port);
1685 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1686                              struct intel_connector *intel_connector);
1687 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1688                               int link_rate, uint8_t lane_count,
1689                               bool link_mst);
1690 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1691                                             int link_rate, uint8_t lane_count);
1692 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1693 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1694 int intel_dp_retrain_link(struct intel_encoder *encoder,
1695                           struct drm_modeset_acquire_ctx *ctx);
1696 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1697 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1698 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1699 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1700 bool intel_dp_compute_config(struct intel_encoder *encoder,
1701                              struct intel_crtc_state *pipe_config,
1702                              struct drm_connector_state *conn_state);
1703 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1704 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1705 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1706                                   bool long_hpd);
1707 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1708                             const struct drm_connector_state *conn_state);
1709 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1710 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1711 void intel_edp_panel_on(struct intel_dp *intel_dp);
1712 void intel_edp_panel_off(struct intel_dp *intel_dp);
1713 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1714 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1715 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1716 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1717 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1718 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1719 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1720 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1721 void intel_plane_destroy(struct drm_plane *plane);
1722 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1723                            const struct intel_crtc_state *crtc_state);
1724 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1725                             const struct intel_crtc_state *crtc_state);
1726 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1727                                unsigned int frontbuffer_bits);
1728 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1729                           unsigned int frontbuffer_bits);
1730
1731 void
1732 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1733                                        uint8_t dp_train_pat);
1734 void
1735 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1736 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1737 uint8_t
1738 intel_dp_voltage_max(struct intel_dp *intel_dp);
1739 uint8_t
1740 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1741 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1742                            uint8_t *link_bw, uint8_t *rate_select);
1743 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1744 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1745 bool
1746 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1747
1748 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1749 {
1750         return ~((1 << lane_count) - 1) & 0xf;
1751 }
1752
1753 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1754 int intel_dp_link_required(int pixel_clock, int bpp);
1755 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1756 bool intel_digital_port_connected(struct intel_encoder *encoder);
1757
1758 /* intel_dp_aux_backlight.c */
1759 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1760
1761 /* intel_dp_mst.c */
1762 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1763 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1764 /* vlv_dsi.c */
1765 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1766
1767 /* intel_dsi_dcs_backlight.c */
1768 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1769
1770 /* intel_dvo.c */
1771 void intel_dvo_init(struct drm_i915_private *dev_priv);
1772 /* intel_hotplug.c */
1773 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1774 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1775                            struct intel_connector *connector);
1776
1777 /* legacy fbdev emulation in intel_fbdev.c */
1778 #ifdef CONFIG_DRM_FBDEV_EMULATION
1779 extern int intel_fbdev_init(struct drm_device *dev);
1780 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1781 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1782 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1783 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1784 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1785 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1786 #else
1787 static inline int intel_fbdev_init(struct drm_device *dev)
1788 {
1789         return 0;
1790 }
1791
1792 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1793 {
1794 }
1795
1796 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1797 {
1798 }
1799
1800 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1801 {
1802 }
1803
1804 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1805 {
1806 }
1807
1808 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1809 {
1810 }
1811
1812 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1813 {
1814 }
1815 #endif
1816
1817 /* intel_fbc.c */
1818 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1819                            struct intel_atomic_state *state);
1820 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1821 void intel_fbc_pre_update(struct intel_crtc *crtc,
1822                           struct intel_crtc_state *crtc_state,
1823                           struct intel_plane_state *plane_state);
1824 void intel_fbc_post_update(struct intel_crtc *crtc);
1825 void intel_fbc_init(struct drm_i915_private *dev_priv);
1826 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1827 void intel_fbc_enable(struct intel_crtc *crtc,
1828                       struct intel_crtc_state *crtc_state,
1829                       struct intel_plane_state *plane_state);
1830 void intel_fbc_disable(struct intel_crtc *crtc);
1831 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1832 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1833                           unsigned int frontbuffer_bits,
1834                           enum fb_op_origin origin);
1835 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1836                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1837 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1838 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1839 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1840
1841 /* intel_hdmi.c */
1842 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1843                      enum port port);
1844 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1845                                struct intel_connector *intel_connector);
1846 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1847 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1848                                struct intel_crtc_state *pipe_config,
1849                                struct drm_connector_state *conn_state);
1850 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1851                                        struct drm_connector *connector,
1852                                        bool high_tmds_clock_ratio,
1853                                        bool scrambling);
1854 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1855 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1856
1857
1858 /* intel_lvds.c */
1859 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1860                              i915_reg_t lvds_reg, enum pipe *pipe);
1861 void intel_lvds_init(struct drm_i915_private *dev_priv);
1862 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1863 bool intel_is_dual_link_lvds(struct drm_device *dev);
1864
1865
1866 /* intel_modes.c */
1867 int intel_connector_update_modes(struct drm_connector *connector,
1868                                  struct edid *edid);
1869 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1870 void intel_attach_force_audio_property(struct drm_connector *connector);
1871 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1872 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1873
1874
1875 /* intel_overlay.c */
1876 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1877 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1878 int intel_overlay_switch_off(struct intel_overlay *overlay);
1879 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1880                                   struct drm_file *file_priv);
1881 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1882                               struct drm_file *file_priv);
1883 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1884
1885
1886 /* intel_panel.c */
1887 int intel_panel_init(struct intel_panel *panel,
1888                      struct drm_display_mode *fixed_mode,
1889                      struct drm_display_mode *downclock_mode);
1890 void intel_panel_fini(struct intel_panel *panel);
1891 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1892                             struct drm_display_mode *adjusted_mode);
1893 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1894                              struct intel_crtc_state *pipe_config,
1895                              int fitting_mode);
1896 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1897                               struct intel_crtc_state *pipe_config,
1898                               int fitting_mode);
1899 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1900                                     u32 level, u32 max);
1901 int intel_panel_setup_backlight(struct drm_connector *connector,
1902                                 enum pipe pipe);
1903 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1904                                   const struct drm_connector_state *conn_state);
1905 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1906 void intel_panel_destroy_backlight(struct drm_connector *connector);
1907 extern struct drm_display_mode *intel_find_panel_downclock(
1908                                 struct drm_i915_private *dev_priv,
1909                                 struct drm_display_mode *fixed_mode,
1910                                 struct drm_connector *connector);
1911
1912 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1913 int intel_backlight_device_register(struct intel_connector *connector);
1914 void intel_backlight_device_unregister(struct intel_connector *connector);
1915 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1916 static inline int intel_backlight_device_register(struct intel_connector *connector)
1917 {
1918         return 0;
1919 }
1920 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1921 {
1922 }
1923 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1924
1925 /* intel_hdcp.c */
1926 void intel_hdcp_atomic_check(struct drm_connector *connector,
1927                              struct drm_connector_state *old_state,
1928                              struct drm_connector_state *new_state);
1929 int intel_hdcp_init(struct intel_connector *connector,
1930                     const struct intel_hdcp_shim *hdcp_shim);
1931 int intel_hdcp_enable(struct intel_connector *connector);
1932 int intel_hdcp_disable(struct intel_connector *connector);
1933 int intel_hdcp_check_link(struct intel_connector *connector);
1934 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1935
1936 /* intel_psr.c */
1937 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1938 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1939 void intel_psr_enable(struct intel_dp *intel_dp,
1940                       const struct intel_crtc_state *crtc_state);
1941 void intel_psr_disable(struct intel_dp *intel_dp,
1942                       const struct intel_crtc_state *old_crtc_state);
1943 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1944                           unsigned frontbuffer_bits,
1945                           enum fb_op_origin origin);
1946 void intel_psr_flush(struct drm_i915_private *dev_priv,
1947                      unsigned frontbuffer_bits,
1948                      enum fb_op_origin origin);
1949 void intel_psr_init(struct drm_i915_private *dev_priv);
1950 void intel_psr_compute_config(struct intel_dp *intel_dp,
1951                               struct intel_crtc_state *crtc_state);
1952 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1953 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1954 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1955 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
1956
1957 /* intel_runtime_pm.c */
1958 int intel_power_domains_init(struct drm_i915_private *);
1959 void intel_power_domains_fini(struct drm_i915_private *);
1960 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1961 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1962 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1963 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1964 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1965 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1966 const char *
1967 intel_display_power_domain_str(enum intel_display_power_domain domain);
1968
1969 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1970                                     enum intel_display_power_domain domain);
1971 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1972                                       enum intel_display_power_domain domain);
1973 void intel_display_power_get(struct drm_i915_private *dev_priv,
1974                              enum intel_display_power_domain domain);
1975 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1976                                         enum intel_display_power_domain domain);
1977 void intel_display_power_put(struct drm_i915_private *dev_priv,
1978                              enum intel_display_power_domain domain);
1979 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1980                             u8 req_slices);
1981
1982 static inline void
1983 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1984 {
1985         WARN_ONCE(dev_priv->runtime_pm.suspended,
1986                   "Device suspended during HW access\n");
1987 }
1988
1989 static inline void
1990 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1991 {
1992         assert_rpm_device_not_suspended(dev_priv);
1993         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1994                   "RPM wakelock ref not held during HW access");
1995 }
1996
1997 /**
1998  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1999  * @dev_priv: i915 device instance
2000  *
2001  * This function disable asserts that check if we hold an RPM wakelock
2002  * reference, while keeping the device-not-suspended checks still enabled.
2003  * It's meant to be used only in special circumstances where our rule about
2004  * the wakelock refcount wrt. the device power state doesn't hold. According
2005  * to this rule at any point where we access the HW or want to keep the HW in
2006  * an active state we must hold an RPM wakelock reference acquired via one of
2007  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2008  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2009  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2010  * users should avoid using this function.
2011  *
2012  * Any calls to this function must have a symmetric call to
2013  * enable_rpm_wakeref_asserts().
2014  */
2015 static inline void
2016 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2017 {
2018         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2019 }
2020
2021 /**
2022  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2023  * @dev_priv: i915 device instance
2024  *
2025  * This function re-enables the RPM assert checks after disabling them with
2026  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2027  * circumstances otherwise its use should be avoided.
2028  *
2029  * Any calls to this function must have a symmetric call to
2030  * disable_rpm_wakeref_asserts().
2031  */
2032 static inline void
2033 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2034 {
2035         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2036 }
2037
2038 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2039 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2040 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2041 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2042
2043 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2044
2045 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2046                              bool override, unsigned int mask);
2047 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2048                           enum dpio_channel ch, bool override);
2049
2050
2051 /* intel_pm.c */
2052 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2053 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2054 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2055 void intel_update_watermarks(struct intel_crtc *crtc);
2056 void intel_init_pm(struct drm_i915_private *dev_priv);
2057 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2058 void intel_pm_setup(struct drm_i915_private *dev_priv);
2059 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2060 void intel_gpu_ips_teardown(void);
2061 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2062 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2063 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2064 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2065 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2066 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2067 bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915);
2068 void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915);
2069 void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915);
2070 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2071 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2072 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2073 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2074 void g4x_wm_get_hw_state(struct drm_device *dev);
2075 void vlv_wm_get_hw_state(struct drm_device *dev);
2076 void ilk_wm_get_hw_state(struct drm_device *dev);
2077 void skl_wm_get_hw_state(struct drm_device *dev);
2078 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2079                           struct skl_ddb_allocation *ddb /* out */);
2080 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2081                               struct skl_pipe_wm *out);
2082 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2083 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2084 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2085 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2086 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2087 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2088                          const struct skl_wm_level *l2);
2089 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2090                                  const struct skl_ddb_entry **entries,
2091                                  const struct skl_ddb_entry *ddb,
2092                                  int ignore);
2093 bool ilk_disable_lp_wm(struct drm_device *dev);
2094 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2095                                   struct intel_crtc_state *cstate);
2096 void intel_init_ipc(struct drm_i915_private *dev_priv);
2097 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2098
2099 /* intel_sdvo.c */
2100 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2101                              i915_reg_t sdvo_reg, enum pipe *pipe);
2102 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2103                      i915_reg_t reg, enum port port);
2104
2105
2106 /* intel_sprite.c */
2107 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2108                              int usecs);
2109 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2110                                               enum pipe pipe, int plane);
2111 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2112                                     struct drm_file *file_priv);
2113 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2114 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2115 void skl_update_plane(struct intel_plane *plane,
2116                       const struct intel_crtc_state *crtc_state,
2117                       const struct intel_plane_state *plane_state);
2118 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2119 bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2120 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2121                        enum pipe pipe, enum plane_id plane_id);
2122 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2123                           enum pipe pipe, enum plane_id plane_id);
2124
2125 /* intel_tv.c */
2126 void intel_tv_init(struct drm_i915_private *dev_priv);
2127
2128 /* intel_atomic.c */
2129 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2130                                                 const struct drm_connector_state *state,
2131                                                 struct drm_property *property,
2132                                                 uint64_t *val);
2133 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2134                                                 struct drm_connector_state *state,
2135                                                 struct drm_property *property,
2136                                                 uint64_t val);
2137 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2138                                          struct drm_connector_state *new_state);
2139 struct drm_connector_state *
2140 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2141
2142 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2143 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2144                                struct drm_crtc_state *state);
2145 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2146 void intel_atomic_state_clear(struct drm_atomic_state *);
2147
2148 static inline struct intel_crtc_state *
2149 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2150                             struct intel_crtc *crtc)
2151 {
2152         struct drm_crtc_state *crtc_state;
2153         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2154         if (IS_ERR(crtc_state))
2155                 return ERR_CAST(crtc_state);
2156
2157         return to_intel_crtc_state(crtc_state);
2158 }
2159
2160 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2161                                struct intel_crtc *intel_crtc,
2162                                struct intel_crtc_state *crtc_state);
2163
2164 /* intel_atomic_plane.c */
2165 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2166 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2167 void intel_plane_destroy_state(struct drm_plane *plane,
2168                                struct drm_plane_state *state);
2169 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2170 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2171                                         struct intel_crtc_state *crtc_state,
2172                                         const struct intel_plane_state *old_plane_state,
2173                                         struct intel_plane_state *intel_state);
2174
2175 /* intel_color.c */
2176 void intel_color_init(struct drm_crtc *crtc);
2177 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2178 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2179 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2180
2181 /* intel_lspcon.c */
2182 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2183 void lspcon_resume(struct intel_lspcon *lspcon);
2184 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2185
2186 /* intel_pipe_crc.c */
2187 #ifdef CONFIG_DEBUG_FS
2188 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2189                               size_t *values_cnt);
2190 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2191 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2192 #else
2193 #define intel_crtc_set_crc_source NULL
2194 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2195 {
2196 }
2197
2198 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2199 {
2200 }
2201 #endif
2202 #endif /* __INTEL_DRV_H__ */