drivers/gpu/drm/i915/intel_huc_fw.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2018 Intel Corporation
   5  */
   6
   7 #include "intel_huc_fw.h"
   8 #include "i915_drv.h"
   9
  10 /**
  11  * DOC: HuC Firmware
  12  *
  13  * Motivation:
  14  * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
  15  * Efficiency Video Coding) operations. Userspace can use the firmware
  16  * capabilities by adding HuC specific commands to batch buffers.
  17  *
  18  * Implementation:
  19  * The same firmware loader is used as the GuC. However, the actual
  20  * loading to HW is deferred until GEM initialization is done.
  21  *
  22  * Note that HuC firmware loading must be done before GuC loading.
  23  */
  24
  25 #define BXT_HUC_FW_MAJOR 01
  26 #define BXT_HUC_FW_MINOR 07
  27 #define BXT_BLD_NUM 1398
  28
  29 #define SKL_HUC_FW_MAJOR 01
  30 #define SKL_HUC_FW_MINOR 07
  31 #define SKL_BLD_NUM 1398
  32
  33 #define KBL_HUC_FW_MAJOR 02
  34 #define KBL_HUC_FW_MINOR 00
  35 #define KBL_BLD_NUM 1810
  36
  37 #define HUC_FW_PATH(platform, major, minor, bld_num) \
  38         "/*(DEBLOBBED)*/"
  39
  40 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
  41         SKL_HUC_FW_MINOR, SKL_BLD_NUM)
  42 /*(DEBLOBBED)*/
  43
  44 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
  45         BXT_HUC_FW_MINOR, BXT_BLD_NUM)
  46 /*(DEBLOBBED)*/
  47
  48 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
  49         KBL_HUC_FW_MINOR, KBL_BLD_NUM)
  50 /*(DEBLOBBED)*/
  51
  52 static void huc_fw_select(struct intel_uc_fw *huc_fw)
  53 {
  54         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
  55         struct drm_i915_private *dev_priv = huc_to_i915(huc);
  56
  57         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
  58
  59         if (!HAS_HUC(dev_priv))
  60                 return;
  61
  62         if (i915_modparams.huc_firmware_path) {
  63                 huc_fw->path = i915_modparams.huc_firmware_path;
  64                 huc_fw->major_ver_wanted = 0;
  65                 huc_fw->minor_ver_wanted = 0;
  66         } else if (IS_SKYLAKE(dev_priv)) {
  67                 huc_fw->path = I915_SKL_HUC_UCODE;
  68                 huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
  69                 huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
  70         } else if (IS_BROXTON(dev_priv)) {
  71                 huc_fw->path = I915_BXT_HUC_UCODE;
  72                 huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
  73                 huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
  74         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
  75                 huc_fw->path = I915_KBL_HUC_UCODE;
  76                 huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
  77                 huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
  78         } else {
  79                 DRM_WARN("%s: No firmware known for this platform!\n",
  80                          intel_uc_fw_type_repr(huc_fw->type));
  81         }
  82 }
  83
  84 /**
  85  * intel_huc_fw_init_early() - initializes HuC firmware struct
  86  * @huc: intel_huc struct
  87  *
  88  * On platforms with HuC selects firmware for uploading
  89  */
  90 void intel_huc_fw_init_early(struct intel_huc *huc)
  91 {
  92         struct intel_uc_fw *huc_fw = &huc->fw;
  93
  94         intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC);
  95         huc_fw_select(huc_fw);
  96 }
  97
  98 /**
  99  * huc_fw_xfer() - DMA's the firmware
 100  * @huc_fw: the firmware descriptor
 101  * @vma: the firmware image (bound into the GGTT)
 102  *
 103  * Transfer the firmware image to RAM for execution by the microcontroller.
 104  *
 105  * Return: 0 on success, non-zero on failure
 106  */
 107 static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 108 {
 109         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
 110         struct drm_i915_private *dev_priv = huc_to_i915(huc);
 111         unsigned long offset = 0;
 112         u32 size;
 113         int ret;
 114
 115         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 116
 117         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 118
 119         /* Set the source address for the uCode */
 120         offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
 121                  huc_fw->header_offset;
 122         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 123         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 124
 125         /* Hardware doesn't look at destination address for HuC. Set it to 0,
 126          * but still program the correct address space.
 127          */
 128         I915_WRITE(DMA_ADDR_1_LOW, 0);
 129         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 130
 131         size = huc_fw->header_size + huc_fw->ucode_size;
 132         I915_WRITE(DMA_COPY_SIZE, size);
 133
 134         /* Start the DMA */
 135         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 136
 137         /* Wait for DMA to finish */
 138         ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
 139
 140         DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 141
 142         /* Disable the bits once DMA is over */
 143         I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
 144
 145         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 146
 147         return ret;
 148 }
 149
 150 /**
 151  * intel_huc_fw_upload() - load HuC uCode to device
 152  * @huc: intel_huc structure
 153  *
 154  * Called from intel_uc_init_hw() during driver load, resume from sleep and
 155  * after a GPU reset. Note that HuC must be loaded before GuC.
 156  *
 157  * The firmware image should have already been fetched into memory, so only
 158  * check that fetch succeeded, and then transfer the image to the h/w.
 159  *
 160  * Return:      non-zero code on error
 161  */
 162 int intel_huc_fw_upload(struct intel_huc *huc)
 163 {
 164         return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);
 165 }