2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
42 /* Map gmbus pin pairs to names and registers. */
43 static const struct gmbus_pin gmbus_pins[] = {
44 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
46 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
47 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
48 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
49 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
52 static const struct gmbus_pin gmbus_pins_bdw[] = {
53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
54 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
55 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
56 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
59 static const struct gmbus_pin gmbus_pins_skl[] = {
60 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
61 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
62 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
65 static const struct gmbus_pin gmbus_pins_bxt[] = {
66 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
67 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
68 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
71 /* pin is expected to be valid */
72 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
75 if (IS_BROXTON(dev_priv))
76 return &gmbus_pins_bxt[pin];
77 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
78 return &gmbus_pins_skl[pin];
79 else if (IS_BROADWELL(dev_priv))
80 return &gmbus_pins_bdw[pin];
82 return &gmbus_pins[pin];
85 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
90 if (IS_BROXTON(dev_priv))
91 size = ARRAY_SIZE(gmbus_pins_bxt);
92 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
93 size = ARRAY_SIZE(gmbus_pins_skl);
94 else if (IS_BROADWELL(dev_priv))
95 size = ARRAY_SIZE(gmbus_pins_bdw);
97 size = ARRAY_SIZE(gmbus_pins);
100 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
103 /* Intel GPIO access functions */
105 #define I2C_RISEFALL_TIME 10
107 static inline struct intel_gmbus *
108 to_intel_gmbus(struct i2c_adapter *i2c)
110 return container_of(i2c, struct intel_gmbus, adapter);
114 intel_i2c_reset(struct drm_device *dev)
116 struct drm_i915_private *dev_priv = to_i915(dev);
118 I915_WRITE(GMBUS0, 0);
119 I915_WRITE(GMBUS4, 0);
122 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
126 /* When using bit bashing for I2C, this bit needs to be set to 1 */
127 if (!IS_PINEVIEW(dev_priv))
130 val = I915_READ(DSPCLK_GATE_D);
132 val |= DPCUNIT_CLOCK_GATE_DISABLE;
134 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
135 I915_WRITE(DSPCLK_GATE_D, val);
138 static u32 get_reserved(struct intel_gmbus *bus)
140 struct drm_i915_private *dev_priv = bus->dev_priv;
141 struct drm_device *dev = &dev_priv->drm;
144 /* On most chips, these bits must be preserved in software. */
145 if (!IS_I830(dev) && !IS_845G(dev))
146 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
147 (GPIO_DATA_PULLUP_DISABLE |
148 GPIO_CLOCK_PULLUP_DISABLE);
153 static int get_clock(void *data)
155 struct intel_gmbus *bus = data;
156 struct drm_i915_private *dev_priv = bus->dev_priv;
157 u32 reserved = get_reserved(bus);
158 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
159 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
160 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
163 static int get_data(void *data)
165 struct intel_gmbus *bus = data;
166 struct drm_i915_private *dev_priv = bus->dev_priv;
167 u32 reserved = get_reserved(bus);
168 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
169 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
170 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
173 static void set_clock(void *data, int state_high)
175 struct intel_gmbus *bus = data;
176 struct drm_i915_private *dev_priv = bus->dev_priv;
177 u32 reserved = get_reserved(bus);
181 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
183 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
186 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
187 POSTING_READ(bus->gpio_reg);
190 static void set_data(void *data, int state_high)
192 struct intel_gmbus *bus = data;
193 struct drm_i915_private *dev_priv = bus->dev_priv;
194 u32 reserved = get_reserved(bus);
198 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
200 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
203 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
204 POSTING_READ(bus->gpio_reg);
208 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
210 struct intel_gmbus *bus = container_of(adapter,
213 struct drm_i915_private *dev_priv = bus->dev_priv;
215 intel_i2c_reset(&dev_priv->drm);
216 intel_i2c_quirk_set(dev_priv, true);
219 udelay(I2C_RISEFALL_TIME);
224 intel_gpio_post_xfer(struct i2c_adapter *adapter)
226 struct intel_gmbus *bus = container_of(adapter,
229 struct drm_i915_private *dev_priv = bus->dev_priv;
233 intel_i2c_quirk_set(dev_priv, false);
237 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
239 struct drm_i915_private *dev_priv = bus->dev_priv;
240 struct i2c_algo_bit_data *algo;
242 algo = &bus->bit_algo;
244 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
245 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
246 bus->adapter.algo_data = algo;
247 algo->setsda = set_data;
248 algo->setscl = set_clock;
249 algo->getsda = get_data;
250 algo->getscl = get_clock;
251 algo->pre_xfer = intel_gpio_pre_xfer;
252 algo->post_xfer = intel_gpio_post_xfer;
253 algo->udelay = I2C_RISEFALL_TIME;
254 algo->timeout = usecs_to_jiffies(2200);
258 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
264 /* Important: The hw handles only the first bit, so set only one! Since
265 * we also need to check for NAKs besides the hw ready/idle signal, we
266 * need to wake up periodically and check that ourselves.
268 if (!HAS_GMBUS_IRQ(dev_priv))
271 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
272 I915_WRITE_FW(GMBUS4, irq_en);
274 status |= GMBUS_SATOER;
275 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
277 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
279 I915_WRITE_FW(GMBUS4, 0);
280 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
282 if (gmbus2 & GMBUS_SATOER)
289 gmbus_wait_idle(struct drm_i915_private *dev_priv)
295 /* Important: The hw handles only the first bit, so set only one! */
297 if (HAS_GMBUS_IRQ(dev_priv))
298 irq_enable = GMBUS_IDLE_EN;
300 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
301 I915_WRITE_FW(GMBUS4, irq_enable);
303 ret = intel_wait_for_register_fw(dev_priv,
304 GMBUS2, GMBUS_ACTIVE, 0,
307 I915_WRITE_FW(GMBUS4, 0);
308 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
314 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
315 unsigned short addr, u8 *buf, unsigned int len,
318 I915_WRITE_FW(GMBUS1,
321 (len << GMBUS_BYTE_COUNT_SHIFT) |
322 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
323 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
328 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
332 val = I915_READ_FW(GMBUS3);
336 } while (--len && ++loop < 4);
343 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
347 unsigned int rx_size = msg->len;
352 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
354 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
355 buf, len, gmbus1_index);
361 } while (rx_size != 0);
367 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
368 unsigned short addr, u8 *buf, unsigned int len)
370 unsigned int chunk_size = len;
374 while (len && loop < 4) {
375 val |= *buf++ << (8 * loop++);
379 I915_WRITE_FW(GMBUS3, val);
380 I915_WRITE_FW(GMBUS1,
382 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
383 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
384 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
390 val |= *buf++ << (8 * loop);
391 } while (--len && ++loop < 4);
393 I915_WRITE_FW(GMBUS3, val);
395 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
404 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
407 unsigned int tx_size = msg->len;
412 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
414 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
420 } while (tx_size != 0);
426 * The gmbus controller can combine a 1 or 2 byte write with a read that
427 * immediately follows it by using an "INDEX" cycle.
430 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
432 return (i + 1 < num &&
433 msgs[i].addr == msgs[i + 1].addr &&
434 !(msgs[i].flags & I2C_M_RD) &&
435 (msgs[i].len == 1 || msgs[i].len == 2) &&
436 (msgs[i + 1].flags & I2C_M_RD));
440 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
442 u32 gmbus1_index = 0;
446 if (msgs[0].len == 2)
447 gmbus5 = GMBUS_2BYTE_INDEX_EN |
448 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
449 if (msgs[0].len == 1)
450 gmbus1_index = GMBUS_CYCLE_INDEX |
451 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
453 /* GMBUS5 holds 16-bit index */
455 I915_WRITE_FW(GMBUS5, gmbus5);
457 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
459 /* Clear GMBUS5 after each index transfer */
461 I915_WRITE_FW(GMBUS5, 0);
467 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
469 struct intel_gmbus *bus = container_of(adapter,
472 struct drm_i915_private *dev_priv = bus->dev_priv;
473 const unsigned int fw =
474 intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
475 FW_REG_READ | FW_REG_WRITE);
476 int i = 0, inc, try = 0;
479 intel_uncore_forcewake_get(dev_priv, fw);
481 I915_WRITE_FW(GMBUS0, bus->reg0);
483 for (; i < num; i += inc) {
485 if (gmbus_is_index_read(msgs, i, num)) {
486 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
487 inc = 2; /* an index read is two msgs */
488 } else if (msgs[i].flags & I2C_M_RD) {
489 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
491 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
495 ret = gmbus_wait(dev_priv,
496 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
497 if (ret == -ETIMEDOUT)
503 /* Generate a STOP condition on the bus. Note that gmbus can't generata
504 * a STOP on the very first cycle. To simplify the code we
505 * unconditionally generate the STOP condition with an additional gmbus
507 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
509 /* Mark the GMBUS interface as disabled after waiting for idle.
510 * We will re-enable it at the start of the next xfer,
511 * till then let it sleep.
513 if (gmbus_wait_idle(dev_priv)) {
514 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
518 I915_WRITE_FW(GMBUS0, 0);
524 * Wait for bus to IDLE before clearing NAK.
525 * If we clear the NAK while bus is still active, then it will stay
526 * active and the next transaction may fail.
528 * If no ACK is received during the address phase of a transaction, the
529 * adapter must report -ENXIO. It is not clear what to return if no ACK
530 * is received at other times. But we have to be careful to not return
531 * spurious -ENXIO because that will prevent i2c and drm edid functions
532 * from retrying. So return -ENXIO only when gmbus properly quiescents -
533 * timing out seems to happen when there _is_ a ddc chip present, but
534 * it's slow responding and only answers on the 2nd retry.
537 if (gmbus_wait_idle(dev_priv)) {
538 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
543 /* Toggle the Software Clear Interrupt bit. This has the effect
544 * of resetting the GMBUS controller and so clearing the
545 * BUS_ERROR raised by the slave's NAK.
547 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
548 I915_WRITE_FW(GMBUS1, 0);
549 I915_WRITE_FW(GMBUS0, 0);
551 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
552 adapter->name, msgs[i].addr,
553 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
556 * Passive adapters sometimes NAK the first probe. Retry the first
557 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
558 * has retries internally. See also the retry loop in
559 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
561 if (ret == -ENXIO && i == 0 && try++ == 0) {
562 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
570 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
571 bus->adapter.name, bus->reg0 & 0xff);
572 I915_WRITE_FW(GMBUS0, 0);
575 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
576 * instead. Use EAGAIN to have i2c core retry.
581 intel_uncore_forcewake_put(dev_priv, fw);
586 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
588 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
590 struct drm_i915_private *dev_priv = bus->dev_priv;
593 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
594 mutex_lock(&dev_priv->gmbus_mutex);
596 if (bus->force_bit) {
597 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
599 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
601 ret = do_gmbus_xfer(adapter, msgs, num);
603 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
606 mutex_unlock(&dev_priv->gmbus_mutex);
607 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
612 static u32 gmbus_func(struct i2c_adapter *adapter)
614 return i2c_bit_algo.functionality(adapter) &
615 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
616 /* I2C_FUNC_10BIT_ADDR | */
617 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
618 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
621 static const struct i2c_algorithm gmbus_algorithm = {
622 .master_xfer = gmbus_xfer,
623 .functionality = gmbus_func
627 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
630 int intel_setup_gmbus(struct drm_device *dev)
632 struct drm_i915_private *dev_priv = to_i915(dev);
633 struct pci_dev *pdev = dev_priv->drm.pdev;
634 struct intel_gmbus *bus;
638 if (HAS_PCH_NOP(dev))
641 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
642 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
643 else if (!HAS_GMCH_DISPLAY(dev_priv))
644 dev_priv->gpio_mmio_base =
645 i915_mmio_reg_offset(PCH_GPIOA) -
646 i915_mmio_reg_offset(GPIOA);
648 mutex_init(&dev_priv->gmbus_mutex);
649 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
651 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
652 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
655 bus = &dev_priv->gmbus[pin];
657 bus->adapter.owner = THIS_MODULE;
658 bus->adapter.class = I2C_CLASS_DDC;
659 snprintf(bus->adapter.name,
660 sizeof(bus->adapter.name),
662 get_gmbus_pin(dev_priv, pin)->name);
664 bus->adapter.dev.parent = &pdev->dev;
665 bus->dev_priv = dev_priv;
667 bus->adapter.algo = &gmbus_algorithm;
670 * We wish to retry with bit banging
671 * after a timed out GMBUS attempt.
673 bus->adapter.retries = 1;
675 /* By default use a conservative clock rate */
676 bus->reg0 = pin | GMBUS_RATE_100KHZ;
678 /* gmbus seems to be broken on i830 */
682 intel_gpio_setup(bus, pin);
684 ret = i2c_add_adapter(&bus->adapter);
689 intel_i2c_reset(&dev_priv->drm);
695 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
698 bus = &dev_priv->gmbus[pin];
699 i2c_del_adapter(&bus->adapter);
704 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
707 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
710 return &dev_priv->gmbus[pin].adapter;
713 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
715 struct intel_gmbus *bus = to_intel_gmbus(adapter);
717 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
720 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
722 struct intel_gmbus *bus = to_intel_gmbus(adapter);
723 struct drm_i915_private *dev_priv = bus->dev_priv;
725 mutex_lock(&dev_priv->gmbus_mutex);
727 bus->force_bit += force_bit ? 1 : -1;
728 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
729 force_bit ? "en" : "dis", adapter->name,
732 mutex_unlock(&dev_priv->gmbus_mutex);
735 void intel_teardown_gmbus(struct drm_device *dev)
737 struct drm_i915_private *dev_priv = to_i915(dev);
738 struct intel_gmbus *bus;
741 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
742 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
745 bus = &dev_priv->gmbus[pin];
746 i2c_del_adapter(&bus->adapter);