drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47
  48         struct notifier_block lid_notifier;
  49 };
  50
  51 struct intel_lvds_pps {
  52         /* 100us units */
  53         int t1_t2;
  54         int t3;
  55         int t4;
  56         int t5;
  57         int tx;
  58
  59         int divider;
  60
  61         int port;
  62         bool powerdown_on_reset;
  63 };
  64
  65 struct intel_lvds_encoder {
  66         struct intel_encoder base;
  67
  68         bool is_dual_link;
  69         i915_reg_t reg;
  70         u32 a3_power;
  71
  72         struct intel_lvds_pps init_pps;
  73         u32 init_lvds_val;
  74
  75         struct intel_lvds_connector *attached_connector;
  76 };
  77
  78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  79 {
  80         return container_of(encoder, struct intel_lvds_encoder, base.base);
  81 }
  82
  83 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  84 {
  85         return container_of(connector, struct intel_lvds_connector, base.base);
  86 }
  87
  88 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  89                                     enum pipe *pipe)
  90 {
  91         struct drm_device *dev = encoder->base.dev;
  92         struct drm_i915_private *dev_priv = to_i915(dev);
  93         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  94         enum intel_display_power_domain power_domain;
  95         u32 tmp;
  96         bool ret;
  97
  98         power_domain = intel_display_port_power_domain(encoder);
  99         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 100                 return false;
 101
 102         ret = false;
 103
 104         tmp = I915_READ(lvds_encoder->reg);
 105
 106         if (!(tmp & LVDS_PORT_EN))
 107                 goto out;
 108
 109         if (HAS_PCH_CPT(dev))
 110                 *pipe = PORT_TO_PIPE_CPT(tmp);
 111         else
 112                 *pipe = PORT_TO_PIPE(tmp);
 113
 114         ret = true;
 115
 116 out:
 117         intel_display_power_put(dev_priv, power_domain);
 118
 119         return ret;
 120 }
 121
 122 static void intel_lvds_get_config(struct intel_encoder *encoder,
 123                                   struct intel_crtc_state *pipe_config)
 124 {
 125         struct drm_device *dev = encoder->base.dev;
 126         struct drm_i915_private *dev_priv = to_i915(dev);
 127         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 128         u32 tmp, flags = 0;
 129
 130         tmp = I915_READ(lvds_encoder->reg);
 131         if (tmp & LVDS_HSYNC_POLARITY)
 132                 flags |= DRM_MODE_FLAG_NHSYNC;
 133         else
 134                 flags |= DRM_MODE_FLAG_PHSYNC;
 135         if (tmp & LVDS_VSYNC_POLARITY)
 136                 flags |= DRM_MODE_FLAG_NVSYNC;
 137         else
 138                 flags |= DRM_MODE_FLAG_PVSYNC;
 139
 140         pipe_config->base.adjusted_mode.flags |= flags;
 141
 142         if (INTEL_INFO(dev)->gen < 5)
 143                 pipe_config->gmch_pfit.lvds_border_bits =
 144                         tmp & LVDS_BORDER_ENABLE;
 145
 146         /* gen2/3 store dither state in pfit control, needs to match */
 147         if (INTEL_INFO(dev)->gen < 4) {
 148                 tmp = I915_READ(PFIT_CONTROL);
 149
 150                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 151         }
 152
 153         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 154 }
 155
 156 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 157                                         struct intel_lvds_pps *pps)
 158 {
 159         u32 val;
 160
 161         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 162
 163         val = I915_READ(PP_ON_DELAYS(0));
 164         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 165                     PANEL_PORT_SELECT_SHIFT;
 166         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 167                      PANEL_POWER_UP_DELAY_SHIFT;
 168         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 169                   PANEL_LIGHT_ON_DELAY_SHIFT;
 170
 171         val = I915_READ(PP_OFF_DELAYS(0));
 172         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 173                   PANEL_POWER_DOWN_DELAY_SHIFT;
 174         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 175                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 176
 177         val = I915_READ(PP_DIVISOR(0));
 178         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 179                        PP_REFERENCE_DIVIDER_SHIFT;
 180         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 181               PANEL_POWER_CYCLE_DELAY_SHIFT;
 182         /*
 183          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 184          * too short power-cycle delay due to the asynchronous programming of
 185          * the register.
 186          */
 187         if (val)
 188                 val--;
 189         /* Convert from 100ms to 100us units */
 190         pps->t4 = val * 1000;
 191
 192         if (INTEL_INFO(dev_priv)->gen <= 4 &&
 193             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 194                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 195                               "setting defaults\n");
 196                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 197                 pps->t1_t2 = 40 * 10;
 198                 pps->t5 = 200 * 10;
 199                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 200                 pps->t3 = 35 * 10;
 201                 pps->tx = 200 * 10;
 202         }
 203
 204         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 205                          "divider %d port %d powerdown_on_reset %d\n",
 206                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 207                          pps->divider, pps->port, pps->powerdown_on_reset);
 208 }
 209
 210 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 211                                    struct intel_lvds_pps *pps)
 212 {
 213         u32 val;
 214
 215         val = I915_READ(PP_CONTROL(0));
 216         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 217         if (pps->powerdown_on_reset)
 218                 val |= PANEL_POWER_RESET;
 219         I915_WRITE(PP_CONTROL(0), val);
 220
 221         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 222                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 223                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 224         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 225                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 226
 227         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 228         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 229                PANEL_POWER_CYCLE_DELAY_SHIFT;
 230         I915_WRITE(PP_DIVISOR(0), val);
 231 }
 232
 233 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 234                                   struct intel_crtc_state *pipe_config,
 235                                   struct drm_connector_state *conn_state)
 236 {
 237         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 239         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 240         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 241         int pipe = crtc->pipe;
 242         u32 temp;
 243
 244         if (HAS_PCH_SPLIT(dev_priv)) {
 245                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 246                 assert_shared_dpll_disabled(dev_priv,
 247                                             pipe_config->shared_dpll);
 248         } else {
 249                 assert_pll_disabled(dev_priv, pipe);
 250         }
 251
 252         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 253
 254         temp = lvds_encoder->init_lvds_val;
 255         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 256
 257         if (HAS_PCH_CPT(dev_priv)) {
 258                 temp &= ~PORT_TRANS_SEL_MASK;
 259                 temp |= PORT_TRANS_SEL_CPT(pipe);
 260         } else {
 261                 if (pipe == 1) {
 262                         temp |= LVDS_PIPEB_SELECT;
 263                 } else {
 264                         temp &= ~LVDS_PIPEB_SELECT;
 265                 }
 266         }
 267
 268         /* set the corresponsding LVDS_BORDER bit */
 269         temp &= ~LVDS_BORDER_ENABLE;
 270         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 271         /* Set the B0-B3 data pairs corresponding to whether we're going to
 272          * set the DPLLs for dual-channel mode or not.
 273          */
 274         if (lvds_encoder->is_dual_link)
 275                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 276         else
 277                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 278
 279         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 280          * appropriately here, but we need to look more thoroughly into how
 281          * panels behave in the two modes. For now, let's just maintain the
 282          * value we got from the BIOS.
 283          */
 284         temp &= ~LVDS_A3_POWER_MASK;
 285         temp |= lvds_encoder->a3_power;
 286
 287         /* Set the dithering flag on LVDS as needed, note that there is no
 288          * special lvds dither control bit on pch-split platforms, dithering is
 289          * only controlled through the PIPECONF reg. */
 290         if (IS_GEN4(dev_priv)) {
 291                 /* Bspec wording suggests that LVDS port dithering only exists
 292                  * for 18bpp panels. */
 293                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 294                         temp |= LVDS_ENABLE_DITHER;
 295                 else
 296                         temp &= ~LVDS_ENABLE_DITHER;
 297         }
 298         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 299         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 300                 temp |= LVDS_HSYNC_POLARITY;
 301         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 302                 temp |= LVDS_VSYNC_POLARITY;
 303
 304         I915_WRITE(lvds_encoder->reg, temp);
 305 }
 306
 307 /**
 308  * Sets the power state for the panel.
 309  */
 310 static void intel_enable_lvds(struct intel_encoder *encoder,
 311                               struct intel_crtc_state *pipe_config,
 312                               struct drm_connector_state *conn_state)
 313 {
 314         struct drm_device *dev = encoder->base.dev;
 315         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 316         struct intel_connector *intel_connector =
 317                 &lvds_encoder->attached_connector->base;
 318         struct drm_i915_private *dev_priv = to_i915(dev);
 319
 320         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 321
 322         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 323         POSTING_READ(lvds_encoder->reg);
 324
 325         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
 326                 DRM_ERROR("timed out waiting for panel to power on\n");
 327
 328         intel_panel_enable_backlight(intel_connector);
 329 }
 330
 331 static void intel_disable_lvds(struct intel_encoder *encoder,
 332                                struct intel_crtc_state *old_crtc_state,
 333                                struct drm_connector_state *old_conn_state)
 334 {
 335         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 336         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 337
 338         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 339         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 340                 DRM_ERROR("timed out waiting for panel to power off\n");
 341
 342         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 343         POSTING_READ(lvds_encoder->reg);
 344 }
 345
 346 static void gmch_disable_lvds(struct intel_encoder *encoder,
 347                               struct intel_crtc_state *old_crtc_state,
 348                               struct drm_connector_state *old_conn_state)
 349
 350 {
 351         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 352         struct intel_connector *intel_connector =
 353                 &lvds_encoder->attached_connector->base;
 354
 355         intel_panel_disable_backlight(intel_connector);
 356
 357         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 358 }
 359
 360 static void pch_disable_lvds(struct intel_encoder *encoder,
 361                              struct intel_crtc_state *old_crtc_state,
 362                              struct drm_connector_state *old_conn_state)
 363 {
 364         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 365         struct intel_connector *intel_connector =
 366                 &lvds_encoder->attached_connector->base;
 367
 368         intel_panel_disable_backlight(intel_connector);
 369 }
 370
 371 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 372                                   struct intel_crtc_state *old_crtc_state,
 373                                   struct drm_connector_state *old_conn_state)
 374 {
 375         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 376 }
 377
 378 static enum drm_mode_status
 379 intel_lvds_mode_valid(struct drm_connector *connector,
 380                       struct drm_display_mode *mode)
 381 {
 382         struct intel_connector *intel_connector = to_intel_connector(connector);
 383         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 384         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 385
 386         if (mode->hdisplay > fixed_mode->hdisplay)
 387                 return MODE_PANEL;
 388         if (mode->vdisplay > fixed_mode->vdisplay)
 389                 return MODE_PANEL;
 390         if (fixed_mode->clock > max_pixclk)
 391                 return MODE_CLOCK_HIGH;
 392
 393         return MODE_OK;
 394 }
 395
 396 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 397                                       struct intel_crtc_state *pipe_config,
 398                                       struct drm_connector_state *conn_state)
 399 {
 400         struct drm_device *dev = intel_encoder->base.dev;
 401         struct intel_lvds_encoder *lvds_encoder =
 402                 to_lvds_encoder(&intel_encoder->base);
 403         struct intel_connector *intel_connector =
 404                 &lvds_encoder->attached_connector->base;
 405         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 406         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 407         unsigned int lvds_bpp;
 408
 409         /* Should never happen!! */
 410         if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
 411                 DRM_ERROR("Can't support LVDS on pipe A\n");
 412                 return false;
 413         }
 414
 415         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 416                 lvds_bpp = 8*3;
 417         else
 418                 lvds_bpp = 6*3;
 419
 420         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 421                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 422                               pipe_config->pipe_bpp, lvds_bpp);
 423                 pipe_config->pipe_bpp = lvds_bpp;
 424         }
 425
 426         /*
 427          * We have timings from the BIOS for the panel, put them in
 428          * to the adjusted mode.  The CRTC will be set up for this mode,
 429          * with the panel scaling set up to source from the H/VDisplay
 430          * of the original mode.
 431          */
 432         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 433                                adjusted_mode);
 434
 435         if (HAS_PCH_SPLIT(dev)) {
 436                 pipe_config->has_pch_encoder = true;
 437
 438                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 439                                         intel_connector->panel.fitting_mode);
 440         } else {
 441                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 442                                          intel_connector->panel.fitting_mode);
 443
 444         }
 445
 446         /*
 447          * XXX: It would be nice to support lower refresh rates on the
 448          * panels to reduce power consumption, and perhaps match the
 449          * user's requested refresh rate.
 450          */
 451
 452         return true;
 453 }
 454
 455 /**
 456  * Detect the LVDS connection.
 457  *
 458  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
 459  * connected and closed means disconnected.  We also send hotplug events as
 460  * needed, using lid status notification from the input layer.
 461  */
 462 static enum drm_connector_status
 463 intel_lvds_detect(struct drm_connector *connector, bool force)
 464 {
 465         struct drm_device *dev = connector->dev;
 466         enum drm_connector_status status;
 467
 468         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 469                       connector->base.id, connector->name);
 470
 471         status = intel_panel_detect(dev);
 472         if (status != connector_status_unknown)
 473                 return status;
 474
 475         return connector_status_connected;
 476 }
 477
 478 /**
 479  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 480  */
 481 static int intel_lvds_get_modes(struct drm_connector *connector)
 482 {
 483         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 484         struct drm_device *dev = connector->dev;
 485         struct drm_display_mode *mode;
 486
 487         /* use cached edid if we have one */
 488         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 489                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 490
 491         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 492         if (mode == NULL)
 493                 return 0;
 494
 495         drm_mode_probed_add(connector, mode);
 496         return 1;
 497 }
 498
 499 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
 500 {
 501         DRM_INFO("Skipping forced modeset for %s\n", id->ident);
 502         return 1;
 503 }
 504
 505 /* The GPU hangs up on these systems if modeset is performed on LID open */
 506 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
 507         {
 508                 .callback = intel_no_modeset_on_lid_dmi_callback,
 509                 .ident = "Toshiba Tecra A11",
 510                 .matches = {
 511                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 512                         DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
 513                 },
 514         },
 515
 516         { }     /* terminating entry */
 517 };
 518
 519 /*
 520  * Lid events. Note the use of 'modeset':
 521  *  - we set it to MODESET_ON_LID_OPEN on lid close,
 522  *    and set it to MODESET_DONE on open
 523  *  - we use it as a "only once" bit (ie we ignore
 524  *    duplicate events where it was already properly set)
 525  *  - the suspend/resume paths will set it to
 526  *    MODESET_SUSPENDED and ignore the lid open event,
 527  *    because they restore the mode ("lid open").
 528  */
 529 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 530                             void *unused)
 531 {
 532         struct intel_lvds_connector *lvds_connector =
 533                 container_of(nb, struct intel_lvds_connector, lid_notifier);
 534         struct drm_connector *connector = &lvds_connector->base.base;
 535         struct drm_device *dev = connector->dev;
 536         struct drm_i915_private *dev_priv = to_i915(dev);
 537
 538         if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
 539                 return NOTIFY_OK;
 540
 541         mutex_lock(&dev_priv->modeset_restore_lock);
 542         if (dev_priv->modeset_restore == MODESET_SUSPENDED)
 543                 goto exit;
 544         /*
 545          * check and update the status of LVDS connector after receiving
 546          * the LID nofication event.
 547          */
 548         connector->status = connector->funcs->detect(connector, false);
 549
 550         /* Don't force modeset on machines where it causes a GPU lockup */
 551         if (dmi_check_system(intel_no_modeset_on_lid))
 552                 goto exit;
 553         if (!acpi_lid_open()) {
 554                 /* do modeset on next lid open event */
 555                 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
 556                 goto exit;
 557         }
 558
 559         if (dev_priv->modeset_restore == MODESET_DONE)
 560                 goto exit;
 561
 562         /*
 563          * Some old platform's BIOS love to wreak havoc while the lid is closed.
 564          * We try to detect this here and undo any damage. The split for PCH
 565          * platforms is rather conservative and a bit arbitrary expect that on
 566          * those platforms VGA disabling requires actual legacy VGA I/O access,
 567          * and as part of the cleanup in the hw state restore we also redisable
 568          * the vga plane.
 569          */
 570         if (!HAS_PCH_SPLIT(dev))
 571                 intel_display_resume(dev);
 572
 573         dev_priv->modeset_restore = MODESET_DONE;
 574
 575 exit:
 576         mutex_unlock(&dev_priv->modeset_restore_lock);
 577         return NOTIFY_OK;
 578 }
 579
 580 /**
 581  * intel_lvds_destroy - unregister and free LVDS structures
 582  * @connector: connector to free
 583  *
 584  * Unregister the DDC bus for this connector then free the driver private
 585  * structure.
 586  */
 587 static void intel_lvds_destroy(struct drm_connector *connector)
 588 {
 589         struct intel_lvds_connector *lvds_connector =
 590                 to_lvds_connector(connector);
 591
 592         if (lvds_connector->lid_notifier.notifier_call)
 593                 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
 594
 595         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 596                 kfree(lvds_connector->base.edid);
 597
 598         intel_panel_fini(&lvds_connector->base.panel);
 599
 600         drm_connector_cleanup(connector);
 601         kfree(connector);
 602 }
 603
 604 static int intel_lvds_set_property(struct drm_connector *connector,
 605                                    struct drm_property *property,
 606                                    uint64_t value)
 607 {
 608         struct intel_connector *intel_connector = to_intel_connector(connector);
 609         struct drm_device *dev = connector->dev;
 610
 611         if (property == dev->mode_config.scaling_mode_property) {
 612                 struct drm_crtc *crtc;
 613
 614                 if (value == DRM_MODE_SCALE_NONE) {
 615                         DRM_DEBUG_KMS("no scaling not supported\n");
 616                         return -EINVAL;
 617                 }
 618
 619                 if (intel_connector->panel.fitting_mode == value) {
 620                         /* the LVDS scaling property is not changed */
 621                         return 0;
 622                 }
 623                 intel_connector->panel.fitting_mode = value;
 624
 625                 crtc = intel_attached_encoder(connector)->base.crtc;
 626                 if (crtc && crtc->state->enable) {
 627                         /*
 628                          * If the CRTC is enabled, the display will be changed
 629                          * according to the new panel fitting mode.
 630                          */
 631                         intel_crtc_restore_mode(crtc);
 632                 }
 633         }
 634
 635         return 0;
 636 }
 637
 638 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 639         .get_modes = intel_lvds_get_modes,
 640         .mode_valid = intel_lvds_mode_valid,
 641 };
 642
 643 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 644         .dpms = drm_atomic_helper_connector_dpms,
 645         .detect = intel_lvds_detect,
 646         .fill_modes = drm_helper_probe_single_connector_modes,
 647         .set_property = intel_lvds_set_property,
 648         .atomic_get_property = intel_connector_atomic_get_property,
 649         .late_register = intel_connector_register,
 650         .early_unregister = intel_connector_unregister,
 651         .destroy = intel_lvds_destroy,
 652         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 653         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 654 };
 655
 656 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 657         .destroy = intel_encoder_destroy,
 658 };
 659
 660 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 661 {
 662         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 663         return 1;
 664 }
 665
 666 /* These systems claim to have LVDS, but really don't */
 667 static const struct dmi_system_id intel_no_lvds[] = {
 668         {
 669                 .callback = intel_no_lvds_dmi_callback,
 670                 .ident = "Apple Mac Mini (Core series)",
 671                 .matches = {
 672                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 673                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 674                 },
 675         },
 676         {
 677                 .callback = intel_no_lvds_dmi_callback,
 678                 .ident = "Apple Mac Mini (Core 2 series)",
 679                 .matches = {
 680                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 681                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 682                 },
 683         },
 684         {
 685                 .callback = intel_no_lvds_dmi_callback,
 686                 .ident = "MSI IM-945GSE-A",
 687                 .matches = {
 688                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 689                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 690                 },
 691         },
 692         {
 693                 .callback = intel_no_lvds_dmi_callback,
 694                 .ident = "Dell Studio Hybrid",
 695                 .matches = {
 696                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 697                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 698                 },
 699         },
 700         {
 701                 .callback = intel_no_lvds_dmi_callback,
 702                 .ident = "Dell OptiPlex FX170",
 703                 .matches = {
 704                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 705                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 706                 },
 707         },
 708         {
 709                 .callback = intel_no_lvds_dmi_callback,
 710                 .ident = "AOpen Mini PC",
 711                 .matches = {
 712                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 713                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 714                 },
 715         },
 716         {
 717                 .callback = intel_no_lvds_dmi_callback,
 718                 .ident = "AOpen Mini PC MP915",
 719                 .matches = {
 720                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 721                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 722                 },
 723         },
 724         {
 725                 .callback = intel_no_lvds_dmi_callback,
 726                 .ident = "AOpen i915GMm-HFS",
 727                 .matches = {
 728                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 729                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 730                 },
 731         },
 732         {
 733                 .callback = intel_no_lvds_dmi_callback,
 734                 .ident = "AOpen i45GMx-I",
 735                 .matches = {
 736                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 737                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 738                 },
 739         },
 740         {
 741                 .callback = intel_no_lvds_dmi_callback,
 742                 .ident = "Aopen i945GTt-VFA",
 743                 .matches = {
 744                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 745                 },
 746         },
 747         {
 748                 .callback = intel_no_lvds_dmi_callback,
 749                 .ident = "Clientron U800",
 750                 .matches = {
 751                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 752                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 753                 },
 754         },
 755         {
 756                 .callback = intel_no_lvds_dmi_callback,
 757                 .ident = "Clientron E830",
 758                 .matches = {
 759                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 760                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 761                 },
 762         },
 763         {
 764                 .callback = intel_no_lvds_dmi_callback,
 765                 .ident = "Asus EeeBox PC EB1007",
 766                 .matches = {
 767                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 768                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 769                 },
 770         },
 771         {
 772                 .callback = intel_no_lvds_dmi_callback,
 773                 .ident = "Asus AT5NM10T-I",
 774                 .matches = {
 775                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 776                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 777                 },
 778         },
 779         {
 780                 .callback = intel_no_lvds_dmi_callback,
 781                 .ident = "Hewlett-Packard HP t5740",
 782                 .matches = {
 783                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 784                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 785                 },
 786         },
 787         {
 788                 .callback = intel_no_lvds_dmi_callback,
 789                 .ident = "Hewlett-Packard t5745",
 790                 .matches = {
 791                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 792                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 793                 },
 794         },
 795         {
 796                 .callback = intel_no_lvds_dmi_callback,
 797                 .ident = "Hewlett-Packard st5747",
 798                 .matches = {
 799                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 800                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 801                 },
 802         },
 803         {
 804                 .callback = intel_no_lvds_dmi_callback,
 805                 .ident = "MSI Wind Box DC500",
 806                 .matches = {
 807                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 808                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 809                 },
 810         },
 811         {
 812                 .callback = intel_no_lvds_dmi_callback,
 813                 .ident = "Gigabyte GA-D525TUD",
 814                 .matches = {
 815                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 816                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 817                 },
 818         },
 819         {
 820                 .callback = intel_no_lvds_dmi_callback,
 821                 .ident = "Supermicro X7SPA-H",
 822                 .matches = {
 823                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 824                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 825                 },
 826         },
 827         {
 828                 .callback = intel_no_lvds_dmi_callback,
 829                 .ident = "Fujitsu Esprimo Q900",
 830                 .matches = {
 831                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 832                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 833                 },
 834         },
 835         {
 836                 .callback = intel_no_lvds_dmi_callback,
 837                 .ident = "Intel D410PT",
 838                 .matches = {
 839                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 840                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 841                 },
 842         },
 843         {
 844                 .callback = intel_no_lvds_dmi_callback,
 845                 .ident = "Intel D425KT",
 846                 .matches = {
 847                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 848                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 849                 },
 850         },
 851         {
 852                 .callback = intel_no_lvds_dmi_callback,
 853                 .ident = "Intel D510MO",
 854                 .matches = {
 855                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 856                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 857                 },
 858         },
 859         {
 860                 .callback = intel_no_lvds_dmi_callback,
 861                 .ident = "Intel D525MW",
 862                 .matches = {
 863                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 864                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 865                 },
 866         },
 867         {
 868                 .callback = intel_no_lvds_dmi_callback,
 869                 .ident = "Radiant P845",
 870                 .matches = {
 871                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 872                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 873                 },
 874         },
 875
 876         { }     /* terminating entry */
 877 };
 878
 879 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 880 {
 881         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 882         return 1;
 883 }
 884
 885 static const struct dmi_system_id intel_dual_link_lvds[] = {
 886         {
 887                 .callback = intel_dual_link_lvds_callback,
 888                 .ident = "Apple MacBook Pro 15\" (2010)",
 889                 .matches = {
 890                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 891                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 892                 },
 893         },
 894         {
 895                 .callback = intel_dual_link_lvds_callback,
 896                 .ident = "Apple MacBook Pro 15\" (2011)",
 897                 .matches = {
 898                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 899                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 900                 },
 901         },
 902         {
 903                 .callback = intel_dual_link_lvds_callback,
 904                 .ident = "Apple MacBook Pro 15\" (2012)",
 905                 .matches = {
 906                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 907                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 908                 },
 909         },
 910         { }     /* terminating entry */
 911 };
 912
 913 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 914 {
 915         struct intel_encoder *intel_encoder;
 916
 917         for_each_intel_encoder(dev, intel_encoder)
 918                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 919                         return intel_encoder;
 920
 921         return NULL;
 922 }
 923
 924 bool intel_is_dual_link_lvds(struct drm_device *dev)
 925 {
 926         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 927
 928         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 929 }
 930
 931 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 932 {
 933         struct drm_device *dev = lvds_encoder->base.base.dev;
 934         unsigned int val;
 935         struct drm_i915_private *dev_priv = to_i915(dev);
 936
 937         /* use the module option value if specified */
 938         if (i915.lvds_channel_mode > 0)
 939                 return i915.lvds_channel_mode == 2;
 940
 941         /* single channel LVDS is limited to 112 MHz */
 942         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 943             > 112999)
 944                 return true;
 945
 946         if (dmi_check_system(intel_dual_link_lvds))
 947                 return true;
 948
 949         /* BIOS should set the proper LVDS register value at boot, but
 950          * in reality, it doesn't set the value when the lid is closed;
 951          * we need to check "the value to be set" in VBT when LVDS
 952          * register is uninitialized.
 953          */
 954         val = I915_READ(lvds_encoder->reg);
 955         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 956                 val = dev_priv->vbt.bios_lvds_val;
 957
 958         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 959 }
 960
 961 static bool intel_lvds_supported(struct drm_device *dev)
 962 {
 963         /* With the introduction of the PCH we gained a dedicated
 964          * LVDS presence pin, use it. */
 965         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 966                 return true;
 967
 968         /* Otherwise LVDS was only attached to mobile products,
 969          * except for the inglorious 830gm */
 970         if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
 971                 return true;
 972
 973         return false;
 974 }
 975
 976 /**
 977  * intel_lvds_init - setup LVDS connectors on this device
 978  * @dev: drm device
 979  *
 980  * Create the connector, register the LVDS DDC bus, and try to figure out what
 981  * modes we can display on the LVDS panel (if present).
 982  */
 983 void intel_lvds_init(struct drm_device *dev)
 984 {
 985         struct drm_i915_private *dev_priv = to_i915(dev);
 986         struct intel_lvds_encoder *lvds_encoder;
 987         struct intel_encoder *intel_encoder;
 988         struct intel_lvds_connector *lvds_connector;
 989         struct intel_connector *intel_connector;
 990         struct drm_connector *connector;
 991         struct drm_encoder *encoder;
 992         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 993         struct drm_display_mode *fixed_mode = NULL;
 994         struct drm_display_mode *downclock_mode = NULL;
 995         struct edid *edid;
 996         struct drm_crtc *crtc;
 997         i915_reg_t lvds_reg;
 998         u32 lvds;
 999         int pipe;
1000         u8 pin;
1001
1002         if (!intel_lvds_supported(dev))
1003                 return;
1004
1005         /* Skip init on machines we know falsely report LVDS */
1006         if (dmi_check_system(intel_no_lvds))
1007                 return;
1008
1009         if (HAS_PCH_SPLIT(dev))
1010                 lvds_reg = PCH_LVDS;
1011         else
1012                 lvds_reg = LVDS;
1013
1014         lvds = I915_READ(lvds_reg);
1015
1016         if (HAS_PCH_SPLIT(dev)) {
1017                 if ((lvds & LVDS_DETECTED) == 0)
1018                         return;
1019                 if (dev_priv->vbt.edp.support) {
1020                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
1021                         return;
1022                 }
1023         }
1024
1025         pin = GMBUS_PIN_PANEL;
1026         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
1027                 if ((lvds & LVDS_PORT_EN) == 0) {
1028                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
1029                         return;
1030                 }
1031                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
1032         }
1033
1034         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
1035         if (!lvds_encoder)
1036                 return;
1037
1038         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
1039         if (!lvds_connector) {
1040                 kfree(lvds_encoder);
1041                 return;
1042         }
1043
1044         if (intel_connector_init(&lvds_connector->base) < 0) {
1045                 kfree(lvds_connector);
1046                 kfree(lvds_encoder);
1047                 return;
1048         }
1049
1050         lvds_encoder->attached_connector = lvds_connector;
1051
1052         intel_encoder = &lvds_encoder->base;
1053         encoder = &intel_encoder->base;
1054         intel_connector = &lvds_connector->base;
1055         connector = &intel_connector->base;
1056         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1057                            DRM_MODE_CONNECTOR_LVDS);
1058
1059         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1060                          DRM_MODE_ENCODER_LVDS, "LVDS");
1061
1062         intel_encoder->enable = intel_enable_lvds;
1063         intel_encoder->pre_enable = intel_pre_enable_lvds;
1064         intel_encoder->compute_config = intel_lvds_compute_config;
1065         if (HAS_PCH_SPLIT(dev_priv)) {
1066                 intel_encoder->disable = pch_disable_lvds;
1067                 intel_encoder->post_disable = pch_post_disable_lvds;
1068         } else {
1069                 intel_encoder->disable = gmch_disable_lvds;
1070         }
1071         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1072         intel_encoder->get_config = intel_lvds_get_config;
1073         intel_connector->get_hw_state = intel_connector_get_hw_state;
1074
1075         intel_connector_attach_encoder(intel_connector, intel_encoder);
1076         intel_encoder->type = INTEL_OUTPUT_LVDS;
1077
1078         intel_encoder->cloneable = 0;
1079         if (HAS_PCH_SPLIT(dev))
1080                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1081         else if (IS_GEN4(dev))
1082                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1083         else
1084                 intel_encoder->crtc_mask = (1 << 1);
1085
1086         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1087         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1088         connector->interlace_allowed = false;
1089         connector->doublescan_allowed = false;
1090
1091         lvds_encoder->reg = lvds_reg;
1092
1093         /* create the scaling mode property */
1094         drm_mode_create_scaling_mode_property(dev);
1095         drm_object_attach_property(&connector->base,
1096                                       dev->mode_config.scaling_mode_property,
1097                                       DRM_MODE_SCALE_ASPECT);
1098         intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1099
1100         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1101         lvds_encoder->init_lvds_val = lvds;
1102
1103         /*
1104          * LVDS discovery:
1105          * 1) check for EDID on DDC
1106          * 2) check for VBT data
1107          * 3) check to see if LVDS is already on
1108          *    if none of the above, no panel
1109          * 4) make sure lid is open
1110          *    if closed, act like it's not there for now
1111          */
1112
1113         /*
1114          * Attempt to get the fixed panel mode from DDC.  Assume that the
1115          * preferred mode is the right one.
1116          */
1117         mutex_lock(&dev->mode_config.mutex);
1118         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1119                 edid = drm_get_edid_switcheroo(connector,
1120                                     intel_gmbus_get_adapter(dev_priv, pin));
1121         else
1122                 edid = drm_get_edid(connector,
1123                                     intel_gmbus_get_adapter(dev_priv, pin));
1124         if (edid) {
1125                 if (drm_add_edid_modes(connector, edid)) {
1126                         drm_mode_connector_update_edid_property(connector,
1127                                                                 edid);
1128                 } else {
1129                         kfree(edid);
1130                         edid = ERR_PTR(-EINVAL);
1131                 }
1132         } else {
1133                 edid = ERR_PTR(-ENOENT);
1134         }
1135         lvds_connector->base.edid = edid;
1136
1137         list_for_each_entry(scan, &connector->probed_modes, head) {
1138                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1139                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1140                         drm_mode_debug_printmodeline(scan);
1141
1142                         fixed_mode = drm_mode_duplicate(dev, scan);
1143                         if (fixed_mode)
1144                                 goto out;
1145                 }
1146         }
1147
1148         /* Failed to get EDID, what about VBT? */
1149         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1150                 DRM_DEBUG_KMS("using mode from VBT: ");
1151                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1152
1153                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1154                 if (fixed_mode) {
1155                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1156                         connector->display_info.width_mm = fixed_mode->width_mm;
1157                         connector->display_info.height_mm = fixed_mode->height_mm;
1158                         goto out;
1159                 }
1160         }
1161
1162         /*
1163          * If we didn't get EDID, try checking if the panel is already turned
1164          * on.  If so, assume that whatever is currently programmed is the
1165          * correct mode.
1166          */
1167
1168         /* Ironlake: FIXME if still fail, not try pipe mode now */
1169         if (HAS_PCH_SPLIT(dev))
1170                 goto failed;
1171
1172         pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1173         crtc = intel_get_crtc_for_pipe(dev, pipe);
1174
1175         if (crtc && (lvds & LVDS_PORT_EN)) {
1176                 fixed_mode = intel_crtc_mode_get(dev, crtc);
1177                 if (fixed_mode) {
1178                         DRM_DEBUG_KMS("using current (BIOS) mode: ");
1179                         drm_mode_debug_printmodeline(fixed_mode);
1180                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1181                         goto out;
1182                 }
1183         }
1184
1185         /* If we still don't have a mode after all that, give up. */
1186         if (!fixed_mode)
1187                 goto failed;
1188
1189 out:
1190         mutex_unlock(&dev->mode_config.mutex);
1191
1192         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1193         intel_panel_setup_backlight(connector, INVALID_PIPE);
1194
1195         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1196         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1197                       lvds_encoder->is_dual_link ? "dual" : "single");
1198
1199         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1200
1201         lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1202         if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1203                 DRM_DEBUG_KMS("lid notifier registration failed\n");
1204                 lvds_connector->lid_notifier.notifier_call = NULL;
1205         }
1206
1207         return;
1208
1209 failed:
1210         mutex_unlock(&dev->mode_config.mutex);
1211
1212         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1213         drm_connector_cleanup(connector);
1214         drm_encoder_cleanup(encoder);
1215         kfree(lvds_encoder);
1216         kfree(lvds_connector);
1217         return;
1218 }