drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47 };
  48
  49 struct intel_lvds_pps {
  50         /* 100us units */
  51         int t1_t2;
  52         int t3;
  53         int t4;
  54         int t5;
  55         int tx;
  56
  57         int divider;
  58
  59         int port;
  60         bool powerdown_on_reset;
  61 };
  62
  63 struct intel_lvds_encoder {
  64         struct intel_encoder base;
  65
  66         bool is_dual_link;
  67         i915_reg_t reg;
  68         u32 a3_power;
  69
  70         struct intel_lvds_pps init_pps;
  71         u32 init_lvds_val;
  72
  73         struct intel_lvds_connector *attached_connector;
  74 };
  75
  76 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  77 {
  78         return container_of(encoder, struct intel_lvds_encoder, base.base);
  79 }
  80
  81 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  82 {
  83         return container_of(connector, struct intel_lvds_connector, base.base);
  84 }
  85
  86 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  87                                     enum pipe *pipe)
  88 {
  89         struct drm_device *dev = encoder->base.dev;
  90         struct drm_i915_private *dev_priv = to_i915(dev);
  91         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  92         u32 tmp;
  93         bool ret;
  94
  95         if (!intel_display_power_get_if_enabled(dev_priv,
  96                                                 encoder->power_domain))
  97                 return false;
  98
  99         ret = false;
 100
 101         tmp = I915_READ(lvds_encoder->reg);
 102
 103         if (!(tmp & LVDS_PORT_EN))
 104                 goto out;
 105
 106         if (HAS_PCH_CPT(dev_priv))
 107                 *pipe = PORT_TO_PIPE_CPT(tmp);
 108         else
 109                 *pipe = PORT_TO_PIPE(tmp);
 110
 111         ret = true;
 112
 113 out:
 114         intel_display_power_put(dev_priv, encoder->power_domain);
 115
 116         return ret;
 117 }
 118
 119 static void intel_lvds_get_config(struct intel_encoder *encoder,
 120                                   struct intel_crtc_state *pipe_config)
 121 {
 122         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 123         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 124         u32 tmp, flags = 0;
 125
 126         tmp = I915_READ(lvds_encoder->reg);
 127         if (tmp & LVDS_HSYNC_POLARITY)
 128                 flags |= DRM_MODE_FLAG_NHSYNC;
 129         else
 130                 flags |= DRM_MODE_FLAG_PHSYNC;
 131         if (tmp & LVDS_VSYNC_POLARITY)
 132                 flags |= DRM_MODE_FLAG_NVSYNC;
 133         else
 134                 flags |= DRM_MODE_FLAG_PVSYNC;
 135
 136         pipe_config->base.adjusted_mode.flags |= flags;
 137
 138         if (INTEL_GEN(dev_priv) < 5)
 139                 pipe_config->gmch_pfit.lvds_border_bits =
 140                         tmp & LVDS_BORDER_ENABLE;
 141
 142         /* gen2/3 store dither state in pfit control, needs to match */
 143         if (INTEL_GEN(dev_priv) < 4) {
 144                 tmp = I915_READ(PFIT_CONTROL);
 145
 146                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 147         }
 148
 149         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 150 }
 151
 152 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 153                                         struct intel_lvds_pps *pps)
 154 {
 155         u32 val;
 156
 157         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 158
 159         val = I915_READ(PP_ON_DELAYS(0));
 160         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 161                     PANEL_PORT_SELECT_SHIFT;
 162         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 163                      PANEL_POWER_UP_DELAY_SHIFT;
 164         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 165                   PANEL_LIGHT_ON_DELAY_SHIFT;
 166
 167         val = I915_READ(PP_OFF_DELAYS(0));
 168         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 169                   PANEL_POWER_DOWN_DELAY_SHIFT;
 170         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 171                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 172
 173         val = I915_READ(PP_DIVISOR(0));
 174         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 175                        PP_REFERENCE_DIVIDER_SHIFT;
 176         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 177               PANEL_POWER_CYCLE_DELAY_SHIFT;
 178         /*
 179          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 180          * too short power-cycle delay due to the asynchronous programming of
 181          * the register.
 182          */
 183         if (val)
 184                 val--;
 185         /* Convert from 100ms to 100us units */
 186         pps->t4 = val * 1000;
 187
 188         if (INTEL_INFO(dev_priv)->gen <= 4 &&
 189             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 190                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 191                               "setting defaults\n");
 192                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 193                 pps->t1_t2 = 40 * 10;
 194                 pps->t5 = 200 * 10;
 195                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 196                 pps->t3 = 35 * 10;
 197                 pps->tx = 200 * 10;
 198         }
 199
 200         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 201                          "divider %d port %d powerdown_on_reset %d\n",
 202                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 203                          pps->divider, pps->port, pps->powerdown_on_reset);
 204 }
 205
 206 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 207                                    struct intel_lvds_pps *pps)
 208 {
 209         u32 val;
 210
 211         val = I915_READ(PP_CONTROL(0));
 212         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 213         if (pps->powerdown_on_reset)
 214                 val |= PANEL_POWER_RESET;
 215         I915_WRITE(PP_CONTROL(0), val);
 216
 217         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 218                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 219                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 220         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 221                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 222
 223         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 224         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 225                PANEL_POWER_CYCLE_DELAY_SHIFT;
 226         I915_WRITE(PP_DIVISOR(0), val);
 227 }
 228
 229 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 230                                   struct intel_crtc_state *pipe_config,
 231                                   struct drm_connector_state *conn_state)
 232 {
 233         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 234         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 235         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 236         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 237         int pipe = crtc->pipe;
 238         u32 temp;
 239
 240         if (HAS_PCH_SPLIT(dev_priv)) {
 241                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 242                 assert_shared_dpll_disabled(dev_priv,
 243                                             pipe_config->shared_dpll);
 244         } else {
 245                 assert_pll_disabled(dev_priv, pipe);
 246         }
 247
 248         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 249
 250         temp = lvds_encoder->init_lvds_val;
 251         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 252
 253         if (HAS_PCH_CPT(dev_priv)) {
 254                 temp &= ~PORT_TRANS_SEL_MASK;
 255                 temp |= PORT_TRANS_SEL_CPT(pipe);
 256         } else {
 257                 if (pipe == 1) {
 258                         temp |= LVDS_PIPEB_SELECT;
 259                 } else {
 260                         temp &= ~LVDS_PIPEB_SELECT;
 261                 }
 262         }
 263
 264         /* set the corresponsding LVDS_BORDER bit */
 265         temp &= ~LVDS_BORDER_ENABLE;
 266         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 267         /* Set the B0-B3 data pairs corresponding to whether we're going to
 268          * set the DPLLs for dual-channel mode or not.
 269          */
 270         if (lvds_encoder->is_dual_link)
 271                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 272         else
 273                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 274
 275         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 276          * appropriately here, but we need to look more thoroughly into how
 277          * panels behave in the two modes. For now, let's just maintain the
 278          * value we got from the BIOS.
 279          */
 280         temp &= ~LVDS_A3_POWER_MASK;
 281         temp |= lvds_encoder->a3_power;
 282
 283         /* Set the dithering flag on LVDS as needed, note that there is no
 284          * special lvds dither control bit on pch-split platforms, dithering is
 285          * only controlled through the PIPECONF reg. */
 286         if (IS_GEN4(dev_priv)) {
 287                 /* Bspec wording suggests that LVDS port dithering only exists
 288                  * for 18bpp panels. */
 289                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 290                         temp |= LVDS_ENABLE_DITHER;
 291                 else
 292                         temp &= ~LVDS_ENABLE_DITHER;
 293         }
 294         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 295         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 296                 temp |= LVDS_HSYNC_POLARITY;
 297         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 298                 temp |= LVDS_VSYNC_POLARITY;
 299
 300         I915_WRITE(lvds_encoder->reg, temp);
 301 }
 302
 303 /**
 304  * Sets the power state for the panel.
 305  */
 306 static void intel_enable_lvds(struct intel_encoder *encoder,
 307                               struct intel_crtc_state *pipe_config,
 308                               struct drm_connector_state *conn_state)
 309 {
 310         struct drm_device *dev = encoder->base.dev;
 311         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 312         struct drm_i915_private *dev_priv = to_i915(dev);
 313
 314         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 315
 316         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 317         POSTING_READ(lvds_encoder->reg);
 318
 319         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
 320                 DRM_ERROR("timed out waiting for panel to power on\n");
 321
 322         intel_panel_enable_backlight(pipe_config, conn_state);
 323 }
 324
 325 static void intel_disable_lvds(struct intel_encoder *encoder,
 326                                struct intel_crtc_state *old_crtc_state,
 327                                struct drm_connector_state *old_conn_state)
 328 {
 329         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 330         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 331
 332         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 333         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 334                 DRM_ERROR("timed out waiting for panel to power off\n");
 335
 336         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 337         POSTING_READ(lvds_encoder->reg);
 338 }
 339
 340 static void gmch_disable_lvds(struct intel_encoder *encoder,
 341                               struct intel_crtc_state *old_crtc_state,
 342                               struct drm_connector_state *old_conn_state)
 343
 344 {
 345         intel_panel_disable_backlight(old_conn_state);
 346
 347         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 348 }
 349
 350 static void pch_disable_lvds(struct intel_encoder *encoder,
 351                              struct intel_crtc_state *old_crtc_state,
 352                              struct drm_connector_state *old_conn_state)
 353 {
 354         intel_panel_disable_backlight(old_conn_state);
 355 }
 356
 357 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 358                                   struct intel_crtc_state *old_crtc_state,
 359                                   struct drm_connector_state *old_conn_state)
 360 {
 361         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 362 }
 363
 364 static enum drm_mode_status
 365 intel_lvds_mode_valid(struct drm_connector *connector,
 366                       struct drm_display_mode *mode)
 367 {
 368         struct intel_connector *intel_connector = to_intel_connector(connector);
 369         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 370         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 371
 372         if (mode->hdisplay > fixed_mode->hdisplay)
 373                 return MODE_PANEL;
 374         if (mode->vdisplay > fixed_mode->vdisplay)
 375                 return MODE_PANEL;
 376         if (fixed_mode->clock > max_pixclk)
 377                 return MODE_CLOCK_HIGH;
 378
 379         return MODE_OK;
 380 }
 381
 382 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 383                                       struct intel_crtc_state *pipe_config,
 384                                       struct drm_connector_state *conn_state)
 385 {
 386         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 387         struct intel_lvds_encoder *lvds_encoder =
 388                 to_lvds_encoder(&intel_encoder->base);
 389         struct intel_connector *intel_connector =
 390                 &lvds_encoder->attached_connector->base;
 391         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 392         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 393         unsigned int lvds_bpp;
 394
 395         /* Should never happen!! */
 396         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 397                 DRM_ERROR("Can't support LVDS on pipe A\n");
 398                 return false;
 399         }
 400
 401         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 402                 lvds_bpp = 8*3;
 403         else
 404                 lvds_bpp = 6*3;
 405
 406         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 407                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 408                               pipe_config->pipe_bpp, lvds_bpp);
 409                 pipe_config->pipe_bpp = lvds_bpp;
 410         }
 411
 412         /*
 413          * We have timings from the BIOS for the panel, put them in
 414          * to the adjusted mode.  The CRTC will be set up for this mode,
 415          * with the panel scaling set up to source from the H/VDisplay
 416          * of the original mode.
 417          */
 418         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 419                                adjusted_mode);
 420
 421         if (HAS_PCH_SPLIT(dev_priv)) {
 422                 pipe_config->has_pch_encoder = true;
 423
 424                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 425                                         conn_state->scaling_mode);
 426         } else {
 427                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 428                                          conn_state->scaling_mode);
 429
 430         }
 431
 432         /*
 433          * XXX: It would be nice to support lower refresh rates on the
 434          * panels to reduce power consumption, and perhaps match the
 435          * user's requested refresh rate.
 436          */
 437
 438         return true;
 439 }
 440
 441 static enum drm_connector_status
 442 intel_lvds_detect(struct drm_connector *connector, bool force)
 443 {
 444         return connector_status_connected;
 445 }
 446
 447 /**
 448  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 449  */
 450 static int intel_lvds_get_modes(struct drm_connector *connector)
 451 {
 452         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 453         struct drm_device *dev = connector->dev;
 454         struct drm_display_mode *mode;
 455
 456         /* use cached edid if we have one */
 457         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 458                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 459
 460         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 461         if (mode == NULL)
 462                 return 0;
 463
 464         drm_mode_probed_add(connector, mode);
 465         return 1;
 466 }
 467
 468 /**
 469  * intel_lvds_destroy - unregister and free LVDS structures
 470  * @connector: connector to free
 471  *
 472  * Unregister the DDC bus for this connector then free the driver private
 473  * structure.
 474  */
 475 static void intel_lvds_destroy(struct drm_connector *connector)
 476 {
 477         struct intel_lvds_connector *lvds_connector =
 478                 to_lvds_connector(connector);
 479
 480         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 481                 kfree(lvds_connector->base.edid);
 482
 483         intel_panel_fini(&lvds_connector->base.panel);
 484
 485         drm_connector_cleanup(connector);
 486         kfree(connector);
 487 }
 488
 489 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 490         .get_modes = intel_lvds_get_modes,
 491         .mode_valid = intel_lvds_mode_valid,
 492         .atomic_check = intel_digital_connector_atomic_check,
 493 };
 494
 495 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 496         .detect = intel_lvds_detect,
 497         .fill_modes = drm_helper_probe_single_connector_modes,
 498         .atomic_get_property = intel_digital_connector_atomic_get_property,
 499         .atomic_set_property = intel_digital_connector_atomic_set_property,
 500         .late_register = intel_connector_register,
 501         .early_unregister = intel_connector_unregister,
 502         .destroy = intel_lvds_destroy,
 503         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 504         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 505 };
 506
 507 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 508         .destroy = intel_encoder_destroy,
 509 };
 510
 511 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 512 {
 513         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 514         return 1;
 515 }
 516
 517 /* These systems claim to have LVDS, but really don't */
 518 static const struct dmi_system_id intel_no_lvds[] = {
 519         {
 520                 .callback = intel_no_lvds_dmi_callback,
 521                 .ident = "Apple Mac Mini (Core series)",
 522                 .matches = {
 523                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 524                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 525                 },
 526         },
 527         {
 528                 .callback = intel_no_lvds_dmi_callback,
 529                 .ident = "Apple Mac Mini (Core 2 series)",
 530                 .matches = {
 531                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 532                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 533                 },
 534         },
 535         {
 536                 .callback = intel_no_lvds_dmi_callback,
 537                 .ident = "MSI IM-945GSE-A",
 538                 .matches = {
 539                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 540                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 541                 },
 542         },
 543         {
 544                 .callback = intel_no_lvds_dmi_callback,
 545                 .ident = "Dell Studio Hybrid",
 546                 .matches = {
 547                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 548                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 549                 },
 550         },
 551         {
 552                 .callback = intel_no_lvds_dmi_callback,
 553                 .ident = "Dell OptiPlex FX170",
 554                 .matches = {
 555                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 556                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 557                 },
 558         },
 559         {
 560                 .callback = intel_no_lvds_dmi_callback,
 561                 .ident = "AOpen Mini PC",
 562                 .matches = {
 563                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 564                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 565                 },
 566         },
 567         {
 568                 .callback = intel_no_lvds_dmi_callback,
 569                 .ident = "AOpen Mini PC MP915",
 570                 .matches = {
 571                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 572                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 573                 },
 574         },
 575         {
 576                 .callback = intel_no_lvds_dmi_callback,
 577                 .ident = "AOpen i915GMm-HFS",
 578                 .matches = {
 579                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 580                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 581                 },
 582         },
 583         {
 584                 .callback = intel_no_lvds_dmi_callback,
 585                 .ident = "AOpen i45GMx-I",
 586                 .matches = {
 587                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 588                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 589                 },
 590         },
 591         {
 592                 .callback = intel_no_lvds_dmi_callback,
 593                 .ident = "Aopen i945GTt-VFA",
 594                 .matches = {
 595                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 596                 },
 597         },
 598         {
 599                 .callback = intel_no_lvds_dmi_callback,
 600                 .ident = "Clientron U800",
 601                 .matches = {
 602                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 603                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 604                 },
 605         },
 606         {
 607                 .callback = intel_no_lvds_dmi_callback,
 608                 .ident = "Clientron E830",
 609                 .matches = {
 610                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 611                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 612                 },
 613         },
 614         {
 615                 .callback = intel_no_lvds_dmi_callback,
 616                 .ident = "Asus EeeBox PC EB1007",
 617                 .matches = {
 618                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 619                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 620                 },
 621         },
 622         {
 623                 .callback = intel_no_lvds_dmi_callback,
 624                 .ident = "Asus AT5NM10T-I",
 625                 .matches = {
 626                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 627                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 628                 },
 629         },
 630         {
 631                 .callback = intel_no_lvds_dmi_callback,
 632                 .ident = "Hewlett-Packard HP t5740",
 633                 .matches = {
 634                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 635                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 636                 },
 637         },
 638         {
 639                 .callback = intel_no_lvds_dmi_callback,
 640                 .ident = "Hewlett-Packard t5745",
 641                 .matches = {
 642                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 643                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 644                 },
 645         },
 646         {
 647                 .callback = intel_no_lvds_dmi_callback,
 648                 .ident = "Hewlett-Packard st5747",
 649                 .matches = {
 650                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 651                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 652                 },
 653         },
 654         {
 655                 .callback = intel_no_lvds_dmi_callback,
 656                 .ident = "MSI Wind Box DC500",
 657                 .matches = {
 658                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 659                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 660                 },
 661         },
 662         {
 663                 .callback = intel_no_lvds_dmi_callback,
 664                 .ident = "Gigabyte GA-D525TUD",
 665                 .matches = {
 666                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 667                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 668                 },
 669         },
 670         {
 671                 .callback = intel_no_lvds_dmi_callback,
 672                 .ident = "Supermicro X7SPA-H",
 673                 .matches = {
 674                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 675                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 676                 },
 677         },
 678         {
 679                 .callback = intel_no_lvds_dmi_callback,
 680                 .ident = "Fujitsu Esprimo Q900",
 681                 .matches = {
 682                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 683                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 684                 },
 685         },
 686         {
 687                 .callback = intel_no_lvds_dmi_callback,
 688                 .ident = "Intel D410PT",
 689                 .matches = {
 690                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 691                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 692                 },
 693         },
 694         {
 695                 .callback = intel_no_lvds_dmi_callback,
 696                 .ident = "Intel D425KT",
 697                 .matches = {
 698                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 699                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 700                 },
 701         },
 702         {
 703                 .callback = intel_no_lvds_dmi_callback,
 704                 .ident = "Intel D510MO",
 705                 .matches = {
 706                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 707                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 708                 },
 709         },
 710         {
 711                 .callback = intel_no_lvds_dmi_callback,
 712                 .ident = "Intel D525MW",
 713                 .matches = {
 714                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 715                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 716                 },
 717         },
 718         {
 719                 .callback = intel_no_lvds_dmi_callback,
 720                 .ident = "Radiant P845",
 721                 .matches = {
 722                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 723                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 724                 },
 725         },
 726
 727         { }     /* terminating entry */
 728 };
 729
 730 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 731 {
 732         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 733         return 1;
 734 }
 735
 736 static const struct dmi_system_id intel_dual_link_lvds[] = {
 737         {
 738                 .callback = intel_dual_link_lvds_callback,
 739                 .ident = "Apple MacBook Pro 15\" (2010)",
 740                 .matches = {
 741                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 742                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 743                 },
 744         },
 745         {
 746                 .callback = intel_dual_link_lvds_callback,
 747                 .ident = "Apple MacBook Pro 15\" (2011)",
 748                 .matches = {
 749                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 750                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 751                 },
 752         },
 753         {
 754                 .callback = intel_dual_link_lvds_callback,
 755                 .ident = "Apple MacBook Pro 15\" (2012)",
 756                 .matches = {
 757                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 758                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 759                 },
 760         },
 761         { }     /* terminating entry */
 762 };
 763
 764 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 765 {
 766         struct intel_encoder *intel_encoder;
 767
 768         for_each_intel_encoder(dev, intel_encoder)
 769                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 770                         return intel_encoder;
 771
 772         return NULL;
 773 }
 774
 775 bool intel_is_dual_link_lvds(struct drm_device *dev)
 776 {
 777         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 778
 779         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 780 }
 781
 782 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 783 {
 784         struct drm_device *dev = lvds_encoder->base.base.dev;
 785         unsigned int val;
 786         struct drm_i915_private *dev_priv = to_i915(dev);
 787
 788         /* use the module option value if specified */
 789         if (i915.lvds_channel_mode > 0)
 790                 return i915.lvds_channel_mode == 2;
 791
 792         /* single channel LVDS is limited to 112 MHz */
 793         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 794             > 112999)
 795                 return true;
 796
 797         if (dmi_check_system(intel_dual_link_lvds))
 798                 return true;
 799
 800         /* BIOS should set the proper LVDS register value at boot, but
 801          * in reality, it doesn't set the value when the lid is closed;
 802          * we need to check "the value to be set" in VBT when LVDS
 803          * register is uninitialized.
 804          */
 805         val = I915_READ(lvds_encoder->reg);
 806         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 807                 val = dev_priv->vbt.bios_lvds_val;
 808
 809         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 810 }
 811
 812 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 813 {
 814         /* With the introduction of the PCH we gained a dedicated
 815          * LVDS presence pin, use it. */
 816         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 817                 return true;
 818
 819         /* Otherwise LVDS was only attached to mobile products,
 820          * except for the inglorious 830gm */
 821         if (INTEL_GEN(dev_priv) <= 4 &&
 822             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 823                 return true;
 824
 825         return false;
 826 }
 827
 828 /**
 829  * intel_lvds_init - setup LVDS connectors on this device
 830  * @dev: drm device
 831  *
 832  * Create the connector, register the LVDS DDC bus, and try to figure out what
 833  * modes we can display on the LVDS panel (if present).
 834  */
 835 void intel_lvds_init(struct drm_i915_private *dev_priv)
 836 {
 837         struct drm_device *dev = &dev_priv->drm;
 838         struct intel_lvds_encoder *lvds_encoder;
 839         struct intel_encoder *intel_encoder;
 840         struct intel_lvds_connector *lvds_connector;
 841         struct intel_connector *intel_connector;
 842         struct drm_connector *connector;
 843         struct drm_encoder *encoder;
 844         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 845         struct drm_display_mode *fixed_mode = NULL;
 846         struct drm_display_mode *downclock_mode = NULL;
 847         struct edid *edid;
 848         struct intel_crtc *crtc;
 849         i915_reg_t lvds_reg;
 850         u32 lvds;
 851         int pipe;
 852         u8 pin;
 853         u32 allowed_scalers;
 854
 855         if (!intel_lvds_supported(dev_priv))
 856                 return;
 857
 858         /* Skip init on machines we know falsely report LVDS */
 859         if (dmi_check_system(intel_no_lvds))
 860                 return;
 861
 862         if (HAS_PCH_SPLIT(dev_priv))
 863                 lvds_reg = PCH_LVDS;
 864         else
 865                 lvds_reg = LVDS;
 866
 867         lvds = I915_READ(lvds_reg);
 868
 869         if (HAS_PCH_SPLIT(dev_priv)) {
 870                 if ((lvds & LVDS_DETECTED) == 0)
 871                         return;
 872                 if (dev_priv->vbt.edp.support) {
 873                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
 874                         return;
 875                 }
 876         }
 877
 878         pin = GMBUS_PIN_PANEL;
 879         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 880                 if ((lvds & LVDS_PORT_EN) == 0) {
 881                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 882                         return;
 883                 }
 884                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 885         }
 886
 887         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 888         if (!lvds_encoder)
 889                 return;
 890
 891         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
 892         if (!lvds_connector) {
 893                 kfree(lvds_encoder);
 894                 return;
 895         }
 896
 897         if (intel_connector_init(&lvds_connector->base) < 0) {
 898                 kfree(lvds_connector);
 899                 kfree(lvds_encoder);
 900                 return;
 901         }
 902
 903         lvds_encoder->attached_connector = lvds_connector;
 904
 905         intel_encoder = &lvds_encoder->base;
 906         encoder = &intel_encoder->base;
 907         intel_connector = &lvds_connector->base;
 908         connector = &intel_connector->base;
 909         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
 910                            DRM_MODE_CONNECTOR_LVDS);
 911
 912         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
 913                          DRM_MODE_ENCODER_LVDS, "LVDS");
 914
 915         intel_encoder->enable = intel_enable_lvds;
 916         intel_encoder->pre_enable = intel_pre_enable_lvds;
 917         intel_encoder->compute_config = intel_lvds_compute_config;
 918         if (HAS_PCH_SPLIT(dev_priv)) {
 919                 intel_encoder->disable = pch_disable_lvds;
 920                 intel_encoder->post_disable = pch_post_disable_lvds;
 921         } else {
 922                 intel_encoder->disable = gmch_disable_lvds;
 923         }
 924         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 925         intel_encoder->get_config = intel_lvds_get_config;
 926         intel_connector->get_hw_state = intel_connector_get_hw_state;
 927
 928         intel_connector_attach_encoder(intel_connector, intel_encoder);
 929
 930         intel_encoder->type = INTEL_OUTPUT_LVDS;
 931         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 932         intel_encoder->port = PORT_NONE;
 933         intel_encoder->cloneable = 0;
 934         if (HAS_PCH_SPLIT(dev_priv))
 935                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 936         else if (IS_GEN4(dev_priv))
 937                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
 938         else
 939                 intel_encoder->crtc_mask = (1 << 1);
 940
 941         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
 942         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 943         connector->interlace_allowed = false;
 944         connector->doublescan_allowed = false;
 945
 946         lvds_encoder->reg = lvds_reg;
 947
 948         /* create the scaling mode property */
 949         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
 950         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
 951         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
 952         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
 953         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 954
 955         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
 956         lvds_encoder->init_lvds_val = lvds;
 957
 958         /*
 959          * LVDS discovery:
 960          * 1) check for EDID on DDC
 961          * 2) check for VBT data
 962          * 3) check to see if LVDS is already on
 963          *    if none of the above, no panel
 964          */
 965
 966         /*
 967          * Attempt to get the fixed panel mode from DDC.  Assume that the
 968          * preferred mode is the right one.
 969          */
 970         mutex_lock(&dev->mode_config.mutex);
 971         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 972                 edid = drm_get_edid_switcheroo(connector,
 973                                     intel_gmbus_get_adapter(dev_priv, pin));
 974         else
 975                 edid = drm_get_edid(connector,
 976                                     intel_gmbus_get_adapter(dev_priv, pin));
 977         if (edid) {
 978                 if (drm_add_edid_modes(connector, edid)) {
 979                         drm_mode_connector_update_edid_property(connector,
 980                                                                 edid);
 981                 } else {
 982                         kfree(edid);
 983                         edid = ERR_PTR(-EINVAL);
 984                 }
 985         } else {
 986                 edid = ERR_PTR(-ENOENT);
 987         }
 988         lvds_connector->base.edid = edid;
 989
 990         list_for_each_entry(scan, &connector->probed_modes, head) {
 991                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
 992                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
 993                         drm_mode_debug_printmodeline(scan);
 994
 995                         fixed_mode = drm_mode_duplicate(dev, scan);
 996                         if (fixed_mode)
 997                                 goto out;
 998                 }
 999         }
1000
1001         /* Failed to get EDID, what about VBT? */
1002         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1003                 DRM_DEBUG_KMS("using mode from VBT: ");
1004                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1005
1006                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1007                 if (fixed_mode) {
1008                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1009                         connector->display_info.width_mm = fixed_mode->width_mm;
1010                         connector->display_info.height_mm = fixed_mode->height_mm;
1011                         goto out;
1012                 }
1013         }
1014
1015         /*
1016          * If we didn't get EDID, try checking if the panel is already turned
1017          * on.  If so, assume that whatever is currently programmed is the
1018          * correct mode.
1019          */
1020
1021         /* Ironlake: FIXME if still fail, not try pipe mode now */
1022         if (HAS_PCH_SPLIT(dev_priv))
1023                 goto failed;
1024
1025         pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1026         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1027
1028         if (crtc && (lvds & LVDS_PORT_EN)) {
1029                 fixed_mode = intel_crtc_mode_get(dev, &crtc->base);
1030                 if (fixed_mode) {
1031                         DRM_DEBUG_KMS("using current (BIOS) mode: ");
1032                         drm_mode_debug_printmodeline(fixed_mode);
1033                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1034                         goto out;
1035                 }
1036         }
1037
1038         /* If we still don't have a mode after all that, give up. */
1039         if (!fixed_mode)
1040                 goto failed;
1041
1042 out:
1043         mutex_unlock(&dev->mode_config.mutex);
1044
1045         intel_panel_init(&intel_connector->panel, fixed_mode, NULL,
1046                          downclock_mode);
1047         intel_panel_setup_backlight(connector, INVALID_PIPE);
1048
1049         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1050         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1051                       lvds_encoder->is_dual_link ? "dual" : "single");
1052
1053         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1054
1055         return;
1056
1057 failed:
1058         mutex_unlock(&dev->mode_config.mutex);
1059
1060         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1061         drm_connector_cleanup(connector);
1062         drm_encoder_cleanup(encoder);
1063         kfree(lvds_encoder);
1064         kfree(lvds_connector);
1065         return;
1066 }