drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  33 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  34
  35 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  36 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  37
  38 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  39 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  40
  41 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  42 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  43
  44 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  45
  46 static const char * const forcewake_domain_names[] = {
  47         "render",
  48         "blitter",
  49         "media",
  50 };
  51
  52 const char *
  53 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  54 {
  55         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  56
  57         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  58                 return forcewake_domain_names[id];
  59
  60         WARN_ON(id);
  61
  62         return "unknown";
  63 }
  64
  65 static void
  66 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  67 {
  68         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  69                   "Device suspended\n");
  70 }
  71
  72 static inline void
  73 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  74 {
  75         WARN_ON(d->reg_set == 0);
  76         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  77 }
  78
  79 static inline void
  80 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  81 {
  82         mod_timer_pinned(&d->timer, jiffies + 1);
  83 }
  84
  85 static inline void
  86 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  87 {
  88         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  89                              FORCEWAKE_KERNEL) == 0,
  90                             FORCEWAKE_ACK_TIMEOUT_MS))
  91                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  92                           intel_uncore_forcewake_domain_to_str(d->id));
  93 }
  94
  95 static inline void
  96 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  97 {
  98         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  99 }
 100
 101 static inline void
 102 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
 103 {
 104         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
 105                              FORCEWAKE_KERNEL),
 106                             FORCEWAKE_ACK_TIMEOUT_MS))
 107                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 108                           intel_uncore_forcewake_domain_to_str(d->id));
 109 }
 110
 111 static inline void
 112 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 113 {
 114         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 115 }
 116
 117 static inline void
 118 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 119 {
 120         /* something from same cacheline, but not from the set register */
 121         if (d->reg_post)
 122                 __raw_posting_read(d->i915, d->reg_post);
 123 }
 124
 125 static void
 126 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 127 {
 128         struct intel_uncore_forcewake_domain *d;
 129         enum forcewake_domain_id id;
 130
 131         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 132                 fw_domain_wait_ack_clear(d);
 133                 fw_domain_get(d);
 134                 fw_domain_wait_ack(d);
 135         }
 136 }
 137
 138 static void
 139 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 140 {
 141         struct intel_uncore_forcewake_domain *d;
 142         enum forcewake_domain_id id;
 143
 144         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 145                 fw_domain_put(d);
 146                 fw_domain_posting_read(d);
 147         }
 148 }
 149
 150 static void
 151 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 152 {
 153         struct intel_uncore_forcewake_domain *d;
 154         enum forcewake_domain_id id;
 155
 156         /* No need to do for all, just do for first found */
 157         for_each_fw_domain(d, dev_priv, id) {
 158                 fw_domain_posting_read(d);
 159                 break;
 160         }
 161 }
 162
 163 static void
 164 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 165 {
 166         struct intel_uncore_forcewake_domain *d;
 167         enum forcewake_domain_id id;
 168
 169         if (dev_priv->uncore.fw_domains == 0)
 170                 return;
 171
 172         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 173                 fw_domain_reset(d);
 174
 175         fw_domains_posting_read(dev_priv);
 176 }
 177
 178 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 179 {
 180         /* w/a for a sporadic read returning 0 by waiting for the GT
 181          * thread to wake up.
 182          */
 183         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 184                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 185                 DRM_ERROR("GT thread status wait timed out\n");
 186 }
 187
 188 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 189                                               enum forcewake_domains fw_domains)
 190 {
 191         fw_domains_get(dev_priv, fw_domains);
 192
 193         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 194         __gen6_gt_wait_for_thread_c0(dev_priv);
 195 }
 196
 197 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 198 {
 199         u32 gtfifodbg;
 200
 201         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 202         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 203                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 204 }
 205
 206 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 207                                      enum forcewake_domains fw_domains)
 208 {
 209         fw_domains_put(dev_priv, fw_domains);
 210         gen6_gt_check_fifodbg(dev_priv);
 211 }
 212
 213 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 214 {
 215         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 216
 217         return count & GT_FIFO_FREE_ENTRIES_MASK;
 218 }
 219
 220 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 221 {
 222         int ret = 0;
 223
 224         /* On VLV, FIFO will be shared by both SW and HW.
 225          * So, we need to read the FREE_ENTRIES everytime */
 226         if (IS_VALLEYVIEW(dev_priv->dev))
 227                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 228
 229         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 230                 int loop = 500;
 231                 u32 fifo = fifo_free_entries(dev_priv);
 232
 233                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 234                         udelay(10);
 235                         fifo = fifo_free_entries(dev_priv);
 236                 }
 237                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 238                         ++ret;
 239                 dev_priv->uncore.fifo_count = fifo;
 240         }
 241         dev_priv->uncore.fifo_count--;
 242
 243         return ret;
 244 }
 245
 246 static void intel_uncore_fw_release_timer(unsigned long arg)
 247 {
 248         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 249         unsigned long irqflags;
 250
 251         assert_device_not_suspended(domain->i915);
 252
 253         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 254         if (WARN_ON(domain->wake_count == 0))
 255                 domain->wake_count++;
 256
 257         if (--domain->wake_count == 0)
 258                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 259                                                           1 << domain->id);
 260
 261         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 262 }
 263
 264 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 265 {
 266         struct drm_i915_private *dev_priv = dev->dev_private;
 267         unsigned long irqflags;
 268         struct intel_uncore_forcewake_domain *domain;
 269         int retry_count = 100;
 270         enum forcewake_domain_id id;
 271         enum forcewake_domains fw = 0, active_domains;
 272
 273         /* Hold uncore.lock across reset to prevent any register access
 274          * with forcewake not set correctly. Wait until all pending
 275          * timers are run before holding.
 276          */
 277         while (1) {
 278                 active_domains = 0;
 279
 280                 for_each_fw_domain(domain, dev_priv, id) {
 281                         if (del_timer_sync(&domain->timer) == 0)
 282                                 continue;
 283
 284                         intel_uncore_fw_release_timer((unsigned long)domain);
 285                 }
 286
 287                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 288
 289                 for_each_fw_domain(domain, dev_priv, id) {
 290                         if (timer_pending(&domain->timer))
 291                                 active_domains |= (1 << id);
 292                 }
 293
 294                 if (active_domains == 0)
 295                         break;
 296
 297                 if (--retry_count == 0) {
 298                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 299                         break;
 300                 }
 301
 302                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 303                 cond_resched();
 304         }
 305
 306         WARN_ON(active_domains);
 307
 308         for_each_fw_domain(domain, dev_priv, id)
 309                 if (domain->wake_count)
 310                         fw |= 1 << id;
 311
 312         if (fw)
 313                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 314
 315         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 316
 317         if (restore) { /* If reset with a user forcewake, try to restore */
 318                 if (fw)
 319                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 320
 321                 if (IS_GEN6(dev) || IS_GEN7(dev))
 322                         dev_priv->uncore.fifo_count =
 323                                 fifo_free_entries(dev_priv);
 324         }
 325
 326         if (!restore)
 327                 assert_forcewakes_inactive(dev_priv);
 328
 329         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 330 }
 331
 332 static void intel_uncore_ellc_detect(struct drm_device *dev)
 333 {
 334         struct drm_i915_private *dev_priv = dev->dev_private;
 335
 336         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 337              INTEL_INFO(dev)->gen >= 9) &&
 338             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 339                 /* The docs do not explain exactly how the calculation can be
 340                  * made. It is somewhat guessable, but for now, it's always
 341                  * 128MB.
 342                  * NB: We can't write IDICR yet because we do not have gt funcs
 343                  * set up */
 344                 dev_priv->ellc_size = 128;
 345                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 346         }
 347 }
 348
 349 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 350                                           bool restore_forcewake)
 351 {
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353
 354         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 355                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 356
 357         /* clear out old GT FIFO errors */
 358         if (IS_GEN6(dev) || IS_GEN7(dev))
 359                 __raw_i915_write32(dev_priv, GTFIFODBG,
 360                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 361
 362         /* WaDisableShadowRegForCpd:chv */
 363         if (IS_CHERRYVIEW(dev)) {
 364                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 365                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 366                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 367                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 368         }
 369
 370         intel_uncore_forcewake_reset(dev, restore_forcewake);
 371 }
 372
 373 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 374 {
 375         __intel_uncore_early_sanitize(dev, restore_forcewake);
 376         i915_check_and_clear_faults(dev);
 377 }
 378
 379 void intel_uncore_sanitize(struct drm_device *dev)
 380 {
 381         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 382         intel_disable_gt_powersave(dev);
 383 }
 384
 385 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 386                                          enum forcewake_domains fw_domains)
 387 {
 388         struct intel_uncore_forcewake_domain *domain;
 389         enum forcewake_domain_id id;
 390
 391         if (!dev_priv->uncore.funcs.force_wake_get)
 392                 return;
 393
 394         fw_domains &= dev_priv->uncore.fw_domains;
 395
 396         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 397                 if (domain->wake_count++)
 398                         fw_domains &= ~(1 << id);
 399         }
 400
 401         if (fw_domains)
 402                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 403 }
 404
 405 /**
 406  * intel_uncore_forcewake_get - grab forcewake domain references
 407  * @dev_priv: i915 device instance
 408  * @fw_domains: forcewake domains to get reference on
 409  *
 410  * This function can be used get GT's forcewake domain references.
 411  * Normal register access will handle the forcewake domains automatically.
 412  * However if some sequence requires the GT to not power down a particular
 413  * forcewake domains this function should be called at the beginning of the
 414  * sequence. And subsequently the reference should be dropped by symmetric
 415  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 416  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 417  */
 418 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 419                                 enum forcewake_domains fw_domains)
 420 {
 421         unsigned long irqflags;
 422
 423         if (!dev_priv->uncore.funcs.force_wake_get)
 424                 return;
 425
 426         WARN_ON(dev_priv->pm.suspended);
 427
 428         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 429         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 430         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 431 }
 432
 433 /**
 434  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 435  * @dev_priv: i915 device instance
 436  * @fw_domains: forcewake domains to get reference on
 437  *
 438  * See intel_uncore_forcewake_get(). This variant places the onus
 439  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 440  */
 441 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 442                                         enum forcewake_domains fw_domains)
 443 {
 444         assert_spin_locked(&dev_priv->uncore.lock);
 445
 446         if (!dev_priv->uncore.funcs.force_wake_get)
 447                 return;
 448
 449         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 450 }
 451
 452 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 453                                          enum forcewake_domains fw_domains)
 454 {
 455         struct intel_uncore_forcewake_domain *domain;
 456         enum forcewake_domain_id id;
 457
 458         if (!dev_priv->uncore.funcs.force_wake_put)
 459                 return;
 460
 461         fw_domains &= dev_priv->uncore.fw_domains;
 462
 463         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 464                 if (WARN_ON(domain->wake_count == 0))
 465                         continue;
 466
 467                 if (--domain->wake_count)
 468                         continue;
 469
 470                 domain->wake_count++;
 471                 fw_domain_arm_timer(domain);
 472         }
 473 }
 474
 475 /**
 476  * intel_uncore_forcewake_put - release a forcewake domain reference
 477  * @dev_priv: i915 device instance
 478  * @fw_domains: forcewake domains to put references
 479  *
 480  * This function drops the device-level forcewakes for specified
 481  * domains obtained by intel_uncore_forcewake_get().
 482  */
 483 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 484                                 enum forcewake_domains fw_domains)
 485 {
 486         unsigned long irqflags;
 487
 488         if (!dev_priv->uncore.funcs.force_wake_put)
 489                 return;
 490
 491         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 492         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 493         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 494 }
 495
 496 /**
 497  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 498  * @dev_priv: i915 device instance
 499  * @fw_domains: forcewake domains to get reference on
 500  *
 501  * See intel_uncore_forcewake_put(). This variant places the onus
 502  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 503  */
 504 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 505                                         enum forcewake_domains fw_domains)
 506 {
 507         assert_spin_locked(&dev_priv->uncore.lock);
 508
 509         if (!dev_priv->uncore.funcs.force_wake_put)
 510                 return;
 511
 512         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 513 }
 514
 515 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 516 {
 517         struct intel_uncore_forcewake_domain *domain;
 518         enum forcewake_domain_id id;
 519
 520         if (!dev_priv->uncore.funcs.force_wake_get)
 521                 return;
 522
 523         for_each_fw_domain(domain, dev_priv, id)
 524                 WARN_ON(domain->wake_count);
 525 }
 526
 527 /* We give fast paths for the really cool registers */
 528 #define NEEDS_FORCE_WAKE(reg) \
 529          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 530
 531 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 532
 533 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 534         (REG_RANGE((reg), 0x2000, 0x4000) || \
 535          REG_RANGE((reg), 0x5000, 0x8000) || \
 536          REG_RANGE((reg), 0xB000, 0x12000) || \
 537          REG_RANGE((reg), 0x2E000, 0x30000))
 538
 539 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 540         (REG_RANGE((reg), 0x12000, 0x14000) || \
 541          REG_RANGE((reg), 0x22000, 0x24000) || \
 542          REG_RANGE((reg), 0x30000, 0x40000))
 543
 544 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 545         (REG_RANGE((reg), 0x2000, 0x4000) || \
 546          REG_RANGE((reg), 0x5200, 0x8000) || \
 547          REG_RANGE((reg), 0x8300, 0x8500) || \
 548          REG_RANGE((reg), 0xB000, 0xB480) || \
 549          REG_RANGE((reg), 0xE000, 0xE800))
 550
 551 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 552         (REG_RANGE((reg), 0x8800, 0x8900) || \
 553          REG_RANGE((reg), 0xD000, 0xD800) || \
 554          REG_RANGE((reg), 0x12000, 0x14000) || \
 555          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 556          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 557          REG_RANGE((reg), 0x30000, 0x38000))
 558
 559 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 560         (REG_RANGE((reg), 0x4000, 0x5000) || \
 561          REG_RANGE((reg), 0x8000, 0x8300) || \
 562          REG_RANGE((reg), 0x8500, 0x8600) || \
 563          REG_RANGE((reg), 0x9000, 0xB000) || \
 564          REG_RANGE((reg), 0xF000, 0x10000))
 565
 566 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 567         REG_RANGE((reg), 0xB00,  0x2000)
 568
 569 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 570         (REG_RANGE((reg), 0x2000, 0x2700) || \
 571          REG_RANGE((reg), 0x3000, 0x4000) || \
 572          REG_RANGE((reg), 0x5200, 0x8000) || \
 573          REG_RANGE((reg), 0x8140, 0x8160) || \
 574          REG_RANGE((reg), 0x8300, 0x8500) || \
 575          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 576          REG_RANGE((reg), 0xB000, 0xB480) || \
 577          REG_RANGE((reg), 0xE000, 0xE900) || \
 578          REG_RANGE((reg), 0x24400, 0x24800))
 579
 580 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 581         (REG_RANGE((reg), 0x8130, 0x8140) || \
 582          REG_RANGE((reg), 0x8800, 0x8A00) || \
 583          REG_RANGE((reg), 0xD000, 0xD800) || \
 584          REG_RANGE((reg), 0x12000, 0x14000) || \
 585          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 586          REG_RANGE((reg), 0x30000, 0x40000))
 587
 588 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 589         REG_RANGE((reg), 0x9400, 0x9800)
 590
 591 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 592         ((reg) < 0x40000 &&\
 593          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 594          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 595          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 596          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 597
 598 static void
 599 ilk_dummy_write(struct drm_i915_private *dev_priv)
 600 {
 601         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 602          * the chip from rc6 before touching it for real. MI_MODE is masked,
 603          * hence harmless to write 0 into. */
 604         __raw_i915_write32(dev_priv, MI_MODE, 0);
 605 }
 606
 607 static void
 608 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 609                         bool before)
 610 {
 611         const char *op = read ? "reading" : "writing to";
 612         const char *when = before ? "before" : "after";
 613
 614         if (!i915.mmio_debug)
 615                 return;
 616
 617         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 618                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 619                      when, op, reg);
 620                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 621                 i915.mmio_debug--; /* Only report the first N failures */
 622         }
 623 }
 624
 625 static void
 626 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 627 {
 628         static bool mmio_debug_once = true;
 629
 630         if (i915.mmio_debug || !mmio_debug_once)
 631                 return;
 632
 633         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 634                 DRM_DEBUG("Unclaimed register detected, "
 635                           "enabling oneshot unclaimed register reporting. "
 636                           "Please use i915.mmio_debug=N for more information.\n");
 637                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 638                 i915.mmio_debug = mmio_debug_once;
 639                 mmio_debug_once = false;
 640         }
 641 }
 642
 643 #define GEN2_READ_HEADER(x) \
 644         u##x val = 0; \
 645         assert_device_not_suspended(dev_priv);
 646
 647 #define GEN2_READ_FOOTER \
 648         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 649         return val
 650
 651 #define __gen2_read(x) \
 652 static u##x \
 653 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 654         GEN2_READ_HEADER(x); \
 655         val = __raw_i915_read##x(dev_priv, reg); \
 656         GEN2_READ_FOOTER; \
 657 }
 658
 659 #define __gen5_read(x) \
 660 static u##x \
 661 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 662         GEN2_READ_HEADER(x); \
 663         ilk_dummy_write(dev_priv); \
 664         val = __raw_i915_read##x(dev_priv, reg); \
 665         GEN2_READ_FOOTER; \
 666 }
 667
 668 __gen5_read(8)
 669 __gen5_read(16)
 670 __gen5_read(32)
 671 __gen5_read(64)
 672 __gen2_read(8)
 673 __gen2_read(16)
 674 __gen2_read(32)
 675 __gen2_read(64)
 676
 677 #undef __gen5_read
 678 #undef __gen2_read
 679
 680 #undef GEN2_READ_FOOTER
 681 #undef GEN2_READ_HEADER
 682
 683 #define GEN6_READ_HEADER(x) \
 684         unsigned long irqflags; \
 685         u##x val = 0; \
 686         assert_device_not_suspended(dev_priv); \
 687         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 688
 689 #define GEN6_READ_FOOTER \
 690         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 691         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 692         return val
 693
 694 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 695                                     enum forcewake_domains fw_domains)
 696 {
 697         struct intel_uncore_forcewake_domain *domain;
 698         enum forcewake_domain_id id;
 699
 700         if (WARN_ON(!fw_domains))
 701                 return;
 702
 703         /* Ideally GCC would be constant-fold and eliminate this loop */
 704         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 705                 if (domain->wake_count) {
 706                         fw_domains &= ~(1 << id);
 707                         continue;
 708                 }
 709
 710                 domain->wake_count++;
 711                 fw_domain_arm_timer(domain);
 712         }
 713
 714         if (fw_domains)
 715                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 716 }
 717
 718 #define __vgpu_read(x) \
 719 static u##x \
 720 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 721         GEN6_READ_HEADER(x); \
 722         val = __raw_i915_read##x(dev_priv, reg); \
 723         GEN6_READ_FOOTER; \
 724 }
 725
 726 #define __gen6_read(x) \
 727 static u##x \
 728 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 729         GEN6_READ_HEADER(x); \
 730         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 731         if (NEEDS_FORCE_WAKE(reg)) \
 732                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 733         val = __raw_i915_read##x(dev_priv, reg); \
 734         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 735         GEN6_READ_FOOTER; \
 736 }
 737
 738 #define __vlv_read(x) \
 739 static u##x \
 740 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 741         GEN6_READ_HEADER(x); \
 742         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 743                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 744         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
 745                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 746         val = __raw_i915_read##x(dev_priv, reg); \
 747         GEN6_READ_FOOTER; \
 748 }
 749
 750 #define __chv_read(x) \
 751 static u##x \
 752 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 753         GEN6_READ_HEADER(x); \
 754         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 755                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 756         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 757                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 758         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 759                 __force_wake_get(dev_priv, \
 760                                  FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 761         val = __raw_i915_read##x(dev_priv, reg); \
 762         GEN6_READ_FOOTER; \
 763 }
 764
 765 #define SKL_NEEDS_FORCE_WAKE(reg) \
 766          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 767
 768 #define __gen9_read(x) \
 769 static u##x \
 770 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 771         enum forcewake_domains fw_engine; \
 772         GEN6_READ_HEADER(x); \
 773         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 774         if (!SKL_NEEDS_FORCE_WAKE(reg)) \
 775                 fw_engine = 0; \
 776         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 777                 fw_engine = FORCEWAKE_RENDER; \
 778         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 779                 fw_engine = FORCEWAKE_MEDIA; \
 780         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 781                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 782         else \
 783                 fw_engine = FORCEWAKE_BLITTER; \
 784         if (fw_engine) \
 785                 __force_wake_get(dev_priv, fw_engine); \
 786         val = __raw_i915_read##x(dev_priv, reg); \
 787         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 788         GEN6_READ_FOOTER; \
 789 }
 790
 791 __vgpu_read(8)
 792 __vgpu_read(16)
 793 __vgpu_read(32)
 794 __vgpu_read(64)
 795 __gen9_read(8)
 796 __gen9_read(16)
 797 __gen9_read(32)
 798 __gen9_read(64)
 799 __chv_read(8)
 800 __chv_read(16)
 801 __chv_read(32)
 802 __chv_read(64)
 803 __vlv_read(8)
 804 __vlv_read(16)
 805 __vlv_read(32)
 806 __vlv_read(64)
 807 __gen6_read(8)
 808 __gen6_read(16)
 809 __gen6_read(32)
 810 __gen6_read(64)
 811
 812 #undef __gen9_read
 813 #undef __chv_read
 814 #undef __vlv_read
 815 #undef __gen6_read
 816 #undef __vgpu_read
 817 #undef GEN6_READ_FOOTER
 818 #undef GEN6_READ_HEADER
 819
 820 #define GEN2_WRITE_HEADER \
 821         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 822         assert_device_not_suspended(dev_priv); \
 823
 824 #define GEN2_WRITE_FOOTER
 825
 826 #define __gen2_write(x) \
 827 static void \
 828 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 829         GEN2_WRITE_HEADER; \
 830         __raw_i915_write##x(dev_priv, reg, val); \
 831         GEN2_WRITE_FOOTER; \
 832 }
 833
 834 #define __gen5_write(x) \
 835 static void \
 836 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 837         GEN2_WRITE_HEADER; \
 838         ilk_dummy_write(dev_priv); \
 839         __raw_i915_write##x(dev_priv, reg, val); \
 840         GEN2_WRITE_FOOTER; \
 841 }
 842
 843 __gen5_write(8)
 844 __gen5_write(16)
 845 __gen5_write(32)
 846 __gen5_write(64)
 847 __gen2_write(8)
 848 __gen2_write(16)
 849 __gen2_write(32)
 850 __gen2_write(64)
 851
 852 #undef __gen5_write
 853 #undef __gen2_write
 854
 855 #undef GEN2_WRITE_FOOTER
 856 #undef GEN2_WRITE_HEADER
 857
 858 #define GEN6_WRITE_HEADER \
 859         unsigned long irqflags; \
 860         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 861         assert_device_not_suspended(dev_priv); \
 862         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 863
 864 #define GEN6_WRITE_FOOTER \
 865         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 866
 867 #define __gen6_write(x) \
 868 static void \
 869 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 870         u32 __fifo_ret = 0; \
 871         GEN6_WRITE_HEADER; \
 872         if (NEEDS_FORCE_WAKE(reg)) { \
 873                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 874         } \
 875         __raw_i915_write##x(dev_priv, reg, val); \
 876         if (unlikely(__fifo_ret)) { \
 877                 gen6_gt_check_fifodbg(dev_priv); \
 878         } \
 879         GEN6_WRITE_FOOTER; \
 880 }
 881
 882 #define __hsw_write(x) \
 883 static void \
 884 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 885         u32 __fifo_ret = 0; \
 886         GEN6_WRITE_HEADER; \
 887         if (NEEDS_FORCE_WAKE(reg)) { \
 888                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 889         } \
 890         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 891         __raw_i915_write##x(dev_priv, reg, val); \
 892         if (unlikely(__fifo_ret)) { \
 893                 gen6_gt_check_fifodbg(dev_priv); \
 894         } \
 895         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 896         hsw_unclaimed_reg_detect(dev_priv); \
 897         GEN6_WRITE_FOOTER; \
 898 }
 899
 900 #define __vgpu_write(x) \
 901 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
 902                           off_t reg, u##x val, bool trace) { \
 903         GEN6_WRITE_HEADER; \
 904         __raw_i915_write##x(dev_priv, reg, val); \
 905         GEN6_WRITE_FOOTER; \
 906 }
 907
 908 static const u32 gen8_shadowed_regs[] = {
 909         FORCEWAKE_MT,
 910         GEN6_RPNSWREQ,
 911         GEN6_RC_VIDEO_FREQ,
 912         RING_TAIL(RENDER_RING_BASE),
 913         RING_TAIL(GEN6_BSD_RING_BASE),
 914         RING_TAIL(VEBOX_RING_BASE),
 915         RING_TAIL(BLT_RING_BASE),
 916         /* TODO: Other registers are not yet used */
 917 };
 918
 919 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 920 {
 921         int i;
 922         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 923                 if (reg == gen8_shadowed_regs[i])
 924                         return true;
 925
 926         return false;
 927 }
 928
 929 #define __gen8_write(x) \
 930 static void \
 931 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 932         GEN6_WRITE_HEADER; \
 933         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 934         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 935                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 936         __raw_i915_write##x(dev_priv, reg, val); \
 937         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 938         hsw_unclaimed_reg_detect(dev_priv); \
 939         GEN6_WRITE_FOOTER; \
 940 }
 941
 942 #define __chv_write(x) \
 943 static void \
 944 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 945         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 946         GEN6_WRITE_HEADER; \
 947         if (!shadowed) { \
 948                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 949                         __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 950                 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 951                         __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 952                 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 953                         __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 954         } \
 955         __raw_i915_write##x(dev_priv, reg, val); \
 956         GEN6_WRITE_FOOTER; \
 957 }
 958
 959 static const u32 gen9_shadowed_regs[] = {
 960         RING_TAIL(RENDER_RING_BASE),
 961         RING_TAIL(GEN6_BSD_RING_BASE),
 962         RING_TAIL(VEBOX_RING_BASE),
 963         RING_TAIL(BLT_RING_BASE),
 964         FORCEWAKE_BLITTER_GEN9,
 965         FORCEWAKE_RENDER_GEN9,
 966         FORCEWAKE_MEDIA_GEN9,
 967         GEN6_RPNSWREQ,
 968         GEN6_RC_VIDEO_FREQ,
 969         /* TODO: Other registers are not yet used */
 970 };
 971
 972 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 973 {
 974         int i;
 975         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 976                 if (reg == gen9_shadowed_regs[i])
 977                         return true;
 978
 979         return false;
 980 }
 981
 982 #define __gen9_write(x) \
 983 static void \
 984 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 985                 bool trace) { \
 986         enum forcewake_domains fw_engine; \
 987         GEN6_WRITE_HEADER; \
 988         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 989         if (!SKL_NEEDS_FORCE_WAKE(reg) || \
 990             is_gen9_shadowed(dev_priv, reg)) \
 991                 fw_engine = 0; \
 992         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 993                 fw_engine = FORCEWAKE_RENDER; \
 994         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 995                 fw_engine = FORCEWAKE_MEDIA; \
 996         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 997                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 998         else \
 999                 fw_engine = FORCEWAKE_BLITTER; \
1000         if (fw_engine) \
1001                 __force_wake_get(dev_priv, fw_engine); \
1002         __raw_i915_write##x(dev_priv, reg, val); \
1003         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
1004         hsw_unclaimed_reg_detect(dev_priv); \
1005         GEN6_WRITE_FOOTER; \
1006 }
1007
1008 __gen9_write(8)
1009 __gen9_write(16)
1010 __gen9_write(32)
1011 __gen9_write(64)
1012 __chv_write(8)
1013 __chv_write(16)
1014 __chv_write(32)
1015 __chv_write(64)
1016 __gen8_write(8)
1017 __gen8_write(16)
1018 __gen8_write(32)
1019 __gen8_write(64)
1020 __hsw_write(8)
1021 __hsw_write(16)
1022 __hsw_write(32)
1023 __hsw_write(64)
1024 __gen6_write(8)
1025 __gen6_write(16)
1026 __gen6_write(32)
1027 __gen6_write(64)
1028 __vgpu_write(8)
1029 __vgpu_write(16)
1030 __vgpu_write(32)
1031 __vgpu_write(64)
1032
1033 #undef __gen9_write
1034 #undef __chv_write
1035 #undef __gen8_write
1036 #undef __hsw_write
1037 #undef __gen6_write
1038 #undef __vgpu_write
1039 #undef GEN6_WRITE_FOOTER
1040 #undef GEN6_WRITE_HEADER
1041
1042 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1043 do { \
1044         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1045         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1046         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1047         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1048 } while (0)
1049
1050 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1051 do { \
1052         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1053         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1054         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1055         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1056 } while (0)
1057
1058
1059 static void fw_domain_init(struct drm_i915_private *dev_priv,
1060                            enum forcewake_domain_id domain_id,
1061                            u32 reg_set, u32 reg_ack)
1062 {
1063         struct intel_uncore_forcewake_domain *d;
1064
1065         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1066                 return;
1067
1068         d = &dev_priv->uncore.fw_domain[domain_id];
1069
1070         WARN_ON(d->wake_count);
1071
1072         d->wake_count = 0;
1073         d->reg_set = reg_set;
1074         d->reg_ack = reg_ack;
1075
1076         if (IS_GEN6(dev_priv)) {
1077                 d->val_reset = 0;
1078                 d->val_set = FORCEWAKE_KERNEL;
1079                 d->val_clear = 0;
1080         } else {
1081                 /* WaRsClearFWBitsAtReset:bdw,skl */
1082                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1083                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1084                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1085         }
1086
1087         if (IS_VALLEYVIEW(dev_priv))
1088                 d->reg_post = FORCEWAKE_ACK_VLV;
1089         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1090                 d->reg_post = ECOBUS;
1091         else
1092                 d->reg_post = 0;
1093
1094         d->i915 = dev_priv;
1095         d->id = domain_id;
1096
1097         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1098
1099         dev_priv->uncore.fw_domains |= (1 << domain_id);
1100
1101         fw_domain_reset(d);
1102 }
1103
1104 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1105 {
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107
1108         if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1109                 return;
1110
1111         if (IS_GEN9(dev)) {
1112                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1113                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1114                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1115                                FORCEWAKE_RENDER_GEN9,
1116                                FORCEWAKE_ACK_RENDER_GEN9);
1117                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1118                                FORCEWAKE_BLITTER_GEN9,
1119                                FORCEWAKE_ACK_BLITTER_GEN9);
1120                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1121                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1122         } else if (IS_VALLEYVIEW(dev)) {
1123                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1124                 if (!IS_CHERRYVIEW(dev))
1125                         dev_priv->uncore.funcs.force_wake_put =
1126                                 fw_domains_put_with_fifo;
1127                 else
1128                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1129                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1130                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1131                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1132                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1133         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1134                 dev_priv->uncore.funcs.force_wake_get =
1135                         fw_domains_get_with_thread_status;
1136                 if (IS_HASWELL(dev))
1137                         dev_priv->uncore.funcs.force_wake_put =
1138                                 fw_domains_put_with_fifo;
1139                 else
1140                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1141                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1142                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1143         } else if (IS_IVYBRIDGE(dev)) {
1144                 u32 ecobus;
1145
1146                 /* IVB configs may use multi-threaded forcewake */
1147
1148                 /* A small trick here - if the bios hasn't configured
1149                  * MT forcewake, and if the device is in RC6, then
1150                  * force_wake_mt_get will not wake the device and the
1151                  * ECOBUS read will return zero. Which will be
1152                  * (correctly) interpreted by the test below as MT
1153                  * forcewake being disabled.
1154                  */
1155                 dev_priv->uncore.funcs.force_wake_get =
1156                         fw_domains_get_with_thread_status;
1157                 dev_priv->uncore.funcs.force_wake_put =
1158                         fw_domains_put_with_fifo;
1159
1160                 /* We need to init first for ECOBUS access and then
1161                  * determine later if we want to reinit, in case of MT access is
1162                  * not working. In this stage we don't know which flavour this
1163                  * ivb is, so it is better to reset also the gen6 fw registers
1164                  * before the ecobus check.
1165                  */
1166
1167                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1168                 __raw_posting_read(dev_priv, ECOBUS);
1169
1170                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1171                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1172
1173                 mutex_lock(&dev->struct_mutex);
1174                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1175                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1176                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1177                 mutex_unlock(&dev->struct_mutex);
1178
1179                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1180                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1181                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1182                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1183                                        FORCEWAKE, FORCEWAKE_ACK);
1184                 }
1185         } else if (IS_GEN6(dev)) {
1186                 dev_priv->uncore.funcs.force_wake_get =
1187                         fw_domains_get_with_thread_status;
1188                 dev_priv->uncore.funcs.force_wake_put =
1189                         fw_domains_put_with_fifo;
1190                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1191                                FORCEWAKE, FORCEWAKE_ACK);
1192         }
1193
1194         /* All future platforms are expected to require complex power gating */
1195         WARN_ON(dev_priv->uncore.fw_domains == 0);
1196 }
1197
1198 void intel_uncore_init(struct drm_device *dev)
1199 {
1200         struct drm_i915_private *dev_priv = dev->dev_private;
1201
1202         i915_check_vgpu(dev);
1203
1204         intel_uncore_ellc_detect(dev);
1205         intel_uncore_fw_domains_init(dev);
1206         __intel_uncore_early_sanitize(dev, false);
1207
1208         switch (INTEL_INFO(dev)->gen) {
1209         default:
1210         case 9:
1211                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1212                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1213                 break;
1214         case 8:
1215                 if (IS_CHERRYVIEW(dev)) {
1216                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1217                         ASSIGN_READ_MMIO_VFUNCS(chv);
1218
1219                 } else {
1220                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1221                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1222                 }
1223                 break;
1224         case 7:
1225         case 6:
1226                 if (IS_HASWELL(dev)) {
1227                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1228                 } else {
1229                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1230                 }
1231
1232                 if (IS_VALLEYVIEW(dev)) {
1233                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1234                 } else {
1235                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1236                 }
1237                 break;
1238         case 5:
1239                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1240                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1241                 break;
1242         case 4:
1243         case 3:
1244         case 2:
1245                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1246                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1247                 break;
1248         }
1249
1250         if (intel_vgpu_active(dev)) {
1251                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1252                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1253         }
1254
1255         i915_check_and_clear_faults(dev);
1256 }
1257 #undef ASSIGN_WRITE_MMIO_VFUNCS
1258 #undef ASSIGN_READ_MMIO_VFUNCS
1259
1260 void intel_uncore_fini(struct drm_device *dev)
1261 {
1262         /* Paranoia: make sure we have disabled everything before we exit. */
1263         intel_uncore_sanitize(dev);
1264         intel_uncore_forcewake_reset(dev, false);
1265 }
1266
1267 #define GEN_RANGE(l, h) GENMASK(h, l)
1268
1269 static const struct register_whitelist {
1270         uint64_t offset;
1271         uint32_t size;
1272         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1273         uint32_t gen_bitmask;
1274 } whitelist[] = {
1275         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1276 };
1277
1278 int i915_reg_read_ioctl(struct drm_device *dev,
1279                         void *data, struct drm_file *file)
1280 {
1281         struct drm_i915_private *dev_priv = dev->dev_private;
1282         struct drm_i915_reg_read *reg = data;
1283         struct register_whitelist const *entry = whitelist;
1284         unsigned size;
1285         u64 offset;
1286         int i, ret = 0;
1287
1288         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1289                 if (entry->offset == (reg->offset & -entry->size) &&
1290                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1291                         break;
1292         }
1293
1294         if (i == ARRAY_SIZE(whitelist))
1295                 return -EINVAL;
1296
1297         /* We use the low bits to encode extra flags as the register should
1298          * be naturally aligned (and those that are not so aligned merely
1299          * limit the available flags for that register).
1300          */
1301         offset = entry->offset;
1302         size = entry->size;
1303         size |= reg->offset ^ offset;
1304
1305         intel_runtime_pm_get(dev_priv);
1306
1307         switch (size) {
1308         case 8 | 1:
1309                 reg->val = I915_READ64_2x32(offset, offset+4);
1310                 break;
1311         case 8:
1312                 reg->val = I915_READ64(offset);
1313                 break;
1314         case 4:
1315                 reg->val = I915_READ(offset);
1316                 break;
1317         case 2:
1318                 reg->val = I915_READ16(offset);
1319                 break;
1320         case 1:
1321                 reg->val = I915_READ8(offset);
1322                 break;
1323         default:
1324                 ret = -EINVAL;
1325                 goto out;
1326         }
1327
1328 out:
1329         intel_runtime_pm_put(dev_priv);
1330         return ret;
1331 }
1332
1333 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1334                                void *data, struct drm_file *file)
1335 {
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         struct drm_i915_reset_stats *args = data;
1338         struct i915_ctx_hang_stats *hs;
1339         struct intel_context *ctx;
1340         int ret;
1341
1342         if (args->flags || args->pad)
1343                 return -EINVAL;
1344
1345         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1346                 return -EPERM;
1347
1348         ret = mutex_lock_interruptible(&dev->struct_mutex);
1349         if (ret)
1350                 return ret;
1351
1352         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1353         if (IS_ERR(ctx)) {
1354                 mutex_unlock(&dev->struct_mutex);
1355                 return PTR_ERR(ctx);
1356         }
1357         hs = &ctx->hang_stats;
1358
1359         if (capable(CAP_SYS_ADMIN))
1360                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1361         else
1362                 args->reset_count = 0;
1363
1364         args->batch_active = hs->batch_active;
1365         args->batch_pending = hs->batch_pending;
1366
1367         mutex_unlock(&dev->struct_mutex);
1368
1369         return 0;
1370 }
1371
1372 static int i915_reset_complete(struct drm_device *dev)
1373 {
1374         u8 gdrst;
1375         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1376         return (gdrst & GRDOM_RESET_STATUS) == 0;
1377 }
1378
1379 static int i915_do_reset(struct drm_device *dev)
1380 {
1381         /* assert reset for at least 20 usec */
1382         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1383         udelay(20);
1384         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1385
1386         return wait_for(i915_reset_complete(dev), 500);
1387 }
1388
1389 static int g4x_reset_complete(struct drm_device *dev)
1390 {
1391         u8 gdrst;
1392         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1393         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1394 }
1395
1396 static int g33_do_reset(struct drm_device *dev)
1397 {
1398         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1399         return wait_for(g4x_reset_complete(dev), 500);
1400 }
1401
1402 static int g4x_do_reset(struct drm_device *dev)
1403 {
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int ret;
1406
1407         pci_write_config_byte(dev->pdev, I915_GDRST,
1408                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1409         ret =  wait_for(g4x_reset_complete(dev), 500);
1410         if (ret)
1411                 return ret;
1412
1413         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1414         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1415         POSTING_READ(VDECCLK_GATE_D);
1416
1417         pci_write_config_byte(dev->pdev, I915_GDRST,
1418                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1419         ret =  wait_for(g4x_reset_complete(dev), 500);
1420         if (ret)
1421                 return ret;
1422
1423         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1424         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1425         POSTING_READ(VDECCLK_GATE_D);
1426
1427         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1428
1429         return 0;
1430 }
1431
1432 static int ironlake_do_reset(struct drm_device *dev)
1433 {
1434         struct drm_i915_private *dev_priv = dev->dev_private;
1435         int ret;
1436
1437         I915_WRITE(ILK_GDSR,
1438                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1439         ret = wait_for((I915_READ(ILK_GDSR) &
1440                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1441         if (ret)
1442                 return ret;
1443
1444         I915_WRITE(ILK_GDSR,
1445                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1446         ret = wait_for((I915_READ(ILK_GDSR) &
1447                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1448         if (ret)
1449                 return ret;
1450
1451         I915_WRITE(ILK_GDSR, 0);
1452
1453         return 0;
1454 }
1455
1456 static int gen6_do_reset(struct drm_device *dev)
1457 {
1458         struct drm_i915_private *dev_priv = dev->dev_private;
1459         int     ret;
1460
1461         /* Reset the chip */
1462
1463         /* GEN6_GDRST is not in the gt power well, no need to check
1464          * for fifo space for the write or forcewake the chip for
1465          * the read
1466          */
1467         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1468
1469         /* Spin waiting for the device to ack the reset request */
1470         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1471
1472         intel_uncore_forcewake_reset(dev, true);
1473
1474         return ret;
1475 }
1476
1477 static int wait_for_register(struct drm_i915_private *dev_priv,
1478                              const u32 reg,
1479                              const u32 mask,
1480                              const u32 value,
1481                              const unsigned long timeout_ms)
1482 {
1483         return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1484 }
1485
1486 static int gen8_do_reset(struct drm_device *dev)
1487 {
1488         struct drm_i915_private *dev_priv = dev->dev_private;
1489         struct intel_engine_cs *engine;
1490         int i;
1491
1492         for_each_ring(engine, dev_priv, i) {
1493                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1494                            _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1495
1496                 if (wait_for_register(dev_priv,
1497                                       RING_RESET_CTL(engine->mmio_base),
1498                                       RESET_CTL_READY_TO_RESET,
1499                                       RESET_CTL_READY_TO_RESET,
1500                                       700)) {
1501                         DRM_ERROR("%s: reset request timeout\n", engine->name);
1502                         goto not_ready;
1503                 }
1504         }
1505
1506         return gen6_do_reset(dev);
1507
1508 not_ready:
1509         for_each_ring(engine, dev_priv, i)
1510                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1511                            _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1512
1513         return -EIO;
1514 }
1515
1516 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1517 {
1518         if (!i915.reset)
1519                 return NULL;
1520
1521         if (INTEL_INFO(dev)->gen >= 8)
1522                 return gen8_do_reset;
1523         else if (INTEL_INFO(dev)->gen >= 6)
1524                 return gen6_do_reset;
1525         else if (IS_GEN5(dev))
1526                 return ironlake_do_reset;
1527         else if (IS_G4X(dev))
1528                 return g4x_do_reset;
1529         else if (IS_G33(dev))
1530                 return g33_do_reset;
1531         else if (INTEL_INFO(dev)->gen >= 3)
1532                 return i915_do_reset;
1533         else
1534                 return NULL;
1535 }
1536
1537 int intel_gpu_reset(struct drm_device *dev)
1538 {
1539         struct drm_i915_private *dev_priv = to_i915(dev);
1540         int (*reset)(struct drm_device *);
1541         int ret;
1542
1543         reset = intel_get_gpu_reset(dev);
1544         if (reset == NULL)
1545                 return -ENODEV;
1546
1547         /* If the power well sleeps during the reset, the reset
1548          * request may be dropped and never completes (causing -EIO).
1549          */
1550         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1551         ret = reset(dev);
1552         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1553
1554         return ret;
1555 }
1556
1557 bool intel_has_gpu_reset(struct drm_device *dev)
1558 {
1559         return intel_get_gpu_reset(dev) != NULL;
1560 }
1561
1562 void intel_uncore_check_errors(struct drm_device *dev)
1563 {
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565
1566         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1567             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1568                 DRM_ERROR("Unclaimed register before interrupt\n");
1569                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1570         }
1571 }