2 * i.MX drm driver - LVDS display bridge
4 * Copyright (C) 2012 Sascha Hauer, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/module.h>
17 #include <linux/clk.h>
18 #include <linux/component.h>
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_fb_helper.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
28 #include <linux/of_device.h>
29 #include <linux/of_graph.h>
30 #include <video/of_display_timing.h>
31 #include <video/of_videomode.h>
32 #include <linux/regmap.h>
33 #include <linux/videodev2.h>
37 #define DRIVER_NAME "imx-ldb"
39 #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
40 #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
41 #define LDB_CH0_MODE_EN_MASK (3 << 0)
42 #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
43 #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
44 #define LDB_CH1_MODE_EN_MASK (3 << 2)
45 #define LDB_SPLIT_MODE_EN (1 << 4)
46 #define LDB_DATA_WIDTH_CH0_24 (1 << 5)
47 #define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
48 #define LDB_DATA_WIDTH_CH1_24 (1 << 7)
49 #define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
50 #define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
51 #define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
52 #define LDB_BGREF_RMODE_INT (1 << 15)
56 struct imx_ldb_channel {
58 struct drm_connector connector;
59 struct drm_encoder encoder;
61 /* Defines what is connected to the ldb, only one at a time */
62 struct drm_panel *panel;
63 struct drm_bridge *bridge;
65 struct device_node *child;
66 struct i2c_adapter *ddc;
70 struct drm_display_mode mode;
76 static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
78 return container_of(c, struct imx_ldb_channel, connector);
81 static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
83 return container_of(e, struct imx_ldb_channel, encoder);
93 struct regmap *regmap;
95 struct imx_ldb_channel channel[2];
96 struct clk *clk[2]; /* our own clock */
97 struct clk *clk_sel[4]; /* parent of display clock */
98 struct clk *clk_parent[4]; /* original parent of clk_sel */
99 struct clk *clk_pll[2]; /* upstream clock we can adjust */
101 const struct bus_mux *lvds_mux;
104 static enum drm_connector_status imx_ldb_connector_detect(
105 struct drm_connector *connector, bool force)
107 return connector_status_connected;
110 static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
113 struct imx_ldb *ldb = imx_ldb_ch->ldb;
114 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
116 switch (bus_format) {
117 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
119 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
120 if (imx_ldb_ch->chno == 0 || dual)
121 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
122 if (imx_ldb_ch->chno == 1 || dual)
123 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
125 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
126 if (imx_ldb_ch->chno == 0 || dual)
127 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
128 LDB_BIT_MAP_CH0_JEIDA;
129 if (imx_ldb_ch->chno == 1 || dual)
130 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
131 LDB_BIT_MAP_CH1_JEIDA;
136 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
138 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
141 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
142 imx_ldb_ch->panel->funcs->get_modes) {
143 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
148 if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
149 imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
151 if (imx_ldb_ch->edid) {
152 drm_mode_connector_update_edid_property(connector,
154 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
157 if (imx_ldb_ch->mode_valid) {
158 struct drm_display_mode *mode;
160 mode = drm_mode_create(connector->dev);
163 drm_mode_copy(mode, &imx_ldb_ch->mode);
164 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
165 drm_mode_probed_add(connector, mode);
172 static struct drm_encoder *imx_ldb_connector_best_encoder(
173 struct drm_connector *connector)
175 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
177 return &imx_ldb_ch->encoder;
180 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
181 unsigned long serial_clk, unsigned long di_clk)
185 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
186 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
187 clk_set_rate(ldb->clk_pll[chno], serial_clk);
189 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
190 clk_get_rate(ldb->clk_pll[chno]));
192 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
193 clk_get_rate(ldb->clk[chno]),
195 clk_set_rate(ldb->clk[chno], di_clk);
197 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
198 clk_get_rate(ldb->clk[chno]));
200 /* set display clock mux to LDB input clock */
201 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
204 "unable to set di%d parent clock to ldb_di%d\n", mux,
208 static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
210 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
211 struct imx_ldb *ldb = imx_ldb_ch->ldb;
212 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
213 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
215 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
216 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
220 drm_panel_prepare(imx_ldb_ch->panel);
223 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
224 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
226 clk_prepare_enable(ldb->clk[0]);
227 clk_prepare_enable(ldb->clk[1]);
229 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
232 if (imx_ldb_ch == &ldb->channel[0] || dual) {
233 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
234 if (mux == 0 || ldb->lvds_mux)
235 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
237 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
239 if (imx_ldb_ch == &ldb->channel[1] || dual) {
240 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
241 if (mux == 1 || ldb->lvds_mux)
242 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
244 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
248 const struct bus_mux *lvds_mux = NULL;
250 if (imx_ldb_ch == &ldb->channel[0])
251 lvds_mux = &ldb->lvds_mux[0];
252 else if (imx_ldb_ch == &ldb->channel[1])
253 lvds_mux = &ldb->lvds_mux[1];
255 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
256 mux << lvds_mux->shift);
259 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
261 drm_panel_enable(imx_ldb_ch->panel);
265 imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
266 struct drm_crtc_state *crtc_state,
267 struct drm_connector_state *connector_state)
269 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
270 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
271 struct imx_ldb *ldb = imx_ldb_ch->ldb;
272 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
273 unsigned long serial_clk;
274 unsigned long di_clk = mode->clock * 1000;
275 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
276 u32 bus_format = imx_ldb_ch->bus_format;
278 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
279 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
283 if (mode->clock > 170000) {
285 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
287 if (mode->clock > 85000 && !dual) {
289 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
293 serial_clk = 3500UL * mode->clock;
294 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
295 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
297 serial_clk = 7000UL * mode->clock;
298 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
302 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
303 if (imx_ldb_ch == &ldb->channel[0] || dual) {
304 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
305 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
306 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
307 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
309 if (imx_ldb_ch == &ldb->channel[1] || dual) {
310 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
311 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
312 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
313 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
317 struct drm_connector *connector = connector_state->connector;
318 struct drm_display_info *di = &connector->display_info;
320 if (di->num_bus_formats)
321 bus_format = di->bus_formats[0];
323 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
326 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
328 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
329 struct imx_ldb *ldb = imx_ldb_ch->ldb;
330 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
334 * imx_ldb_encoder_disable is called by
335 * drm_helper_disable_unused_functions without
336 * the encoder being enabled before.
338 if (imx_ldb_ch == &ldb->channel[0] &&
339 (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
341 else if (imx_ldb_ch == &ldb->channel[1] &&
342 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
345 drm_panel_disable(imx_ldb_ch->panel);
347 if (imx_ldb_ch == &ldb->channel[0] || dual)
348 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
349 if (imx_ldb_ch == &ldb->channel[1] || dual)
350 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
352 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
355 clk_disable_unprepare(ldb->clk[0]);
356 clk_disable_unprepare(ldb->clk[1]);
360 const struct bus_mux *lvds_mux = NULL;
362 if (imx_ldb_ch == &ldb->channel[0])
363 lvds_mux = &ldb->lvds_mux[0];
364 else if (imx_ldb_ch == &ldb->channel[1])
365 lvds_mux = &ldb->lvds_mux[1];
367 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
368 mux &= lvds_mux->mask;
369 mux >>= lvds_mux->shift;
371 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
374 /* set display clock mux back to original input clock */
375 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
378 "unable to set di%d parent clock to original parent\n",
381 drm_panel_unprepare(imx_ldb_ch->panel);
384 static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
385 struct drm_crtc_state *crtc_state,
386 struct drm_connector_state *conn_state)
388 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
389 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
390 struct drm_display_info *di = &conn_state->connector->display_info;
391 u32 bus_format = imx_ldb_ch->bus_format;
393 /* Bus format description in DT overrides connector display info. */
394 if (!bus_format && di->num_bus_formats) {
395 bus_format = di->bus_formats[0];
396 imx_crtc_state->bus_flags = di->bus_flags;
398 bus_format = imx_ldb_ch->bus_format;
399 imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
401 switch (bus_format) {
402 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
403 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
405 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
406 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
407 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
413 imx_crtc_state->di_hsync_pin = 2;
414 imx_crtc_state->di_vsync_pin = 3;
420 static const struct drm_connector_funcs imx_ldb_connector_funcs = {
421 .dpms = drm_atomic_helper_connector_dpms,
422 .fill_modes = drm_helper_probe_single_connector_modes,
423 .detect = imx_ldb_connector_detect,
424 .destroy = imx_drm_connector_destroy,
425 .reset = drm_atomic_helper_connector_reset,
426 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
427 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
430 static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
431 .get_modes = imx_ldb_connector_get_modes,
432 .best_encoder = imx_ldb_connector_best_encoder,
435 static const struct drm_encoder_funcs imx_ldb_encoder_funcs = {
436 .destroy = imx_drm_encoder_destroy,
439 static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
440 .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
441 .enable = imx_ldb_encoder_enable,
442 .disable = imx_ldb_encoder_disable,
443 .atomic_check = imx_ldb_encoder_atomic_check,
446 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
450 snprintf(clkname, sizeof(clkname), "di%d", chno);
451 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
452 if (IS_ERR(ldb->clk[chno]))
453 return PTR_ERR(ldb->clk[chno]);
455 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
456 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
458 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
461 static int imx_ldb_register(struct drm_device *drm,
462 struct imx_ldb_channel *imx_ldb_ch)
464 struct imx_ldb *ldb = imx_ldb_ch->ldb;
465 struct drm_encoder *encoder = &imx_ldb_ch->encoder;
468 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
472 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
476 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
477 ret = imx_ldb_get_clk(ldb, 1);
482 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
483 drm_encoder_init(drm, encoder, &imx_ldb_encoder_funcs,
484 DRM_MODE_ENCODER_LVDS, NULL);
486 if (imx_ldb_ch->bridge) {
487 imx_ldb_ch->bridge->encoder = encoder;
489 imx_ldb_ch->encoder.bridge = imx_ldb_ch->bridge;
490 ret = drm_bridge_attach(drm, imx_ldb_ch->bridge);
492 DRM_ERROR("Failed to initialize bridge with drm\n");
497 * We want to add the connector whenever there is no bridge
498 * that brings its own, not only when there is a panel. For
499 * historical reasons, the ldb driver can also work without
502 drm_connector_helper_add(&imx_ldb_ch->connector,
503 &imx_ldb_connector_helper_funcs);
504 drm_connector_init(drm, &imx_ldb_ch->connector,
505 &imx_ldb_connector_funcs,
506 DRM_MODE_CONNECTOR_LVDS);
507 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
511 if (imx_ldb_ch->panel) {
512 ret = drm_panel_attach(imx_ldb_ch->panel,
513 &imx_ldb_ch->connector);
526 struct imx_ldb_bit_mapping {
529 const char * const mapping;
532 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
533 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
534 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
535 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
538 static u32 of_get_bus_format(struct device *dev, struct device_node *np)
544 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
548 of_property_read_u32(np, "fsl,data-width", &datawidth);
550 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
551 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
552 datawidth == imx_ldb_bit_mappings[i].datawidth)
553 return imx_ldb_bit_mappings[i].bus_format;
556 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
561 static struct bus_mux imx6q_lvds_mux[2] = {
565 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
569 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
574 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
575 * of_match_device will walk through this list and take the first entry
576 * matching any of its compatible values. Therefore, the more generic
577 * entries (in this case fsl,imx53-ldb) need to be ordered last.
579 static const struct of_device_id imx_ldb_dt_ids[] = {
580 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
581 { .compatible = "fsl,imx53-ldb", .data = NULL, },
584 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
586 static int imx_ldb_panel_ddc(struct device *dev,
587 struct imx_ldb_channel *channel, struct device_node *child)
589 struct device_node *ddc_node;
593 ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
595 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
596 of_node_put(ddc_node);
598 dev_warn(dev, "failed to get ddc i2c adapter\n");
599 return -EPROBE_DEFER;
604 /* if no DDC available, fallback to hardcoded EDID */
605 dev_dbg(dev, "no ddc available\n");
607 edidp = of_get_property(child, "edid",
610 channel->edid = kmemdup(edidp,
613 } else if (!channel->panel) {
614 /* fallback to display-timings node */
615 ret = of_get_drm_display_mode(child,
620 channel->mode_valid = 1;
626 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
628 struct drm_device *drm = data;
629 struct device_node *np = dev->of_node;
630 const struct of_device_id *of_id =
631 of_match_device(imx_ldb_dt_ids, dev);
632 struct device_node *child;
633 struct imx_ldb *imx_ldb;
638 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
642 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
643 if (IS_ERR(imx_ldb->regmap)) {
644 dev_err(dev, "failed to get parent regmap\n");
645 return PTR_ERR(imx_ldb->regmap);
648 /* disable LDB by resetting the control register to POR default */
649 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
654 imx_ldb->lvds_mux = of_id->data;
656 dual = of_property_read_bool(np, "fsl,dual-channel");
658 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
661 * There are three different possible clock mux configurations:
662 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
663 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
664 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
665 * Map them all to di0_sel...di3_sel.
667 for (i = 0; i < 4; i++) {
670 sprintf(clkname, "di%d_sel", i);
671 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
672 if (IS_ERR(imx_ldb->clk_sel[i])) {
673 ret = PTR_ERR(imx_ldb->clk_sel[i]);
674 imx_ldb->clk_sel[i] = NULL;
678 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
683 for_each_child_of_node(np, child) {
684 struct imx_ldb_channel *channel;
685 struct device_node *ep;
688 ret = of_property_read_u32(child, "reg", &i);
689 if (ret || i < 0 || i > 1)
692 if (!of_device_is_available(child))
696 dev_warn(dev, "dual-channel mode, ignoring second output\n");
700 channel = &imx_ldb->channel[i];
701 channel->ldb = imx_ldb;
703 channel->child = child;
706 * The output port is port@4 with an external 4-port mux or
707 * port@2 with the internal 2-port mux.
709 ep = of_graph_get_endpoint_by_regs(child,
710 imx_ldb->lvds_mux ? 4 : 2,
713 struct device_node *remote;
715 remote = of_graph_get_remote_port_parent(ep);
718 channel->panel = of_drm_find_panel(remote);
719 channel->bridge = of_drm_find_bridge(remote);
721 return -EPROBE_DEFER;
724 if (!channel->panel && !channel->bridge) {
725 dev_err(dev, "panel/bridge not found: %s\n",
727 return -EPROBE_DEFER;
731 /* panel ddc only if there is no bridge */
732 if (!channel->bridge) {
733 ret = imx_ldb_panel_ddc(dev, channel, child);
738 bus_format = of_get_bus_format(dev, child);
739 if (bus_format == -EINVAL) {
741 * If no bus format was specified in the device tree,
742 * we can still get it from the connected panel later.
744 if (channel->panel && channel->panel->funcs &&
745 channel->panel->funcs->get_modes)
748 if (bus_format < 0) {
749 dev_err(dev, "could not determine data mapping: %d\n",
753 channel->bus_format = bus_format;
755 ret = imx_ldb_register(drm, channel);
760 dev_set_drvdata(dev, imx_ldb);
765 static void imx_ldb_unbind(struct device *dev, struct device *master,
768 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
771 for (i = 0; i < 2; i++) {
772 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
775 drm_bridge_detach(channel->bridge);
777 drm_panel_detach(channel->panel);
779 kfree(channel->edid);
780 i2c_put_adapter(channel->ddc);
784 static const struct component_ops imx_ldb_ops = {
785 .bind = imx_ldb_bind,
786 .unbind = imx_ldb_unbind,
789 static int imx_ldb_probe(struct platform_device *pdev)
791 return component_add(&pdev->dev, &imx_ldb_ops);
794 static int imx_ldb_remove(struct platform_device *pdev)
796 component_del(&pdev->dev, &imx_ldb_ops);
800 static struct platform_driver imx_ldb_driver = {
801 .probe = imx_ldb_probe,
802 .remove = imx_ldb_remove,
804 .of_match_table = imx_ldb_dt_ids,
809 module_platform_driver(imx_ldb_driver);
811 MODULE_DESCRIPTION("i.MX LVDS driver");
812 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
813 MODULE_LICENSE("GPL");
814 MODULE_ALIAS("platform:" DRIVER_NAME);