drivers/gpu/drm/mediatek/mtk_drm_crtc.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <asm/barrier.h>
  15 #include <drm/drmP.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <drm/drm_plane_helper.h>
  19 #include <linux/clk.h>
  20 #include <linux/pm_runtime.h>
  21 #include <soc/mediatek/smi.h>
  22
  23 #include "mtk_drm_drv.h"
  24 #include "mtk_drm_crtc.h"
  25 #include "mtk_drm_ddp.h"
  26 #include "mtk_drm_ddp_comp.h"
  27 #include "mtk_drm_gem.h"
  28 #include "mtk_drm_plane.h"
  29
  30 /**
  31  * struct mtk_drm_crtc - MediaTek specific crtc structure.
  32  * @base: crtc object.
  33  * @enabled: records whether crtc_enable succeeded
  34  * @planes: array of 4 drm_plane structures, one for each overlay plane
  35  * @pending_planes: whether any plane has pending changes to be applied
  36  * @config_regs: memory mapped mmsys configuration register space
  37  * @mutex: handle to one of the ten disp_mutex streams
  38  * @ddp_comp_nr: number of components in ddp_comp
  39  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
  40  */
  41 struct mtk_drm_crtc {
  42         struct drm_crtc                 base;
  43         bool                            enabled;
  44
  45         bool                            pending_needs_vblank;
  46         struct drm_pending_vblank_event *event;
  47
  48         struct drm_plane                planes[OVL_LAYER_NR];
  49         bool                            pending_planes;
  50
  51         void __iomem                    *config_regs;
  52         struct mtk_disp_mutex           *mutex;
  53         unsigned int                    ddp_comp_nr;
  54         struct mtk_ddp_comp             **ddp_comp;
  55 };
  56
  57 struct mtk_crtc_state {
  58         struct drm_crtc_state           base;
  59
  60         bool                            pending_config;
  61         unsigned int                    pending_width;
  62         unsigned int                    pending_height;
  63         unsigned int                    pending_vrefresh;
  64 };
  65
  66 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
  67 {
  68         return container_of(c, struct mtk_drm_crtc, base);
  69 }
  70
  71 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
  72 {
  73         return container_of(s, struct mtk_crtc_state, base);
  74 }
  75
  76 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  77 {
  78         struct drm_crtc *crtc = &mtk_crtc->base;
  79         unsigned long flags;
  80
  81         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  82         drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
  83         drm_crtc_vblank_put(crtc);
  84         mtk_crtc->event = NULL;
  85         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  86 }
  87
  88 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  89 {
  90         drm_crtc_handle_vblank(&mtk_crtc->base);
  91         if (mtk_crtc->pending_needs_vblank) {
  92                 mtk_drm_crtc_finish_page_flip(mtk_crtc);
  93                 mtk_crtc->pending_needs_vblank = false;
  94         }
  95 }
  96
  97 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
  98 {
  99         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 100         int i;
 101
 102         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 103                 clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
 104
 105         mtk_disp_mutex_put(mtk_crtc->mutex);
 106
 107         drm_crtc_cleanup(crtc);
 108 }
 109
 110 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
 111 {
 112         struct mtk_crtc_state *state;
 113
 114         if (crtc->state) {
 115                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 116
 117                 state = to_mtk_crtc_state(crtc->state);
 118                 memset(state, 0, sizeof(*state));
 119         } else {
 120                 state = kzalloc(sizeof(*state), GFP_KERNEL);
 121                 if (!state)
 122                         return;
 123                 crtc->state = &state->base;
 124         }
 125
 126         state->base.crtc = crtc;
 127 }
 128
 129 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
 130 {
 131         struct mtk_crtc_state *state;
 132
 133         state = kzalloc(sizeof(*state), GFP_KERNEL);
 134         if (!state)
 135                 return NULL;
 136
 137         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 138
 139         WARN_ON(state->base.crtc != crtc);
 140         state->base.crtc = crtc;
 141
 142         return &state->base;
 143 }
 144
 145 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
 146                                        struct drm_crtc_state *state)
 147 {
 148         __drm_atomic_helper_crtc_destroy_state(state);
 149         kfree(to_mtk_crtc_state(state));
 150 }
 151
 152 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 153                                     const struct drm_display_mode *mode,
 154                                     struct drm_display_mode *adjusted_mode)
 155 {
 156         /* Nothing to do here, but this callback is mandatory. */
 157         return true;
 158 }
 159
 160 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 161 {
 162         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 163
 164         state->pending_width = crtc->mode.hdisplay;
 165         state->pending_height = crtc->mode.vdisplay;
 166         state->pending_vrefresh = crtc->mode.vrefresh;
 167         wmb();  /* Make sure the above parameters are set before update */
 168         state->pending_config = true;
 169 }
 170
 171 int mtk_drm_crtc_enable_vblank(struct drm_device *drm, unsigned int pipe)
 172 {
 173         struct mtk_drm_private *priv = drm->dev_private;
 174         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(priv->crtc[pipe]);
 175         struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
 176
 177         mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base);
 178
 179         return 0;
 180 }
 181
 182 void mtk_drm_crtc_disable_vblank(struct drm_device *drm, unsigned int pipe)
 183 {
 184         struct mtk_drm_private *priv = drm->dev_private;
 185         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(priv->crtc[pipe]);
 186         struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
 187
 188         mtk_ddp_comp_disable_vblank(ovl);
 189 }
 190
 191 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
 192 {
 193         int ret;
 194         int i;
 195
 196         DRM_DEBUG_DRIVER("%s\n", __func__);
 197         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 198                 ret = clk_enable(mtk_crtc->ddp_comp[i]->clk);
 199                 if (ret) {
 200                         DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 201                         goto err;
 202                 }
 203         }
 204
 205         return 0;
 206 err:
 207         while (--i >= 0)
 208                 clk_disable(mtk_crtc->ddp_comp[i]->clk);
 209         return ret;
 210 }
 211
 212 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
 213 {
 214         int i;
 215
 216         DRM_DEBUG_DRIVER("%s\n", __func__);
 217         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 218                 clk_disable(mtk_crtc->ddp_comp[i]->clk);
 219 }
 220
 221 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 222 {
 223         struct drm_crtc *crtc = &mtk_crtc->base;
 224         struct drm_connector *connector;
 225         struct drm_encoder *encoder;
 226         unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 227         int ret;
 228         int i;
 229
 230         DRM_DEBUG_DRIVER("%s\n", __func__);
 231         if (WARN_ON(!crtc->state))
 232                 return -EINVAL;
 233
 234         width = crtc->state->adjusted_mode.hdisplay;
 235         height = crtc->state->adjusted_mode.vdisplay;
 236         vrefresh = crtc->state->adjusted_mode.vrefresh;
 237
 238         drm_for_each_encoder(encoder, crtc->dev) {
 239                 if (encoder->crtc != crtc)
 240                         continue;
 241
 242                 drm_for_each_connector(connector, crtc->dev) {
 243                         if (connector->encoder != encoder)
 244                                 continue;
 245                         if (connector->display_info.bpc != 0 &&
 246                             bpc > connector->display_info.bpc)
 247                                 bpc = connector->display_info.bpc;
 248                 }
 249         }
 250
 251         ret = pm_runtime_get_sync(crtc->dev->dev);
 252         if (ret < 0) {
 253                 DRM_ERROR("Failed to enable power domain: %d\n", ret);
 254                 return ret;
 255         }
 256
 257         ret = mtk_disp_mutex_prepare(mtk_crtc->mutex);
 258         if (ret < 0) {
 259                 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
 260                 goto err_pm_runtime_put;
 261         }
 262
 263         ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
 264         if (ret < 0) {
 265                 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
 266                 goto err_mutex_unprepare;
 267         }
 268
 269         DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
 270         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 271                 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
 272                                          mtk_crtc->ddp_comp[i]->id,
 273                                          mtk_crtc->ddp_comp[i + 1]->id);
 274                 mtk_disp_mutex_add_comp(mtk_crtc->mutex,
 275                                         mtk_crtc->ddp_comp[i]->id);
 276         }
 277         mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 278         mtk_disp_mutex_enable(mtk_crtc->mutex);
 279
 280         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 281                 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
 282
 283                 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
 284                 mtk_ddp_comp_start(comp);
 285         }
 286
 287         /* Initially configure all planes */
 288         for (i = 0; i < OVL_LAYER_NR; i++) {
 289                 struct drm_plane *plane = &mtk_crtc->planes[i];
 290                 struct mtk_plane_state *plane_state;
 291
 292                 plane_state = to_mtk_plane_state(plane->state);
 293                 mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i,
 294                                           plane_state);
 295         }
 296
 297         return 0;
 298
 299 err_mutex_unprepare:
 300         mtk_disp_mutex_unprepare(mtk_crtc->mutex);
 301 err_pm_runtime_put:
 302         pm_runtime_put(crtc->dev->dev);
 303         return ret;
 304 }
 305
 306 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
 307 {
 308         struct drm_device *drm = mtk_crtc->base.dev;
 309         struct drm_crtc *crtc = &mtk_crtc->base;
 310         int i;
 311
 312         DRM_DEBUG_DRIVER("%s\n", __func__);
 313         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 314                 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
 315         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 316                 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
 317                                            mtk_crtc->ddp_comp[i]->id);
 318         mtk_disp_mutex_disable(mtk_crtc->mutex);
 319         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 320                 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
 321                                               mtk_crtc->ddp_comp[i]->id,
 322                                               mtk_crtc->ddp_comp[i + 1]->id);
 323                 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
 324                                            mtk_crtc->ddp_comp[i]->id);
 325         }
 326         mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 327         mtk_crtc_ddp_clk_disable(mtk_crtc);
 328         mtk_disp_mutex_unprepare(mtk_crtc->mutex);
 329
 330         pm_runtime_put(drm->dev);
 331
 332         if (crtc->state->event && !crtc->state->active) {
 333                 spin_lock_irq(&crtc->dev->event_lock);
 334                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 335                 crtc->state->event = NULL;
 336                 spin_unlock_irq(&crtc->dev->event_lock);
 337         }
 338 }
 339
 340 static void mtk_drm_crtc_enable(struct drm_crtc *crtc)
 341 {
 342         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 343         struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
 344         int ret;
 345
 346         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 347
 348         ret = mtk_smi_larb_get(ovl->larb_dev);
 349         if (ret) {
 350                 DRM_ERROR("Failed to get larb: %d\n", ret);
 351                 return;
 352         }
 353
 354         ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 355         if (ret) {
 356                 mtk_smi_larb_put(ovl->larb_dev);
 357                 return;
 358         }
 359
 360         drm_crtc_vblank_on(crtc);
 361         mtk_crtc->enabled = true;
 362 }
 363
 364 static void mtk_drm_crtc_disable(struct drm_crtc *crtc)
 365 {
 366         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 367         struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
 368         int i;
 369
 370         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 371         if (!mtk_crtc->enabled)
 372                 return;
 373
 374         /* Set all pending plane state to disabled */
 375         for (i = 0; i < OVL_LAYER_NR; i++) {
 376                 struct drm_plane *plane = &mtk_crtc->planes[i];
 377                 struct mtk_plane_state *plane_state;
 378
 379                 plane_state = to_mtk_plane_state(plane->state);
 380                 plane_state->pending.enable = false;
 381                 plane_state->pending.config = true;
 382         }
 383         mtk_crtc->pending_planes = true;
 384
 385         /* Wait for planes to be disabled */
 386         drm_crtc_wait_one_vblank(crtc);
 387
 388         drm_crtc_vblank_off(crtc);
 389         mtk_crtc_ddp_hw_fini(mtk_crtc);
 390         mtk_smi_larb_put(ovl->larb_dev);
 391
 392         mtk_crtc->enabled = false;
 393 }
 394
 395 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 396                                       struct drm_crtc_state *old_crtc_state)
 397 {
 398         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 399         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 400
 401         if (mtk_crtc->event && state->base.event)
 402                 DRM_ERROR("new event while there is still a pending event\n");
 403
 404         if (state->base.event) {
 405                 state->base.event->pipe = drm_crtc_index(crtc);
 406                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 407                 mtk_crtc->event = state->base.event;
 408                 state->base.event = NULL;
 409         }
 410 }
 411
 412 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 413                                       struct drm_crtc_state *old_crtc_state)
 414 {
 415         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 416         unsigned int pending_planes = 0;
 417         int i;
 418
 419         if (mtk_crtc->event)
 420                 mtk_crtc->pending_needs_vblank = true;
 421         for (i = 0; i < OVL_LAYER_NR; i++) {
 422                 struct drm_plane *plane = &mtk_crtc->planes[i];
 423                 struct mtk_plane_state *plane_state;
 424
 425                 plane_state = to_mtk_plane_state(plane->state);
 426                 if (plane_state->pending.dirty) {
 427                         plane_state->pending.config = true;
 428                         plane_state->pending.dirty = false;
 429                         pending_planes |= BIT(i);
 430                 }
 431         }
 432         if (pending_planes)
 433                 mtk_crtc->pending_planes = true;
 434         if (crtc->state->color_mgmt_changed)
 435                 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 436                         mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
 437 }
 438
 439 static const struct drm_crtc_funcs mtk_crtc_funcs = {
 440         .set_config             = drm_atomic_helper_set_config,
 441         .page_flip              = drm_atomic_helper_page_flip,
 442         .destroy                = mtk_drm_crtc_destroy,
 443         .reset                  = mtk_drm_crtc_reset,
 444         .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
 445         .atomic_destroy_state   = mtk_drm_crtc_destroy_state,
 446         .gamma_set              = drm_atomic_helper_legacy_gamma_set,
 447 };
 448
 449 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
 450         .mode_fixup     = mtk_drm_crtc_mode_fixup,
 451         .mode_set_nofb  = mtk_drm_crtc_mode_set_nofb,
 452         .enable         = mtk_drm_crtc_enable,
 453         .disable        = mtk_drm_crtc_disable,
 454         .atomic_begin   = mtk_drm_crtc_atomic_begin,
 455         .atomic_flush   = mtk_drm_crtc_atomic_flush,
 456 };
 457
 458 static int mtk_drm_crtc_init(struct drm_device *drm,
 459                              struct mtk_drm_crtc *mtk_crtc,
 460                              struct drm_plane *primary,
 461                              struct drm_plane *cursor, unsigned int pipe)
 462 {
 463         int ret;
 464
 465         ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 466                                         &mtk_crtc_funcs, NULL);
 467         if (ret)
 468                 goto err_cleanup_crtc;
 469
 470         drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
 471
 472         return 0;
 473
 474 err_cleanup_crtc:
 475         drm_crtc_cleanup(&mtk_crtc->base);
 476         return ret;
 477 }
 478
 479 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
 480 {
 481         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 482         struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
 483         unsigned int i;
 484
 485         /*
 486          * TODO: instead of updating the registers here, we should prepare
 487          * working registers in atomic_commit and let the hardware command
 488          * queue update module registers on vblank.
 489          */
 490         if (state->pending_config) {
 491                 mtk_ddp_comp_config(ovl, state->pending_width,
 492                                     state->pending_height,
 493                                     state->pending_vrefresh, 0);
 494
 495                 state->pending_config = false;
 496         }
 497
 498         if (mtk_crtc->pending_planes) {
 499                 for (i = 0; i < OVL_LAYER_NR; i++) {
 500                         struct drm_plane *plane = &mtk_crtc->planes[i];
 501                         struct mtk_plane_state *plane_state;
 502
 503                         plane_state = to_mtk_plane_state(plane->state);
 504
 505                         if (plane_state->pending.config) {
 506                                 mtk_ddp_comp_layer_config(ovl, i, plane_state);
 507                                 plane_state->pending.config = false;
 508                         }
 509                 }
 510                 mtk_crtc->pending_planes = false;
 511         }
 512
 513         mtk_drm_finish_page_flip(mtk_crtc);
 514 }
 515
 516 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 517                         const enum mtk_ddp_comp_id *path, unsigned int path_len)
 518 {
 519         struct mtk_drm_private *priv = drm_dev->dev_private;
 520         struct device *dev = drm_dev->dev;
 521         struct mtk_drm_crtc *mtk_crtc;
 522         enum drm_plane_type type;
 523         unsigned int zpos;
 524         int pipe = priv->num_pipes;
 525         int ret;
 526         int i;
 527
 528         for (i = 0; i < path_len; i++) {
 529                 enum mtk_ddp_comp_id comp_id = path[i];
 530                 struct device_node *node;
 531
 532                 node = priv->comp_node[comp_id];
 533                 if (!node) {
 534                         dev_info(dev,
 535                                  "Not creating crtc %d because component %d is disabled or missing\n",
 536                                  pipe, comp_id);
 537                         return 0;
 538                 }
 539         }
 540
 541         mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
 542         if (!mtk_crtc)
 543                 return -ENOMEM;
 544
 545         mtk_crtc->config_regs = priv->config_regs;
 546         mtk_crtc->ddp_comp_nr = path_len;
 547         mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
 548                                                 sizeof(*mtk_crtc->ddp_comp),
 549                                                 GFP_KERNEL);
 550
 551         mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe);
 552         if (IS_ERR(mtk_crtc->mutex)) {
 553                 ret = PTR_ERR(mtk_crtc->mutex);
 554                 dev_err(dev, "Failed to get mutex: %d\n", ret);
 555                 return ret;
 556         }
 557
 558         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 559                 enum mtk_ddp_comp_id comp_id = path[i];
 560                 struct mtk_ddp_comp *comp;
 561                 struct device_node *node;
 562
 563                 node = priv->comp_node[comp_id];
 564                 comp = priv->ddp_comp[comp_id];
 565                 if (!comp) {
 566                         dev_err(dev, "Component %s not initialized\n",
 567                                 node->full_name);
 568                         ret = -ENODEV;
 569                         goto unprepare;
 570                 }
 571
 572                 ret = clk_prepare(comp->clk);
 573                 if (ret) {
 574                         dev_err(dev,
 575                                 "Failed to prepare clock for component %s: %d\n",
 576                                 node->full_name, ret);
 577                         goto unprepare;
 578                 }
 579
 580                 mtk_crtc->ddp_comp[i] = comp;
 581         }
 582
 583         for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) {
 584                 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
 585                                 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
 586                                                 DRM_PLANE_TYPE_OVERLAY;
 587                 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
 588                                      BIT(pipe), type);
 589                 if (ret)
 590                         goto unprepare;
 591         }
 592
 593         ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
 594                                 &mtk_crtc->planes[1], pipe);
 595         if (ret < 0)
 596                 goto unprepare;
 597         drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
 598         drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
 599         priv->crtc[pipe] = &mtk_crtc->base;
 600         priv->num_pipes++;
 601
 602         return 0;
 603
 604 unprepare:
 605         while (--i >= 0)
 606                 clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
 607
 608         return ret;
 609 }