2 * Copyright (C) 2016 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include "meson_drv.h"
24 #include "meson_venc.h"
25 #include "meson_vpp.h"
26 #include "meson_vclk.h"
27 #include "meson_registers.h"
32 * VENC Handle the pixels encoding to the output formats.
33 * We handle the following encodings :
35 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
36 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
37 * - Setup of more clock rates for HDMI modes
41 * - LCD Panel encoding via ENCL
42 * - TV Panel encoding via ENCT
48 * _____ _____ ____________________
49 * vd1---| |-| | | VENC /---------|----VDAC
50 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
51 * osd1--| |-| | | \ | X--HDMI-TX
52 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
54 * | \--ENCL-----------|----LVDS
55 * |____________________|
57 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
58 * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI.
59 * The ENCP is designed for Progressive encoding but can also generate
60 * 1080i interlaced pixels, and was initialy desined to encode pixels for
61 * VDAC to output RGB ou YUV analog outputs.
62 * It's output is only used through the ENCP_DVI encoder for HDMI.
63 * The ENCL LVDS encoder is not implemented.
65 * The ENCI and ENCP encoders needs specially defined parameters for each
66 * supported mode and thus cannot be determined from standard video timings.
68 * The ENCI end ENCP DVI encoders are more generic and can generate any timings
69 * from the pixel data generated by ENCI or ENCP, so can use the standard video
70 * timings are source for HW parameters.
74 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
75 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
76 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
77 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
79 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
80 .mode_tag = MESON_VENC_MODE_CVBS_PAL,
86 .video_prog_mode = 0xff,
92 .top_field_line_start = 22,
93 .top_field_line_end = 310,
94 .bottom_field_line_start = 23,
95 .bottom_field_line_end = 311,
96 .video_saturation = 9,
98 .video_brightness = 0,
100 .analog_sync_adj = 0x8080,
103 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
104 .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
110 .video_prog_mode = 0xf0,
116 .top_field_line_start = 18,
117 .top_field_line_end = 258,
118 .bottom_field_line_start = 19,
119 .bottom_field_line_end = 259,
120 .video_saturation = 18,
122 .video_brightness = 0,
124 .analog_sync_adj = 0x9c00,
127 union meson_hdmi_venc_mode {
129 unsigned int mode_tag;
130 unsigned int hso_begin;
131 unsigned int hso_end;
132 unsigned int vso_even;
133 unsigned int vso_odd;
134 unsigned int macv_max_amp;
135 unsigned int video_prog_mode;
136 unsigned int video_mode;
137 unsigned int sch_adjust;
138 unsigned int yc_delay;
139 unsigned int pixel_start;
140 unsigned int pixel_end;
141 unsigned int top_field_line_start;
142 unsigned int top_field_line_end;
143 unsigned int bottom_field_line_start;
144 unsigned int bottom_field_line_end;
147 unsigned int dvi_settings;
148 unsigned int video_mode;
149 unsigned int video_mode_adv;
150 unsigned int video_prog_mode;
151 bool video_prog_mode_present;
152 unsigned int video_sync_mode;
153 bool video_sync_mode_present;
154 unsigned int video_yc_dly;
155 bool video_yc_dly_present;
156 unsigned int video_rgb_ctrl;
157 bool video_rgb_ctrl_present;
158 unsigned int video_filt_ctrl;
159 bool video_filt_ctrl_present;
160 unsigned int video_ofld_voav_ofst;
161 bool video_ofld_voav_ofst_present;
162 unsigned int yfp1_htime;
163 unsigned int yfp2_htime;
164 unsigned int max_pxcnt;
165 unsigned int hspuls_begin;
166 unsigned int hspuls_end;
167 unsigned int hspuls_switch;
168 unsigned int vspuls_begin;
169 unsigned int vspuls_end;
170 unsigned int vspuls_bline;
171 unsigned int vspuls_eline;
172 unsigned int eqpuls_begin;
173 bool eqpuls_begin_present;
174 unsigned int eqpuls_end;
175 bool eqpuls_end_present;
176 unsigned int eqpuls_bline;
177 bool eqpuls_bline_present;
178 unsigned int eqpuls_eline;
179 bool eqpuls_eline_present;
180 unsigned int havon_begin;
181 unsigned int havon_end;
182 unsigned int vavon_bline;
183 unsigned int vavon_eline;
184 unsigned int hso_begin;
185 unsigned int hso_end;
186 unsigned int vso_begin;
187 unsigned int vso_end;
188 unsigned int vso_bline;
189 unsigned int vso_eline;
190 bool vso_eline_present;
193 unsigned int sy2_val;
194 bool sy2_val_present;
195 unsigned int max_lncnt;
199 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
205 .macv_max_amp = 0x810b,
206 .video_prog_mode = 0xf0,
212 .top_field_line_start = 18,
213 .top_field_line_end = 258,
214 .bottom_field_line_start = 19,
215 .bottom_field_line_end = 259,
219 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
225 .macv_max_amp = 8107,
226 .video_prog_mode = 0xff,
232 .top_field_line_start = 22,
233 .top_field_line_end = 310,
234 .bottom_field_line_start = 23,
235 .bottom_field_line_end = 311,
239 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
241 .dvi_settings = 0x21,
242 .video_mode = 0x4000,
243 .video_mode_adv = 0x9,
244 .video_prog_mode = 0,
245 .video_prog_mode_present = true,
246 .video_sync_mode = 7,
247 .video_sync_mode_present = true,
250 .video_filt_ctrl = 0x2052,
251 .video_filt_ctrl_present = true,
252 /* video_ofld_voav_ofst */
256 .hspuls_begin = 0x22,
278 .sy_val_present = true,
280 .sy2_val_present = true,
285 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
287 .dvi_settings = 0x21,
288 .video_mode = 0x4000,
289 .video_mode_adv = 0x9,
290 .video_prog_mode = 0,
291 .video_prog_mode_present = true,
292 .video_sync_mode = 7,
293 .video_sync_mode_present = true,
296 .video_filt_ctrl = 0x52,
297 .video_filt_ctrl_present = true,
298 /* video_ofld_voav_ofst */
324 .sy_val_present = true,
326 .sy2_val_present = true,
331 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
333 .dvi_settings = 0x2029,
334 .video_mode = 0x4040,
335 .video_mode_adv = 0x19,
336 /* video_prog_mode */
337 /* video_sync_mode */
340 /* video_filt_ctrl */
341 /* video_ofld_voav_ofst */
366 .vso_eline_present = true,
373 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
375 .dvi_settings = 0x202d,
376 .video_mode = 0x4040,
377 .video_mode_adv = 0x19,
378 .video_prog_mode = 0x100,
379 .video_prog_mode_present = true,
380 .video_sync_mode = 0x407,
381 .video_sync_mode_present = true,
383 .video_yc_dly_present = true,
385 /* video_filt_ctrl */
386 /* video_ofld_voav_ofst */
411 .vso_eline_present = true,
418 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
420 .dvi_settings = 0x2029,
421 .video_mode = 0x5ffc,
422 .video_mode_adv = 0x19,
423 .video_prog_mode = 0x100,
424 .video_prog_mode_present = true,
425 .video_sync_mode = 0x207,
426 .video_sync_mode_present = true,
429 /* video_filt_ctrl */
430 .video_ofld_voav_ofst = 0x11,
431 .video_ofld_voav_ofst_present = true,
446 .eqpuls_begin = 2288,
447 .eqpuls_begin_present = true,
449 .eqpuls_end_present = true,
451 .eqpuls_bline_present = true,
453 .eqpuls_eline_present = true,
460 .vso_eline_present = true,
467 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
469 .dvi_settings = 0x202d,
470 .video_mode = 0x5ffc,
471 .video_mode_adv = 0x19,
472 .video_prog_mode = 0x100,
473 .video_prog_mode_present = true,
474 .video_sync_mode = 0x7,
475 .video_sync_mode_present = true,
478 /* video_filt_ctrl */
479 .video_ofld_voav_ofst = 0x11,
480 .video_ofld_voav_ofst_present = true,
495 .eqpuls_begin = 2288,
496 .eqpuls_begin_present = true,
498 .eqpuls_end_present = true,
500 .eqpuls_bline_present = true,
502 .eqpuls_eline_present = true,
509 .vso_eline_present = true,
516 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
519 .video_mode = 0x4040,
520 .video_mode_adv = 0x18,
521 .video_prog_mode = 0x100,
522 .video_prog_mode_present = true,
523 .video_sync_mode = 0x7,
524 .video_sync_mode_present = true,
526 .video_yc_dly_present = true,
528 .video_rgb_ctrl_present = true,
529 .video_filt_ctrl = 0x1052,
530 .video_filt_ctrl_present = true,
531 /* video_ofld_voav_ofst */
549 .eqpuls_bline_present = true,
551 .eqpuls_eline_present = true,
558 .vso_eline_present = true,
565 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
568 .video_mode = 0x4040,
569 .video_mode_adv = 0x18,
570 .video_prog_mode = 0x100,
571 .video_prog_mode_present = true,
572 /* video_sync_mode */
575 .video_filt_ctrl = 0x1052,
576 .video_filt_ctrl_present = true,
577 /* video_ofld_voav_ofst */
581 .hspuls_begin = 2156,
602 .vso_eline_present = true,
609 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
612 .video_mode = 0x4040,
613 .video_mode_adv = 0x18,
614 .video_prog_mode = 0x100,
615 .video_prog_mode_present = true,
616 .video_sync_mode = 0x7,
617 .video_sync_mode_present = true,
619 .video_yc_dly_present = true,
621 .video_rgb_ctrl_present = true,
622 /* video_filt_ctrl */
623 /* video_ofld_voav_ofst */
641 .eqpuls_bline_present = true,
643 .eqpuls_eline_present = true,
650 .vso_eline_present = true,
657 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
660 .video_mode = 0x4040,
661 .video_mode_adv = 0x18,
662 .video_prog_mode = 0x100,
663 .video_prog_mode_present = true,
664 /* video_sync_mode */
667 .video_filt_ctrl = 0x1052,
668 .video_filt_ctrl_present = true,
669 /* video_ofld_voav_ofst */
673 .hspuls_begin = 2156,
694 .vso_eline_present = true,
701 struct meson_hdmi_venc_vic_mode {
703 union meson_hdmi_venc_mode *mode;
704 } meson_hdmi_venc_vic_modes[] = {
705 { 6, &meson_hdmi_enci_mode_480i },
706 { 7, &meson_hdmi_enci_mode_480i },
707 { 21, &meson_hdmi_enci_mode_576i },
708 { 22, &meson_hdmi_enci_mode_576i },
709 { 2, &meson_hdmi_encp_mode_480p },
710 { 3, &meson_hdmi_encp_mode_480p },
711 { 17, &meson_hdmi_encp_mode_576p },
712 { 18, &meson_hdmi_encp_mode_576p },
713 { 4, &meson_hdmi_encp_mode_720p60 },
714 { 19, &meson_hdmi_encp_mode_720p50 },
715 { 5, &meson_hdmi_encp_mode_1080i60 },
716 { 20, &meson_hdmi_encp_mode_1080i50 },
717 { 32, &meson_hdmi_encp_mode_1080p24 },
718 { 33, &meson_hdmi_encp_mode_1080p50 },
719 { 34, &meson_hdmi_encp_mode_1080p30 },
720 { 31, &meson_hdmi_encp_mode_1080p50 },
721 { 16, &meson_hdmi_encp_mode_1080p60 },
722 { 0, NULL}, /* sentinel */
725 static signed int to_signed(unsigned int a)
733 static unsigned long modulo(unsigned long a, unsigned long b)
742 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
744 if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
745 DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
748 if (mode->hdisplay < 640 || mode->hdisplay > 1920)
749 return MODE_BAD_HVALUE;
751 if (mode->vdisplay < 480 || mode->vdisplay > 1200)
752 return MODE_BAD_VVALUE;
756 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode);
758 bool meson_venc_hdmi_supported_vic(int vic)
760 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
762 while (vmode->vic && vmode->mode) {
763 if (vmode->vic == vic)
770 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic);
772 void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode,
773 union meson_hdmi_venc_mode *dmt_mode)
775 memset(dmt_mode, 0, sizeof(*dmt_mode));
777 dmt_mode->encp.dvi_settings = 0x21;
778 dmt_mode->encp.video_mode = 0x4040;
779 dmt_mode->encp.video_mode_adv = 0x18;
780 dmt_mode->encp.max_pxcnt = mode->htotal - 1;
781 dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start;
782 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin +
784 dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start;
785 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline +
787 dmt_mode->encp.hso_begin = 0;
788 dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start;
789 dmt_mode->encp.vso_begin = 30;
790 dmt_mode->encp.vso_end = 50;
791 dmt_mode->encp.vso_bline = 0;
792 dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start;
793 dmt_mode->encp.vso_eline_present = true;
794 dmt_mode->encp.max_lncnt = mode->vtotal - 1;
797 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
799 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
801 while (vmode->vic && vmode->mode) {
802 if (vmode->vic == vic)
810 bool meson_venc_hdmi_venc_repeat(int vic)
812 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
813 if (vic == 6 || vic == 7 || /* 480i */
814 vic == 21 || vic == 22 || /* 576i */
815 vic == 17 || vic == 18 || /* 576p */
816 vic == 2 || vic == 3 || /* 480p */
817 vic == 4 || /* 720p60 */
818 vic == 19 || /* 720p50 */
819 vic == 5 || /* 1080i60 */
820 vic == 20) /* 1080i50 */
825 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
827 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
828 struct drm_display_mode *mode)
830 union meson_hdmi_venc_mode *vmode = NULL;
831 union meson_hdmi_venc_mode vmode_dmt;
832 bool use_enci = false;
833 bool venc_repeat = false;
834 bool hdmi_repeat = false;
835 unsigned int venc_hdmi_latency = 2;
836 unsigned long total_pixels_venc = 0;
837 unsigned long active_pixels_venc = 0;
838 unsigned long front_porch_venc = 0;
839 unsigned long hsync_pixels_venc = 0;
840 unsigned long de_h_begin = 0;
841 unsigned long de_h_end = 0;
842 unsigned long de_v_begin_even = 0;
843 unsigned long de_v_end_even = 0;
844 unsigned long de_v_begin_odd = 0;
845 unsigned long de_v_end_odd = 0;
846 unsigned long hs_begin = 0;
847 unsigned long hs_end = 0;
848 unsigned long vs_adjust = 0;
849 unsigned long vs_bline_evn = 0;
850 unsigned long vs_eline_evn = 0;
851 unsigned long vs_bline_odd = 0;
852 unsigned long vs_eline_odd = 0;
853 unsigned long vso_begin_evn = 0;
854 unsigned long vso_begin_odd = 0;
855 unsigned int eof_lines;
856 unsigned int sof_lines;
857 unsigned int vsync_lines;
859 if (meson_venc_hdmi_supported_vic(vic)) {
860 vmode = meson_venc_hdmi_get_vic_vmode(vic);
862 dev_err(priv->dev, "%s: Fatal Error, unsupported mode "
863 DRM_MODE_FMT "\n", __func__,
868 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
872 /* Use VENCI for 480i and 576i and double HDMI pixels */
873 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
876 venc_hdmi_latency = 1;
879 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
880 if (meson_venc_hdmi_venc_repeat(vic))
883 eof_lines = mode->vsync_start - mode->vdisplay;
884 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
886 sof_lines = mode->vtotal - mode->vsync_end;
887 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
889 vsync_lines = mode->vsync_end - mode->vsync_start;
890 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
893 total_pixels_venc = mode->htotal;
895 total_pixels_venc /= 2;
897 total_pixels_venc *= 2;
899 active_pixels_venc = mode->hdisplay;
901 active_pixels_venc /= 2;
903 active_pixels_venc *= 2;
905 front_porch_venc = (mode->hsync_start - mode->hdisplay);
907 front_porch_venc /= 2;
909 front_porch_venc *= 2;
911 hsync_pixels_venc = (mode->hsync_end - mode->hsync_start);
913 hsync_pixels_venc /= 2;
915 hsync_pixels_venc *= 2;
918 writel_bits_relaxed(0xff, 0xff,
919 priv->io_base + _REG(VENC_VDAC_SETTING));
921 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
922 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
925 unsigned int lines_f0;
926 unsigned int lines_f1;
928 /* CVBS Filter settings */
929 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
930 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
932 /* Digital Video Select : Interlace, clk27 clk, external */
933 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
935 /* Reset Video Mode */
936 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
937 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
939 /* Horizontal sync signal output */
940 writel_relaxed(vmode->enci.hso_begin,
941 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
942 writel_relaxed(vmode->enci.hso_end,
943 priv->io_base + _REG(ENCI_SYNC_HSO_END));
945 /* Vertical Sync lines */
946 writel_relaxed(vmode->enci.vso_even,
947 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
948 writel_relaxed(vmode->enci.vso_odd,
949 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
951 /* Macrovision max amplitude change */
952 writel_relaxed(vmode->enci.macv_max_amp,
953 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
956 writel_relaxed(vmode->enci.video_prog_mode,
957 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
958 writel_relaxed(vmode->enci.video_mode,
959 priv->io_base + _REG(ENCI_VIDEO_MODE));
961 /* Advanced Video Mode :
963 * Blank line end at line17/22
964 * High bandwidth Luma Filter
965 * Low bandwidth Chroma Filter
966 * Bypass luma low pass filter
967 * No macrovision on CSYNC
969 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
971 writel(vmode->enci.sch_adjust,
972 priv->io_base + _REG(ENCI_VIDEO_SCH));
974 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
975 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
977 if (vmode->enci.yc_delay)
978 writel_relaxed(vmode->enci.yc_delay,
979 priv->io_base + _REG(ENCI_YC_DELAY));
982 /* UNreset Interlaced TV Encoder */
983 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
985 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
986 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
989 writel_relaxed(vmode->enci.pixel_start,
990 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
991 writel_relaxed(vmode->enci.pixel_end,
992 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
994 writel_relaxed(vmode->enci.top_field_line_start,
995 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
996 writel_relaxed(vmode->enci.top_field_line_end,
997 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
999 writel_relaxed(vmode->enci.bottom_field_line_start,
1000 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1001 writel_relaxed(vmode->enci.bottom_field_line_end,
1002 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1004 /* Select ENCI for VIU */
1005 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1007 /* Interlace video enable */
1008 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1010 lines_f0 = mode->vtotal >> 1;
1011 lines_f1 = lines_f0 + 1;
1013 de_h_begin = modulo(readl_relaxed(priv->io_base +
1014 _REG(ENCI_VFIFO2VD_PIXEL_START))
1015 + venc_hdmi_latency,
1017 de_h_end = modulo(de_h_begin + active_pixels_venc,
1020 writel_relaxed(de_h_begin,
1021 priv->io_base + _REG(ENCI_DE_H_BEGIN));
1022 writel_relaxed(de_h_end,
1023 priv->io_base + _REG(ENCI_DE_H_END));
1025 de_v_begin_even = readl_relaxed(priv->io_base +
1026 _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1027 de_v_end_even = de_v_begin_even + mode->vdisplay;
1028 de_v_begin_odd = readl_relaxed(priv->io_base +
1029 _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1030 de_v_end_odd = de_v_begin_odd + mode->vdisplay;
1032 writel_relaxed(de_v_begin_even,
1033 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
1034 writel_relaxed(de_v_end_even,
1035 priv->io_base + _REG(ENCI_DE_V_END_EVEN));
1036 writel_relaxed(de_v_begin_odd,
1037 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
1038 writel_relaxed(de_v_end_odd,
1039 priv->io_base + _REG(ENCI_DE_V_END_ODD));
1041 /* Program Hsync timing */
1042 hs_begin = de_h_end + front_porch_venc;
1043 if (de_h_end + front_porch_venc >= total_pixels_venc) {
1044 hs_begin -= total_pixels_venc;
1047 hs_begin = de_h_end + front_porch_venc;
1051 hs_end = modulo(hs_begin + hsync_pixels_venc,
1053 writel_relaxed(hs_begin,
1054 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
1055 writel_relaxed(hs_end,
1056 priv->io_base + _REG(ENCI_DVI_HSO_END));
1058 /* Program Vsync timing for even field */
1059 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
1060 vs_bline_evn = (de_v_end_odd - 1)
1064 vs_eline_evn = vs_bline_evn + vsync_lines;
1066 writel_relaxed(vs_bline_evn,
1067 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1069 writel_relaxed(vs_eline_evn,
1070 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
1072 writel_relaxed(hs_begin,
1073 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1074 writel_relaxed(hs_begin,
1075 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
1077 vs_bline_odd = (de_v_end_odd - 1)
1081 writel_relaxed(vs_bline_odd,
1082 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1084 writel_relaxed(hs_begin,
1085 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1087 if ((vs_bline_odd + vsync_lines) >= lines_f1) {
1088 vs_eline_evn = vs_bline_odd
1092 writel_relaxed(vs_eline_evn, priv->io_base
1093 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1095 writel_relaxed(hs_begin, priv->io_base
1096 + _REG(ENCI_DVI_VSO_END_EVN));
1098 vs_eline_odd = vs_bline_odd
1101 writel_relaxed(vs_eline_odd, priv->io_base
1102 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1104 writel_relaxed(hs_begin, priv->io_base
1105 + _REG(ENCI_DVI_VSO_END_ODD));
1109 /* Program Vsync timing for odd field */
1110 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
1111 vs_bline_odd = (de_v_end_even - 1)
1114 vs_eline_odd = vs_bline_odd + vsync_lines;
1116 writel_relaxed(vs_bline_odd,
1117 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1119 writel_relaxed(vs_eline_odd,
1120 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
1122 vso_begin_odd = modulo(hs_begin
1123 + (total_pixels_venc >> 1),
1126 writel_relaxed(vso_begin_odd,
1127 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1128 writel_relaxed(vso_begin_odd,
1129 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
1131 vs_bline_evn = (de_v_end_even - 1)
1134 writel_relaxed(vs_bline_evn,
1135 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1137 vso_begin_evn = modulo(hs_begin
1138 + (total_pixels_venc >> 1),
1141 writel_relaxed(vso_begin_evn, priv->io_base
1142 + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1144 if (vs_bline_evn + vsync_lines >= lines_f0) {
1145 vs_eline_odd = vs_bline_evn
1149 writel_relaxed(vs_eline_odd, priv->io_base
1150 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1152 writel_relaxed(vso_begin_evn, priv->io_base
1153 + _REG(ENCI_DVI_VSO_END_ODD));
1155 vs_eline_evn = vs_bline_evn + vsync_lines;
1157 writel_relaxed(vs_eline_evn, priv->io_base
1158 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1160 writel_relaxed(vso_begin_evn, priv->io_base
1161 + _REG(ENCI_DVI_VSO_END_EVN));
1165 writel_relaxed(vmode->encp.dvi_settings,
1166 priv->io_base + _REG(VENC_DVI_SETTING));
1167 writel_relaxed(vmode->encp.video_mode,
1168 priv->io_base + _REG(ENCP_VIDEO_MODE));
1169 writel_relaxed(vmode->encp.video_mode_adv,
1170 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
1171 if (vmode->encp.video_prog_mode_present)
1172 writel_relaxed(vmode->encp.video_prog_mode,
1173 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1174 if (vmode->encp.video_sync_mode_present)
1175 writel_relaxed(vmode->encp.video_sync_mode,
1176 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
1177 if (vmode->encp.video_yc_dly_present)
1178 writel_relaxed(vmode->encp.video_yc_dly,
1179 priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
1180 if (vmode->encp.video_rgb_ctrl_present)
1181 writel_relaxed(vmode->encp.video_rgb_ctrl,
1182 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
1183 if (vmode->encp.video_filt_ctrl_present)
1184 writel_relaxed(vmode->encp.video_filt_ctrl,
1185 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
1186 if (vmode->encp.video_ofld_voav_ofst_present)
1187 writel_relaxed(vmode->encp.video_ofld_voav_ofst,
1189 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1190 writel_relaxed(vmode->encp.yfp1_htime,
1191 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
1192 writel_relaxed(vmode->encp.yfp2_htime,
1193 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
1194 writel_relaxed(vmode->encp.max_pxcnt,
1195 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
1196 writel_relaxed(vmode->encp.hspuls_begin,
1197 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
1198 writel_relaxed(vmode->encp.hspuls_end,
1199 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
1200 writel_relaxed(vmode->encp.hspuls_switch,
1201 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
1202 writel_relaxed(vmode->encp.vspuls_begin,
1203 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
1204 writel_relaxed(vmode->encp.vspuls_end,
1205 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
1206 writel_relaxed(vmode->encp.vspuls_bline,
1207 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
1208 writel_relaxed(vmode->encp.vspuls_eline,
1209 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
1210 if (vmode->encp.eqpuls_begin_present)
1211 writel_relaxed(vmode->encp.eqpuls_begin,
1212 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
1213 if (vmode->encp.eqpuls_end_present)
1214 writel_relaxed(vmode->encp.eqpuls_end,
1215 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
1216 if (vmode->encp.eqpuls_bline_present)
1217 writel_relaxed(vmode->encp.eqpuls_bline,
1218 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
1219 if (vmode->encp.eqpuls_eline_present)
1220 writel_relaxed(vmode->encp.eqpuls_eline,
1221 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
1222 writel_relaxed(vmode->encp.havon_begin,
1223 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
1224 writel_relaxed(vmode->encp.havon_end,
1225 priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
1226 writel_relaxed(vmode->encp.vavon_bline,
1227 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
1228 writel_relaxed(vmode->encp.vavon_eline,
1229 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
1230 writel_relaxed(vmode->encp.hso_begin,
1231 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
1232 writel_relaxed(vmode->encp.hso_end,
1233 priv->io_base + _REG(ENCP_VIDEO_HSO_END));
1234 writel_relaxed(vmode->encp.vso_begin,
1235 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
1236 writel_relaxed(vmode->encp.vso_end,
1237 priv->io_base + _REG(ENCP_VIDEO_VSO_END));
1238 writel_relaxed(vmode->encp.vso_bline,
1239 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
1240 if (vmode->encp.vso_eline_present)
1241 writel_relaxed(vmode->encp.vso_eline,
1242 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
1243 if (vmode->encp.sy_val_present)
1244 writel_relaxed(vmode->encp.sy_val,
1245 priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
1246 if (vmode->encp.sy2_val_present)
1247 writel_relaxed(vmode->encp.sy2_val,
1248 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
1249 writel_relaxed(vmode->encp.max_lncnt,
1250 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
1252 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
1254 /* Set DE signal’s polarity is active high */
1255 writel_bits_relaxed(BIT(14), BIT(14),
1256 priv->io_base + _REG(ENCP_VIDEO_MODE));
1258 /* Program DE timing */
1259 de_h_begin = modulo(readl_relaxed(priv->io_base +
1260 _REG(ENCP_VIDEO_HAVON_BEGIN))
1261 + venc_hdmi_latency,
1263 de_h_end = modulo(de_h_begin + active_pixels_venc,
1266 writel_relaxed(de_h_begin,
1267 priv->io_base + _REG(ENCP_DE_H_BEGIN));
1268 writel_relaxed(de_h_end,
1269 priv->io_base + _REG(ENCP_DE_H_END));
1271 /* Program DE timing for even field */
1272 de_v_begin_even = readl_relaxed(priv->io_base
1273 + _REG(ENCP_VIDEO_VAVON_BLINE));
1274 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1275 de_v_end_even = de_v_begin_even +
1276 (mode->vdisplay / 2);
1278 de_v_end_even = de_v_begin_even + mode->vdisplay;
1280 writel_relaxed(de_v_begin_even,
1281 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
1282 writel_relaxed(de_v_end_even,
1283 priv->io_base + _REG(ENCP_DE_V_END_EVEN));
1285 /* Program DE timing for odd field if needed */
1286 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1287 unsigned int ofld_voav_ofst =
1288 readl_relaxed(priv->io_base +
1289 _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1290 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
1292 + ((mode->vtotal - 1) / 2);
1293 de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2);
1295 writel_relaxed(de_v_begin_odd,
1296 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
1297 writel_relaxed(de_v_end_odd,
1298 priv->io_base + _REG(ENCP_DE_V_END_ODD));
1301 /* Program Hsync timing */
1302 if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
1305 - total_pixels_venc;
1313 hs_end = modulo(hs_begin + hsync_pixels_venc,
1316 writel_relaxed(hs_begin,
1317 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
1318 writel_relaxed(hs_end,
1319 priv->io_base + _REG(ENCP_DVI_HSO_END));
1321 /* Program Vsync timing for even field */
1322 if (de_v_begin_even >=
1323 (sof_lines + vsync_lines + (1 - vs_adjust)))
1324 vs_bline_evn = de_v_begin_even
1329 vs_bline_evn = mode->vtotal
1335 vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
1338 writel_relaxed(vs_bline_evn,
1339 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
1340 writel_relaxed(vs_eline_evn,
1341 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
1343 vso_begin_evn = hs_begin;
1344 writel_relaxed(vso_begin_evn,
1345 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
1346 writel_relaxed(vso_begin_evn,
1347 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
1349 /* Program Vsync timing for odd field if needed */
1350 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1351 vs_bline_odd = (de_v_begin_odd - 1)
1354 vs_eline_odd = (de_v_begin_odd - 1)
1356 vso_begin_odd = modulo(hs_begin
1357 + (total_pixels_venc >> 1),
1360 writel_relaxed(vs_bline_odd,
1361 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
1362 writel_relaxed(vs_eline_odd,
1363 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
1364 writel_relaxed(vso_begin_odd,
1365 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
1366 writel_relaxed(vso_begin_odd,
1367 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
1370 /* Select ENCP for VIU */
1371 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
1374 writel_relaxed((use_enci ? 1 : 2) |
1375 (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
1376 (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
1378 (venc_repeat ? 1 << 8 : 0) |
1379 (hdmi_repeat ? 1 << 12 : 0),
1380 priv->io_base + _REG(VPU_HDMI_SETTING));
1382 priv->venc.hdmi_repeat = hdmi_repeat;
1383 priv->venc.venc_repeat = venc_repeat;
1384 priv->venc.hdmi_use_enci = use_enci;
1386 priv->venc.current_mode = MESON_VENC_MODE_HDMI;
1388 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
1390 void meson_venci_cvbs_mode_set(struct meson_drm *priv,
1391 struct meson_cvbs_enci_mode *mode)
1393 if (mode->mode_tag == priv->venc.current_mode)
1396 /* CVBS Filter settings */
1397 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1398 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1400 /* Digital Video Select : Interlace, clk27 clk, external */
1401 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1403 /* Reset Video Mode */
1404 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1405 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1407 /* Horizontal sync signal output */
1408 writel_relaxed(mode->hso_begin,
1409 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1410 writel_relaxed(mode->hso_end,
1411 priv->io_base + _REG(ENCI_SYNC_HSO_END));
1413 /* Vertical Sync lines */
1414 writel_relaxed(mode->vso_even,
1415 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1416 writel_relaxed(mode->vso_odd,
1417 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1419 /* Macrovision max amplitude change */
1420 writel_relaxed(0x8100 + mode->macv_max_amp,
1421 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1424 writel_relaxed(mode->video_prog_mode,
1425 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1426 writel_relaxed(mode->video_mode,
1427 priv->io_base + _REG(ENCI_VIDEO_MODE));
1429 /* Advanced Video Mode :
1430 * Demux shifting 0x2
1431 * Blank line end at line17/22
1432 * High bandwidth Luma Filter
1433 * Low bandwidth Chroma Filter
1434 * Bypass luma low pass filter
1435 * No macrovision on CSYNC
1437 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1439 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
1441 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1442 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1444 /* 0x3 Y, C, and Component Y delay */
1445 writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
1448 writel_relaxed(mode->pixel_start,
1449 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1450 writel_relaxed(mode->pixel_end,
1451 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1453 writel_relaxed(mode->top_field_line_start,
1454 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1455 writel_relaxed(mode->top_field_line_end,
1456 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1458 writel_relaxed(mode->bottom_field_line_start,
1459 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1460 writel_relaxed(mode->bottom_field_line_end,
1461 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1463 /* Internal Venc, Internal VIU Sync, Internal Vencoder */
1464 writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
1466 /* UNreset Interlaced TV Encoder */
1467 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1469 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1470 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1473 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
1475 /* Video Upsampling */
1476 writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1477 writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1478 writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1480 /* Select Interlace Y DACs */
1481 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
1482 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
1483 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
1484 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
1485 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
1486 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
1488 /* Select ENCI for VIU */
1489 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1491 /* Enable ENCI FIFO */
1492 writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1494 /* Select ENCI DACs 0, 1, 4, and 5 */
1495 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
1496 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
1498 /* Interlace video enable */
1499 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1501 /* Configure Video Saturation / Contrast / Brightness / Hue */
1502 writel_relaxed(mode->video_saturation,
1503 priv->io_base + _REG(ENCI_VIDEO_SAT));
1504 writel_relaxed(mode->video_contrast,
1505 priv->io_base + _REG(ENCI_VIDEO_CONT));
1506 writel_relaxed(mode->video_brightness,
1507 priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
1508 writel_relaxed(mode->video_hue,
1509 priv->io_base + _REG(ENCI_VIDEO_HUE));
1511 /* Enable DAC0 Filter */
1512 writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1513 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
1515 /* 0 in Macrovision register 0 */
1516 writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
1518 /* Analog Synchronization and color burst value adjust */
1519 writel_relaxed(mode->analog_sync_adj,
1520 priv->io_base + _REG(ENCI_SYNC_ADJ));
1522 priv->venc.current_mode = mode->mode_tag;
1525 /* Returns the current ENCI field polarity */
1526 unsigned int meson_venci_get_field(struct meson_drm *priv)
1528 return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29);
1531 void meson_venc_enable_vsync(struct meson_drm *priv)
1533 writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
1534 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
1537 void meson_venc_disable_vsync(struct meson_drm *priv)
1539 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
1540 writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
1543 void meson_venc_init(struct meson_drm *priv)
1545 /* Disable CVBS VDAC */
1546 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
1547 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
1549 /* Power Down Dacs */
1550 writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
1552 /* Disable HDMI PHY */
1553 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
1556 writel_bits_relaxed(0x3, 0,
1557 priv->io_base + _REG(VPU_HDMI_SETTING));
1559 /* Disable all encoders */
1560 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1561 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1562 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
1564 /* Disable VSync IRQ */
1565 meson_venc_disable_vsync(priv);
1567 priv->venc.current_mode = MESON_VENC_MODE_NONE;