drivers/gpu/drm/msm/adreno/a3xx.xml.h

   1 #ifndef A3XX_XML
   2 #define A3XX_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-17 13:21:27)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31866 bytes, from 2017-06-06 18:26:14)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 111898 bytes, from 2017-06-06 18:23:59)
  18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 139480 bytes, from 2017-06-16 12:44:39)
  19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)
  20
  21 Copyright (C) 2013-2017 by the following authors:
  22 - Rob Clark <robdclark@gmail.com> (robclark)
  23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  24
  25 Permission is hereby granted, free of charge, to any person obtaining
  26 a copy of this software and associated documentation files (the
  27 "Software"), to deal in the Software without restriction, including
  28 without limitation the rights to use, copy, modify, merge, publish,
  29 distribute, sublicense, and/or sell copies of the Software, and to
  30 permit persons to whom the Software is furnished to do so, subject to
  31 the following conditions:
  32
  33 The above copyright notice and this permission notice (including the
  34 next paragraph) shall be included in all copies or substantial
  35 portions of the Software.
  36
  37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  44 */
  45
  46
  47 enum a3xx_tile_mode {
  48         LINEAR = 0,
  49         TILE_32X32 = 2,
  50 };
  51
  52 enum a3xx_state_block_id {
  53         HLSQ_BLOCK_ID_TP_TEX = 2,
  54         HLSQ_BLOCK_ID_TP_MIPMAP = 3,
  55         HLSQ_BLOCK_ID_SP_VS = 4,
  56         HLSQ_BLOCK_ID_SP_FS = 6,
  57 };
  58
  59 enum a3xx_cache_opcode {
  60         INVALIDATE = 1,
  61 };
  62
  63 enum a3xx_vtx_fmt {
  64         VFMT_32_FLOAT = 0,
  65         VFMT_32_32_FLOAT = 1,
  66         VFMT_32_32_32_FLOAT = 2,
  67         VFMT_32_32_32_32_FLOAT = 3,
  68         VFMT_16_FLOAT = 4,
  69         VFMT_16_16_FLOAT = 5,
  70         VFMT_16_16_16_FLOAT = 6,
  71         VFMT_16_16_16_16_FLOAT = 7,
  72         VFMT_32_FIXED = 8,
  73         VFMT_32_32_FIXED = 9,
  74         VFMT_32_32_32_FIXED = 10,
  75         VFMT_32_32_32_32_FIXED = 11,
  76         VFMT_16_SINT = 16,
  77         VFMT_16_16_SINT = 17,
  78         VFMT_16_16_16_SINT = 18,
  79         VFMT_16_16_16_16_SINT = 19,
  80         VFMT_16_UINT = 20,
  81         VFMT_16_16_UINT = 21,
  82         VFMT_16_16_16_UINT = 22,
  83         VFMT_16_16_16_16_UINT = 23,
  84         VFMT_16_SNORM = 24,
  85         VFMT_16_16_SNORM = 25,
  86         VFMT_16_16_16_SNORM = 26,
  87         VFMT_16_16_16_16_SNORM = 27,
  88         VFMT_16_UNORM = 28,
  89         VFMT_16_16_UNORM = 29,
  90         VFMT_16_16_16_UNORM = 30,
  91         VFMT_16_16_16_16_UNORM = 31,
  92         VFMT_32_UINT = 32,
  93         VFMT_32_32_UINT = 33,
  94         VFMT_32_32_32_UINT = 34,
  95         VFMT_32_32_32_32_UINT = 35,
  96         VFMT_32_SINT = 36,
  97         VFMT_32_32_SINT = 37,
  98         VFMT_32_32_32_SINT = 38,
  99         VFMT_32_32_32_32_SINT = 39,
 100         VFMT_8_UINT = 40,
 101         VFMT_8_8_UINT = 41,
 102         VFMT_8_8_8_UINT = 42,
 103         VFMT_8_8_8_8_UINT = 43,
 104         VFMT_8_UNORM = 44,
 105         VFMT_8_8_UNORM = 45,
 106         VFMT_8_8_8_UNORM = 46,
 107         VFMT_8_8_8_8_UNORM = 47,
 108         VFMT_8_SINT = 48,
 109         VFMT_8_8_SINT = 49,
 110         VFMT_8_8_8_SINT = 50,
 111         VFMT_8_8_8_8_SINT = 51,
 112         VFMT_8_SNORM = 52,
 113         VFMT_8_8_SNORM = 53,
 114         VFMT_8_8_8_SNORM = 54,
 115         VFMT_8_8_8_8_SNORM = 55,
 116         VFMT_10_10_10_2_UINT = 56,
 117         VFMT_10_10_10_2_UNORM = 57,
 118         VFMT_10_10_10_2_SINT = 58,
 119         VFMT_10_10_10_2_SNORM = 59,
 120         VFMT_2_10_10_10_UINT = 60,
 121         VFMT_2_10_10_10_UNORM = 61,
 122         VFMT_2_10_10_10_SINT = 62,
 123         VFMT_2_10_10_10_SNORM = 63,
 124 };
 125
 126 enum a3xx_tex_fmt {
 127         TFMT_5_6_5_UNORM = 4,
 128         TFMT_5_5_5_1_UNORM = 5,
 129         TFMT_4_4_4_4_UNORM = 7,
 130         TFMT_Z16_UNORM = 9,
 131         TFMT_X8Z24_UNORM = 10,
 132         TFMT_Z32_FLOAT = 11,
 133         TFMT_UV_64X32 = 16,
 134         TFMT_VU_64X32 = 17,
 135         TFMT_Y_64X32 = 18,
 136         TFMT_NV12_64X32 = 19,
 137         TFMT_UV_LINEAR = 20,
 138         TFMT_VU_LINEAR = 21,
 139         TFMT_Y_LINEAR = 22,
 140         TFMT_NV12_LINEAR = 23,
 141         TFMT_I420_Y = 24,
 142         TFMT_I420_U = 26,
 143         TFMT_I420_V = 27,
 144         TFMT_ATC_RGB = 32,
 145         TFMT_ATC_RGBA_EXPLICIT = 33,
 146         TFMT_ETC1 = 34,
 147         TFMT_ATC_RGBA_INTERPOLATED = 35,
 148         TFMT_DXT1 = 36,
 149         TFMT_DXT3 = 37,
 150         TFMT_DXT5 = 38,
 151         TFMT_2_10_10_10_UNORM = 40,
 152         TFMT_10_10_10_2_UNORM = 41,
 153         TFMT_9_9_9_E5_FLOAT = 42,
 154         TFMT_11_11_10_FLOAT = 43,
 155         TFMT_A8_UNORM = 44,
 156         TFMT_L8_UNORM = 45,
 157         TFMT_L8_A8_UNORM = 47,
 158         TFMT_8_UNORM = 48,
 159         TFMT_8_8_UNORM = 49,
 160         TFMT_8_8_8_UNORM = 50,
 161         TFMT_8_8_8_8_UNORM = 51,
 162         TFMT_8_SNORM = 52,
 163         TFMT_8_8_SNORM = 53,
 164         TFMT_8_8_8_SNORM = 54,
 165         TFMT_8_8_8_8_SNORM = 55,
 166         TFMT_8_UINT = 56,
 167         TFMT_8_8_UINT = 57,
 168         TFMT_8_8_8_UINT = 58,
 169         TFMT_8_8_8_8_UINT = 59,
 170         TFMT_8_SINT = 60,
 171         TFMT_8_8_SINT = 61,
 172         TFMT_8_8_8_SINT = 62,
 173         TFMT_8_8_8_8_SINT = 63,
 174         TFMT_16_FLOAT = 64,
 175         TFMT_16_16_FLOAT = 65,
 176         TFMT_16_16_16_16_FLOAT = 67,
 177         TFMT_16_UINT = 68,
 178         TFMT_16_16_UINT = 69,
 179         TFMT_16_16_16_16_UINT = 71,
 180         TFMT_16_SINT = 72,
 181         TFMT_16_16_SINT = 73,
 182         TFMT_16_16_16_16_SINT = 75,
 183         TFMT_16_UNORM = 76,
 184         TFMT_16_16_UNORM = 77,
 185         TFMT_16_16_16_16_UNORM = 79,
 186         TFMT_16_SNORM = 80,
 187         TFMT_16_16_SNORM = 81,
 188         TFMT_16_16_16_16_SNORM = 83,
 189         TFMT_32_FLOAT = 84,
 190         TFMT_32_32_FLOAT = 85,
 191         TFMT_32_32_32_32_FLOAT = 87,
 192         TFMT_32_UINT = 88,
 193         TFMT_32_32_UINT = 89,
 194         TFMT_32_32_32_32_UINT = 91,
 195         TFMT_32_SINT = 92,
 196         TFMT_32_32_SINT = 93,
 197         TFMT_32_32_32_32_SINT = 95,
 198         TFMT_2_10_10_10_UINT = 96,
 199         TFMT_10_10_10_2_UINT = 97,
 200         TFMT_ETC2_RG11_SNORM = 112,
 201         TFMT_ETC2_RG11_UNORM = 113,
 202         TFMT_ETC2_R11_SNORM = 114,
 203         TFMT_ETC2_R11_UNORM = 115,
 204         TFMT_ETC2_RGBA8 = 116,
 205         TFMT_ETC2_RGB8A1 = 117,
 206         TFMT_ETC2_RGB8 = 118,
 207 };
 208
 209 enum a3xx_tex_fetchsize {
 210         TFETCH_DISABLE = 0,
 211         TFETCH_1_BYTE = 1,
 212         TFETCH_2_BYTE = 2,
 213         TFETCH_4_BYTE = 3,
 214         TFETCH_8_BYTE = 4,
 215         TFETCH_16_BYTE = 5,
 216 };
 217
 218 enum a3xx_color_fmt {
 219         RB_R5G6B5_UNORM = 0,
 220         RB_R5G5B5A1_UNORM = 1,
 221         RB_R4G4B4A4_UNORM = 3,
 222         RB_R8G8B8_UNORM = 4,
 223         RB_R8G8B8A8_UNORM = 8,
 224         RB_R8G8B8A8_SNORM = 9,
 225         RB_R8G8B8A8_UINT = 10,
 226         RB_R8G8B8A8_SINT = 11,
 227         RB_R8G8_UNORM = 12,
 228         RB_R8G8_SNORM = 13,
 229         RB_R8_UINT = 14,
 230         RB_R8_SINT = 15,
 231         RB_R10G10B10A2_UNORM = 16,
 232         RB_A2R10G10B10_UNORM = 17,
 233         RB_R10G10B10A2_UINT = 18,
 234         RB_A2R10G10B10_UINT = 19,
 235         RB_A8_UNORM = 20,
 236         RB_R8_UNORM = 21,
 237         RB_R16_FLOAT = 24,
 238         RB_R16G16_FLOAT = 25,
 239         RB_R16G16B16A16_FLOAT = 27,
 240         RB_R11G11B10_FLOAT = 28,
 241         RB_R16_SNORM = 32,
 242         RB_R16G16_SNORM = 33,
 243         RB_R16G16B16A16_SNORM = 35,
 244         RB_R16_UNORM = 36,
 245         RB_R16G16_UNORM = 37,
 246         RB_R16G16B16A16_UNORM = 39,
 247         RB_R16_SINT = 40,
 248         RB_R16G16_SINT = 41,
 249         RB_R16G16B16A16_SINT = 43,
 250         RB_R16_UINT = 44,
 251         RB_R16G16_UINT = 45,
 252         RB_R16G16B16A16_UINT = 47,
 253         RB_R32_FLOAT = 48,
 254         RB_R32G32_FLOAT = 49,
 255         RB_R32G32B32A32_FLOAT = 51,
 256         RB_R32_SINT = 52,
 257         RB_R32G32_SINT = 53,
 258         RB_R32G32B32A32_SINT = 55,
 259         RB_R32_UINT = 56,
 260         RB_R32G32_UINT = 57,
 261         RB_R32G32B32A32_UINT = 59,
 262 };
 263
 264 enum a3xx_cp_perfcounter_select {
 265         CP_ALWAYS_COUNT = 0,
 266         CP_AHB_PFPTRANS_WAIT = 3,
 267         CP_AHB_NRTTRANS_WAIT = 6,
 268         CP_CSF_NRT_READ_WAIT = 8,
 269         CP_CSF_I1_FIFO_FULL = 9,
 270         CP_CSF_I2_FIFO_FULL = 10,
 271         CP_CSF_ST_FIFO_FULL = 11,
 272         CP_RESERVED_12 = 12,
 273         CP_CSF_RING_ROQ_FULL = 13,
 274         CP_CSF_I1_ROQ_FULL = 14,
 275         CP_CSF_I2_ROQ_FULL = 15,
 276         CP_CSF_ST_ROQ_FULL = 16,
 277         CP_RESERVED_17 = 17,
 278         CP_MIU_TAG_MEM_FULL = 18,
 279         CP_MIU_NRT_WRITE_STALLED = 22,
 280         CP_MIU_NRT_READ_STALLED = 23,
 281         CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
 282         CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
 283         CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
 284         CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
 285         CP_ME_MICRO_RB_STARVED = 30,
 286         CP_AHB_RBBM_DWORD_SENT = 40,
 287         CP_ME_BUSY_CLOCKS = 41,
 288         CP_ME_WAIT_CONTEXT_AVAIL = 42,
 289         CP_PFP_TYPE0_PACKET = 43,
 290         CP_PFP_TYPE3_PACKET = 44,
 291         CP_CSF_RB_WPTR_NEQ_RPTR = 45,
 292         CP_CSF_I1_SIZE_NEQ_ZERO = 46,
 293         CP_CSF_I2_SIZE_NEQ_ZERO = 47,
 294         CP_CSF_RBI1I2_FETCHING = 48,
 295 };
 296
 297 enum a3xx_gras_tse_perfcounter_select {
 298         GRAS_TSEPERF_INPUT_PRIM = 0,
 299         GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
 300         GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
 301         GRAS_TSEPERF_CLIPPED_PRIM = 3,
 302         GRAS_TSEPERF_NEW_PRIM = 4,
 303         GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
 304         GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
 305         GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
 306         GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
 307         GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
 308         GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
 309         GRAS_TSEPERF_POST_CLIP_PRIM = 11,
 310         GRAS_TSEPERF_WORKING_CYCLES = 12,
 311         GRAS_TSEPERF_PC_STARVE = 13,
 312         GRAS_TSERASPERF_STALL = 14,
 313 };
 314
 315 enum a3xx_gras_ras_perfcounter_select {
 316         GRAS_RASPERF_16X16_TILES = 0,
 317         GRAS_RASPERF_8X8_TILES = 1,
 318         GRAS_RASPERF_4X4_TILES = 2,
 319         GRAS_RASPERF_WORKING_CYCLES = 3,
 320         GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
 321         GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
 322         GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
 323 };
 324
 325 enum a3xx_hlsq_perfcounter_select {
 326         HLSQ_PERF_SP_VS_CONSTANT = 0,
 327         HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
 328         HLSQ_PERF_SP_FS_CONSTANT = 2,
 329         HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
 330         HLSQ_PERF_TP_STATE = 4,
 331         HLSQ_PERF_QUADS = 5,
 332         HLSQ_PERF_PIXELS = 6,
 333         HLSQ_PERF_VERTICES = 7,
 334         HLSQ_PERF_FS8_THREADS = 8,
 335         HLSQ_PERF_FS16_THREADS = 9,
 336         HLSQ_PERF_FS32_THREADS = 10,
 337         HLSQ_PERF_VS8_THREADS = 11,
 338         HLSQ_PERF_VS16_THREADS = 12,
 339         HLSQ_PERF_SP_VS_DATA_BYTES = 13,
 340         HLSQ_PERF_SP_FS_DATA_BYTES = 14,
 341         HLSQ_PERF_ACTIVE_CYCLES = 15,
 342         HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
 343         HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
 344         HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
 345         HLSQ_PERF_STALL_CYCLES_UCHE = 19,
 346         HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
 347         HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
 348         HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
 349         HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
 350         HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
 351         HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
 352         HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
 353         HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
 354         HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
 355 };
 356
 357 enum a3xx_pc_perfcounter_select {
 358         PC_PCPERF_VISIBILITY_STREAMS = 0,
 359         PC_PCPERF_TOTAL_INSTANCES = 1,
 360         PC_PCPERF_PRIMITIVES_PC_VPC = 2,
 361         PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
 362         PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
 363         PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
 364         PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
 365         PC_PCPERF_VERTICES_TO_VFD = 7,
 366         PC_PCPERF_REUSED_VERTICES = 8,
 367         PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
 368         PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
 369         PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
 370         PC_PCPERF_CYCLES_IS_WORKING = 12,
 371 };
 372
 373 enum a3xx_rb_perfcounter_select {
 374         RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
 375         RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
 376         RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
 377         RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
 378         RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
 379         RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
 380         RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
 381         RB_RBPERF_RB_MARB_DATA = 7,
 382         RB_RBPERF_SP_RB_QUAD = 8,
 383         RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
 384         RB_RBPERF_GMEM_CH0_READ = 10,
 385         RB_RBPERF_GMEM_CH1_READ = 11,
 386         RB_RBPERF_GMEM_CH0_WRITE = 12,
 387         RB_RBPERF_GMEM_CH1_WRITE = 13,
 388         RB_RBPERF_CP_CONTEXT_DONE = 14,
 389         RB_RBPERF_CP_CACHE_FLUSH = 15,
 390         RB_RBPERF_CP_ZPASS_DONE = 16,
 391 };
 392
 393 enum a3xx_rbbm_perfcounter_select {
 394         RBBM_ALAWYS_ON = 0,
 395         RBBM_VBIF_BUSY = 1,
 396         RBBM_TSE_BUSY = 2,
 397         RBBM_RAS_BUSY = 3,
 398         RBBM_PC_DCALL_BUSY = 4,
 399         RBBM_PC_VSD_BUSY = 5,
 400         RBBM_VFD_BUSY = 6,
 401         RBBM_VPC_BUSY = 7,
 402         RBBM_UCHE_BUSY = 8,
 403         RBBM_VSC_BUSY = 9,
 404         RBBM_HLSQ_BUSY = 10,
 405         RBBM_ANY_RB_BUSY = 11,
 406         RBBM_ANY_TEX_BUSY = 12,
 407         RBBM_ANY_USP_BUSY = 13,
 408         RBBM_ANY_MARB_BUSY = 14,
 409         RBBM_ANY_ARB_BUSY = 15,
 410         RBBM_AHB_STATUS_BUSY = 16,
 411         RBBM_AHB_STATUS_STALLED = 17,
 412         RBBM_AHB_STATUS_TXFR = 18,
 413         RBBM_AHB_STATUS_TXFR_SPLIT = 19,
 414         RBBM_AHB_STATUS_TXFR_ERROR = 20,
 415         RBBM_AHB_STATUS_LONG_STALL = 21,
 416         RBBM_RBBM_STATUS_MASKED = 22,
 417 };
 418
 419 enum a3xx_sp_perfcounter_select {
 420         SP_LM_LOAD_INSTRUCTIONS = 0,
 421         SP_LM_STORE_INSTRUCTIONS = 1,
 422         SP_LM_ATOMICS = 2,
 423         SP_UCHE_LOAD_INSTRUCTIONS = 3,
 424         SP_UCHE_STORE_INSTRUCTIONS = 4,
 425         SP_UCHE_ATOMICS = 5,
 426         SP_VS_TEX_INSTRUCTIONS = 6,
 427         SP_VS_CFLOW_INSTRUCTIONS = 7,
 428         SP_VS_EFU_INSTRUCTIONS = 8,
 429         SP_VS_FULL_ALU_INSTRUCTIONS = 9,
 430         SP_VS_HALF_ALU_INSTRUCTIONS = 10,
 431         SP_FS_TEX_INSTRUCTIONS = 11,
 432         SP_FS_CFLOW_INSTRUCTIONS = 12,
 433         SP_FS_EFU_INSTRUCTIONS = 13,
 434         SP_FS_FULL_ALU_INSTRUCTIONS = 14,
 435         SP_FS_HALF_ALU_INSTRUCTIONS = 15,
 436         SP_FS_BARY_INSTRUCTIONS = 16,
 437         SP_VS_INSTRUCTIONS = 17,
 438         SP_FS_INSTRUCTIONS = 18,
 439         SP_ADDR_LOCK_COUNT = 19,
 440         SP_UCHE_READ_TRANS = 20,
 441         SP_UCHE_WRITE_TRANS = 21,
 442         SP_EXPORT_VPC_TRANS = 22,
 443         SP_EXPORT_RB_TRANS = 23,
 444         SP_PIXELS_KILLED = 24,
 445         SP_ICL1_REQUESTS = 25,
 446         SP_ICL1_MISSES = 26,
 447         SP_ICL0_REQUESTS = 27,
 448         SP_ICL0_MISSES = 28,
 449         SP_ALU_ACTIVE_CYCLES = 29,
 450         SP_EFU_ACTIVE_CYCLES = 30,
 451         SP_STALL_CYCLES_BY_VPC = 31,
 452         SP_STALL_CYCLES_BY_TP = 32,
 453         SP_STALL_CYCLES_BY_UCHE = 33,
 454         SP_STALL_CYCLES_BY_RB = 34,
 455         SP_ACTIVE_CYCLES_ANY = 35,
 456         SP_ACTIVE_CYCLES_ALL = 36,
 457 };
 458
 459 enum a3xx_tp_perfcounter_select {
 460         TPL1_TPPERF_L1_REQUESTS = 0,
 461         TPL1_TPPERF_TP0_L1_REQUESTS = 1,
 462         TPL1_TPPERF_TP0_L1_MISSES = 2,
 463         TPL1_TPPERF_TP1_L1_REQUESTS = 3,
 464         TPL1_TPPERF_TP1_L1_MISSES = 4,
 465         TPL1_TPPERF_TP2_L1_REQUESTS = 5,
 466         TPL1_TPPERF_TP2_L1_MISSES = 6,
 467         TPL1_TPPERF_TP3_L1_REQUESTS = 7,
 468         TPL1_TPPERF_TP3_L1_MISSES = 8,
 469         TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
 470         TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
 471         TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
 472         TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
 473         TPL1_TPPERF_BILINEAR_OPS = 13,
 474         TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
 475         TPL1_TPPERF_QUADQUADS_SHADOW = 15,
 476         TPL1_TPPERF_QUADS_ARRAY = 16,
 477         TPL1_TPPERF_QUADS_PROJECTION = 17,
 478         TPL1_TPPERF_QUADS_GRADIENT = 18,
 479         TPL1_TPPERF_QUADS_1D2D = 19,
 480         TPL1_TPPERF_QUADS_3DCUBE = 20,
 481         TPL1_TPPERF_ZERO_LOD = 21,
 482         TPL1_TPPERF_OUTPUT_TEXELS = 22,
 483         TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
 484         TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
 485         TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
 486         TPL1_TPPERF_LATENCY = 26,
 487         TPL1_TPPERF_LATENCY_TRANS = 27,
 488 };
 489
 490 enum a3xx_vfd_perfcounter_select {
 491         VFD_PERF_UCHE_BYTE_FETCHED = 0,
 492         VFD_PERF_UCHE_TRANS = 1,
 493         VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
 494         VFD_PERF_FETCH_INSTRUCTIONS = 3,
 495         VFD_PERF_DECODE_INSTRUCTIONS = 4,
 496         VFD_PERF_ACTIVE_CYCLES = 5,
 497         VFD_PERF_STALL_CYCLES_UCHE = 6,
 498         VFD_PERF_STALL_CYCLES_HLSQ = 7,
 499         VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
 500         VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
 501 };
 502
 503 enum a3xx_vpc_perfcounter_select {
 504         VPC_PERF_SP_LM_PRIMITIVES = 0,
 505         VPC_PERF_COMPONENTS_FROM_SP = 1,
 506         VPC_PERF_SP_LM_COMPONENTS = 2,
 507         VPC_PERF_ACTIVE_CYCLES = 3,
 508         VPC_PERF_STALL_CYCLES_LM = 4,
 509         VPC_PERF_STALL_CYCLES_RAS = 5,
 510 };
 511
 512 enum a3xx_uche_perfcounter_select {
 513         UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
 514         UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
 515         UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
 516         UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
 517         UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
 518         UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
 519         UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
 520         UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
 521         UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
 522         UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
 523         UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
 524         UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
 525         UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
 526         UCHE_UCHEPERF_EVICTS = 16,
 527         UCHE_UCHEPERF_FLUSHES = 17,
 528         UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
 529         UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
 530         UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
 531 };
 532
 533 enum a3xx_intp_mode {
 534         SMOOTH = 0,
 535         FLAT = 1,
 536         ZERO = 2,
 537         ONE = 3,
 538 };
 539
 540 enum a3xx_repl_mode {
 541         S = 1,
 542         T = 2,
 543         ONE_T = 3,
 544 };
 545
 546 enum a3xx_tex_filter {
 547         A3XX_TEX_NEAREST = 0,
 548         A3XX_TEX_LINEAR = 1,
 549         A3XX_TEX_ANISO = 2,
 550 };
 551
 552 enum a3xx_tex_clamp {
 553         A3XX_TEX_REPEAT = 0,
 554         A3XX_TEX_CLAMP_TO_EDGE = 1,
 555         A3XX_TEX_MIRROR_REPEAT = 2,
 556         A3XX_TEX_CLAMP_TO_BORDER = 3,
 557         A3XX_TEX_MIRROR_CLAMP = 4,
 558 };
 559
 560 enum a3xx_tex_aniso {
 561         A3XX_TEX_ANISO_1 = 0,
 562         A3XX_TEX_ANISO_2 = 1,
 563         A3XX_TEX_ANISO_4 = 2,
 564         A3XX_TEX_ANISO_8 = 3,
 565         A3XX_TEX_ANISO_16 = 4,
 566 };
 567
 568 enum a3xx_tex_swiz {
 569         A3XX_TEX_X = 0,
 570         A3XX_TEX_Y = 1,
 571         A3XX_TEX_Z = 2,
 572         A3XX_TEX_W = 3,
 573         A3XX_TEX_ZERO = 4,
 574         A3XX_TEX_ONE = 5,
 575 };
 576
 577 enum a3xx_tex_type {
 578         A3XX_TEX_1D = 0,
 579         A3XX_TEX_2D = 1,
 580         A3XX_TEX_CUBE = 2,
 581         A3XX_TEX_3D = 3,
 582 };
 583
 584 enum a3xx_tex_msaa {
 585         A3XX_TPL1_MSAA1X = 0,
 586         A3XX_TPL1_MSAA2X = 1,
 587         A3XX_TPL1_MSAA4X = 2,
 588         A3XX_TPL1_MSAA8X = 3,
 589 };
 590
 591 #define A3XX_INT0_RBBM_GPU_IDLE                                 0x00000001
 592 #define A3XX_INT0_RBBM_AHB_ERROR                                0x00000002
 593 #define A3XX_INT0_RBBM_REG_TIMEOUT                              0x00000004
 594 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT                            0x00000008
 595 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT                           0x00000010
 596 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW                         0x00000020
 597 #define A3XX_INT0_VFD_ERROR                                     0x00000040
 598 #define A3XX_INT0_CP_SW_INT                                     0x00000080
 599 #define A3XX_INT0_CP_T0_PACKET_IN_IB                            0x00000100
 600 #define A3XX_INT0_CP_OPCODE_ERROR                               0x00000200
 601 #define A3XX_INT0_CP_RESERVED_BIT_ERROR                         0x00000400
 602 #define A3XX_INT0_CP_HW_FAULT                                   0x00000800
 603 #define A3XX_INT0_CP_DMA                                        0x00001000
 604 #define A3XX_INT0_CP_IB2_INT                                    0x00002000
 605 #define A3XX_INT0_CP_IB1_INT                                    0x00004000
 606 #define A3XX_INT0_CP_RB_INT                                     0x00008000
 607 #define A3XX_INT0_CP_REG_PROTECT_FAULT                          0x00010000
 608 #define A3XX_INT0_CP_RB_DONE_TS                                 0x00020000
 609 #define A3XX_INT0_CP_VS_DONE_TS                                 0x00040000
 610 #define A3XX_INT0_CP_PS_DONE_TS                                 0x00080000
 611 #define A3XX_INT0_CACHE_FLUSH_TS                                0x00100000
 612 #define A3XX_INT0_CP_AHB_ERROR_HALT                             0x00200000
 613 #define A3XX_INT0_MISC_HANG_DETECT                              0x01000000
 614 #define A3XX_INT0_UCHE_OOB_ACCESS                               0x02000000
 615 #define REG_A3XX_RBBM_HW_VERSION                                0x00000000
 616
 617 #define REG_A3XX_RBBM_HW_RELEASE                                0x00000001
 618
 619 #define REG_A3XX_RBBM_HW_CONFIGURATION                          0x00000002
 620
 621 #define REG_A3XX_RBBM_CLOCK_CTL                                 0x00000010
 622
 623 #define REG_A3XX_RBBM_SP_HYST_CNT                               0x00000012
 624
 625 #define REG_A3XX_RBBM_SW_RESET_CMD                              0x00000018
 626
 627 #define REG_A3XX_RBBM_AHB_CTL0                                  0x00000020
 628
 629 #define REG_A3XX_RBBM_AHB_CTL1                                  0x00000021
 630
 631 #define REG_A3XX_RBBM_AHB_CMD                                   0x00000022
 632
 633 #define REG_A3XX_RBBM_AHB_ERROR_STATUS                          0x00000027
 634
 635 #define REG_A3XX_RBBM_GPR0_CTL                                  0x0000002e
 636
 637 #define REG_A3XX_RBBM_STATUS                                    0x00000030
 638 #define A3XX_RBBM_STATUS_HI_BUSY                                0x00000001
 639 #define A3XX_RBBM_STATUS_CP_ME_BUSY                             0x00000002
 640 #define A3XX_RBBM_STATUS_CP_PFP_BUSY                            0x00000004
 641 #define A3XX_RBBM_STATUS_CP_NRT_BUSY                            0x00004000
 642 #define A3XX_RBBM_STATUS_VBIF_BUSY                              0x00008000
 643 #define A3XX_RBBM_STATUS_TSE_BUSY                               0x00010000
 644 #define A3XX_RBBM_STATUS_RAS_BUSY                               0x00020000
 645 #define A3XX_RBBM_STATUS_RB_BUSY                                0x00040000
 646 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00080000
 647 #define A3XX_RBBM_STATUS_PC_VSD_BUSY                            0x00100000
 648 #define A3XX_RBBM_STATUS_VFD_BUSY                               0x00200000
 649 #define A3XX_RBBM_STATUS_VPC_BUSY                               0x00400000
 650 #define A3XX_RBBM_STATUS_UCHE_BUSY                              0x00800000
 651 #define A3XX_RBBM_STATUS_SP_BUSY                                0x01000000
 652 #define A3XX_RBBM_STATUS_TPL1_BUSY                              0x02000000
 653 #define A3XX_RBBM_STATUS_MARB_BUSY                              0x04000000
 654 #define A3XX_RBBM_STATUS_VSC_BUSY                               0x08000000
 655 #define A3XX_RBBM_STATUS_ARB_BUSY                               0x10000000
 656 #define A3XX_RBBM_STATUS_HLSQ_BUSY                              0x20000000
 657 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC                          0x40000000
 658 #define A3XX_RBBM_STATUS_GPU_BUSY                               0x80000000
 659
 660 #define REG_A3XX_RBBM_NQWAIT_UNTIL                              0x00000040
 661
 662 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL                      0x00000033
 663
 664 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL                    0x00000050
 665
 666 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0                  0x00000051
 667
 668 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1                  0x00000054
 669
 670 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2                  0x00000057
 671
 672 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3                  0x0000005a
 673
 674 #define REG_A3XX_RBBM_INT_SET_CMD                               0x00000060
 675
 676 #define REG_A3XX_RBBM_INT_CLEAR_CMD                             0x00000061
 677
 678 #define REG_A3XX_RBBM_INT_0_MASK                                0x00000063
 679
 680 #define REG_A3XX_RBBM_INT_0_STATUS                              0x00000064
 681
 682 #define REG_A3XX_RBBM_PERFCTR_CTL                               0x00000080
 683 #define A3XX_RBBM_PERFCTR_CTL_ENABLE                            0x00000001
 684
 685 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000081
 686
 687 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000082
 688
 689 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000084
 690
 691 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x00000085
 692
 693 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT                       0x00000086
 694
 695 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT                       0x00000087
 696
 697 #define REG_A3XX_RBBM_GPU_BUSY_MASKED                           0x00000088
 698
 699 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO                           0x00000090
 700
 701 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI                           0x00000091
 702
 703 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO                         0x00000092
 704
 705 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI                         0x00000093
 706
 707 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO                         0x00000094
 708
 709 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI                         0x00000095
 710
 711 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO                           0x00000096
 712
 713 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI                           0x00000097
 714
 715 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO                           0x00000098
 716
 717 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI                           0x00000099
 718
 719 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO                           0x0000009a
 720
 721 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI                           0x0000009b
 722
 723 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO                           0x0000009c
 724
 725 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI                           0x0000009d
 726
 727 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO                          0x0000009e
 728
 729 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI                          0x0000009f
 730
 731 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO                          0x000000a0
 732
 733 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI                          0x000000a1
 734
 735 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO                         0x000000a2
 736
 737 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI                         0x000000a3
 738
 739 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO                         0x000000a4
 740
 741 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI                         0x000000a5
 742
 743 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO                         0x000000a6
 744
 745 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI                         0x000000a7
 746
 747 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO                         0x000000a8
 748
 749 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI                         0x000000a9
 750
 751 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO                         0x000000aa
 752
 753 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI                         0x000000ab
 754
 755 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO                         0x000000ac
 756
 757 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI                         0x000000ad
 758
 759 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO                          0x000000ae
 760
 761 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI                          0x000000af
 762
 763 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO                          0x000000b0
 764
 765 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI                          0x000000b1
 766
 767 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO                          0x000000b2
 768
 769 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI                          0x000000b3
 770
 771 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO                          0x000000b4
 772
 773 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI                          0x000000b5
 774
 775 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO                          0x000000b6
 776
 777 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI                          0x000000b7
 778
 779 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO                          0x000000b8
 780
 781 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI                          0x000000b9
 782
 783 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO                         0x000000ba
 784
 785 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI                         0x000000bb
 786
 787 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO                         0x000000bc
 788
 789 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI                         0x000000bd
 790
 791 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO                         0x000000be
 792
 793 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI                         0x000000bf
 794
 795 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO                         0x000000c0
 796
 797 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI                         0x000000c1
 798
 799 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO                         0x000000c2
 800
 801 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI                         0x000000c3
 802
 803 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO                         0x000000c4
 804
 805 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI                         0x000000c5
 806
 807 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO                           0x000000c6
 808
 809 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI                           0x000000c7
 810
 811 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO                           0x000000c8
 812
 813 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI                           0x000000c9
 814
 815 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO                           0x000000ca
 816
 817 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI                           0x000000cb
 818
 819 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO                           0x000000cc
 820
 821 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI                           0x000000cd
 822
 823 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO                           0x000000ce
 824
 825 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI                           0x000000cf
 826
 827 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO                           0x000000d0
 828
 829 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI                           0x000000d1
 830
 831 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO                           0x000000d2
 832
 833 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI                           0x000000d3
 834
 835 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO                           0x000000d4
 836
 837 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI                           0x000000d5
 838
 839 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO                           0x000000d6
 840
 841 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI                           0x000000d7
 842
 843 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO                           0x000000d8
 844
 845 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI                           0x000000d9
 846
 847 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO                           0x000000da
 848
 849 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI                           0x000000db
 850
 851 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO                           0x000000dc
 852
 853 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI                           0x000000dd
 854
 855 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO                           0x000000de
 856
 857 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI                           0x000000df
 858
 859 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO                           0x000000e0
 860
 861 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI                           0x000000e1
 862
 863 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO                           0x000000e2
 864
 865 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI                           0x000000e3
 866
 867 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO                           0x000000e4
 868
 869 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI                           0x000000e5
 870
 871 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO                          0x000000ea
 872
 873 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI                          0x000000eb
 874
 875 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO                          0x000000ec
 876
 877 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI                          0x000000ed
 878
 879 #define REG_A3XX_RBBM_RBBM_CTL                                  0x00000100
 880
 881 #define REG_A3XX_RBBM_DEBUG_BUS_CTL                             0x00000111
 882
 883 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS                     0x00000112
 884
 885 #define REG_A3XX_CP_PFP_UCODE_ADDR                              0x000001c9
 886
 887 #define REG_A3XX_CP_PFP_UCODE_DATA                              0x000001ca
 888
 889 #define REG_A3XX_CP_ROQ_ADDR                                    0x000001cc
 890
 891 #define REG_A3XX_CP_ROQ_DATA                                    0x000001cd
 892
 893 #define REG_A3XX_CP_MERCIU_ADDR                                 0x000001d1
 894
 895 #define REG_A3XX_CP_MERCIU_DATA                                 0x000001d2
 896
 897 #define REG_A3XX_CP_MERCIU_DATA2                                0x000001d3
 898
 899 #define REG_A3XX_CP_MEQ_ADDR                                    0x000001da
 900
 901 #define REG_A3XX_CP_MEQ_DATA                                    0x000001db
 902
 903 #define REG_A3XX_CP_WFI_PEND_CTR                                0x000001f5
 904
 905 #define REG_A3XX_RBBM_PM_OVERRIDE2                              0x0000039d
 906
 907 #define REG_A3XX_CP_PERFCOUNTER_SELECT                          0x00000445
 908
 909 #define REG_A3XX_CP_HW_FAULT                                    0x0000045c
 910
 911 #define REG_A3XX_CP_PROTECT_CTRL                                0x0000045e
 912
 913 #define REG_A3XX_CP_PROTECT_STATUS                              0x0000045f
 914
 915 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
 916
 917 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
 918
 919 #define REG_A3XX_CP_AHB_FAULT                                   0x0000054d
 920
 921 #define REG_A3XX_SQ_GPR_MANAGEMENT                              0x00000d00
 922
 923 #define REG_A3XX_SQ_INST_STORE_MANAGMENT                        0x00000d02
 924
 925 #define REG_A3XX_TP0_CHICKEN                                    0x00000e1e
 926
 927 #define REG_A3XX_SP_GLOBAL_MEM_SIZE                             0x00000e22
 928
 929 #define REG_A3XX_SP_GLOBAL_MEM_ADDR                             0x00000e23
 930
 931 #define REG_A3XX_GRAS_CL_CLIP_CNTL                              0x00002040
 932 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER                  0x00001000
 933 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE                     0x00010000
 934 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE                0x00020000
 935 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE              0x00080000
 936 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE                 0x00100000
 937 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE           0x00200000
 938 #define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z                  0x00400000
 939 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD                           0x00800000
 940 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD                           0x01000000
 941 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE                    0x02000000
 942 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK       0x1c000000
 943 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT      26
 944 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val)
 945 {
 946         return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK;
 947 }
 948
 949 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ                            0x00002044
 950 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK                     0x000003ff
 951 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT                    0
 952 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
 953 {
 954         return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
 955 }
 956 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK                     0x000ffc00
 957 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT                    10
 958 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
 959 {
 960         return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
 961 }
 962
 963 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET                          0x00002048
 964 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK                        0xffffffff
 965 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT                       0
 966 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
 967 {
 968         return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
 969 }
 970
 971 #define REG_A3XX_GRAS_CL_VPORT_XSCALE                           0x00002049
 972 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK                         0xffffffff
 973 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT                        0
 974 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
 975 {
 976         return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
 977 }
 978
 979 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET                          0x0000204a
 980 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK                        0xffffffff
 981 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT                       0
 982 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
 983 {
 984         return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK;
 985 }
 986
 987 #define REG_A3XX_GRAS_CL_VPORT_YSCALE                           0x0000204b
 988 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK                         0xffffffff
 989 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT                        0
 990 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
 991 {
 992         return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK;
 993 }
 994
 995 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET                          0x0000204c
 996 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK                        0xffffffff
 997 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT                       0
 998 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
 999 {
1000         return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK;
1001 }
1002
1003 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE                           0x0000204d
1004 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK                         0xffffffff
1005 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT                        0
1006 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
1007 {
1008         return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK;
1009 }
1010
1011 #define REG_A3XX_GRAS_SU_POINT_MINMAX                           0x00002068
1012 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK                     0x0000ffff
1013 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT                    0
1014 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
1015 {
1016         return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
1017 }
1018 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK                     0xffff0000
1019 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT                    16
1020 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
1021 {
1022         return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
1023 }
1024
1025 #define REG_A3XX_GRAS_SU_POINT_SIZE                             0x00002069
1026 #define A3XX_GRAS_SU_POINT_SIZE__MASK                           0xffffffff
1027 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT                          0
1028 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
1029 {
1030         return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
1031 }
1032
1033 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE                      0x0000206c
1034 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK                0x00ffffff
1035 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT               0
1036 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
1037 {
1038         return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
1039 }
1040
1041 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x0000206d
1042 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
1043 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
1044 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
1045 {
1046         return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
1047 }
1048
1049 #define REG_A3XX_GRAS_SU_MODE_CONTROL                           0x00002070
1050 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT                    0x00000001
1051 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK                     0x00000002
1052 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW                      0x00000004
1053 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK           0x000007f8
1054 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT          3
1055 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
1056 {
1057         return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
1058 }
1059 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET                   0x00000800
1060
1061 #define REG_A3XX_GRAS_SC_CONTROL                                0x00002072
1062 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK                  0x000000f0
1063 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT                 4
1064 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1065 {
1066         return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
1067 }
1068 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK                 0x00000f00
1069 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT                8
1070 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
1071 {
1072         return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
1073 }
1074 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK                  0x0000f000
1075 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT                 12
1076 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
1077 {
1078         return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
1079 }
1080
1081 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL                      0x00002074
1082 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
1083 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK                  0x00007fff
1084 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT                 0
1085 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
1086 {
1087         return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
1088 }
1089 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK                  0x7fff0000
1090 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT                 16
1091 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
1092 {
1093         return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
1094 }
1095
1096 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR                      0x00002075
1097 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
1098 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK                  0x00007fff
1099 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT                 0
1100 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
1101 {
1102         return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
1103 }
1104 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK                  0x7fff0000
1105 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT                 16
1106 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
1107 {
1108         return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
1109 }
1110
1111 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x00002079
1112 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
1113 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
1114 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
1115 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
1116 {
1117         return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
1118 }
1119 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
1120 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
1121 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
1122 {
1123         return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
1124 }
1125
1126 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x0000207a
1127 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
1128 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
1129 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
1130 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
1131 {
1132         return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
1133 }
1134 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
1135 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
1136 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
1137 {
1138         return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
1139 }
1140
1141 #define REG_A3XX_RB_MODE_CONTROL                                0x000020c0
1142 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS                        0x00000080
1143 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK                  0x00000700
1144 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT                 8
1145 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1146 {
1147         return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
1148 }
1149 #define A3XX_RB_MODE_CONTROL_MRT__MASK                          0x00003000
1150 #define A3XX_RB_MODE_CONTROL_MRT__SHIFT                         12
1151 static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
1152 {
1153         return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
1154 }
1155 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE              0x00008000
1156 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE                0x00010000
1157
1158 #define REG_A3XX_RB_RENDER_CONTROL                              0x000020c1
1159 #define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE             0x00000001
1160 #define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE                    0x00000002
1161 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE           0x00000004
1162 #define A3XX_RB_RENDER_CONTROL_FACENESS                         0x00000008
1163 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK                  0x00000ff0
1164 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT                 4
1165 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
1166 {
1167         return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
1168 }
1169 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE               0x00001000
1170 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM                      0x00002000
1171 #define A3XX_RB_RENDER_CONTROL_XCOORD                           0x00004000
1172 #define A3XX_RB_RENDER_CONTROL_YCOORD                           0x00008000
1173 #define A3XX_RB_RENDER_CONTROL_ZCOORD                           0x00010000
1174 #define A3XX_RB_RENDER_CONTROL_WCOORD                           0x00020000
1175 #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE                   0x00080000
1176 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE          0x00100000
1177 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST                       0x00400000
1178 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK            0x07000000
1179 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT           24
1180 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1181 {
1182         return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
1183 }
1184 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE                0x40000000
1185 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE                     0x80000000
1186
1187 #define REG_A3XX_RB_MSAA_CONTROL                                0x000020c2
1188 #define A3XX_RB_MSAA_CONTROL_DISABLE                            0x00000400
1189 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK                      0x0000f000
1190 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT                     12
1191 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
1192 {
1193         return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK;
1194 }
1195 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK                  0xffff0000
1196 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT                 16
1197 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
1198 {
1199         return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
1200 }
1201
1202 #define REG_A3XX_RB_ALPHA_REF                                   0x000020c3
1203 #define A3XX_RB_ALPHA_REF_UINT__MASK                            0x0000ff00
1204 #define A3XX_RB_ALPHA_REF_UINT__SHIFT                           8
1205 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
1206 {
1207         return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
1208 }
1209 #define A3XX_RB_ALPHA_REF_FLOAT__MASK                           0xffff0000
1210 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT                          16
1211 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
1212 {
1213         return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
1214 }
1215
1216 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
1217
1218 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
1219 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE                    0x00000008
1220 #define A3XX_RB_MRT_CONTROL_BLEND                               0x00000010
1221 #define A3XX_RB_MRT_CONTROL_BLEND2                              0x00000020
1222 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK                      0x00000f00
1223 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                     8
1224 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
1225 {
1226         return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
1227 }
1228 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK                   0x00003000
1229 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT                  12
1230 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
1231 {
1232         return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK;
1233 }
1234 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x0f000000
1235 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             24
1236 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
1237 {
1238         return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
1239 }
1240
1241 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
1242 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x0000003f
1243 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
1244 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
1245 {
1246         return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
1247 }
1248 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK              0x000000c0
1249 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT             6
1250 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
1251 {
1252         return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1253 }
1254 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00000c00
1255 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  10
1256 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1257 {
1258         return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1259 }
1260 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB                         0x00004000
1261 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK              0xfffe0000
1262 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT             17
1263 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1264 {
1265         return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1266 }
1267
1268 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
1269 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK               0xfffffff0
1270 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT              4
1271 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
1272 {
1273         return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
1274 }
1275
1276 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
1277 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
1278 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
1279 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1280 {
1281         return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1282 }
1283 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
1284 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
1285 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1286 {
1287         return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1288 }
1289 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
1290 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
1291 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1292 {
1293         return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1294 }
1295 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
1296 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
1297 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1298 {
1299         return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1300 }
1301 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
1302 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
1303 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1304 {
1305         return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1306 }
1307 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
1308 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
1309 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1310 {
1311         return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1312 }
1313 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE                  0x20000000
1314
1315 #define REG_A3XX_RB_BLEND_RED                                   0x000020e4
1316 #define A3XX_RB_BLEND_RED_UINT__MASK                            0x000000ff
1317 #define A3XX_RB_BLEND_RED_UINT__SHIFT                           0
1318 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
1319 {
1320         return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
1321 }
1322 #define A3XX_RB_BLEND_RED_FLOAT__MASK                           0xffff0000
1323 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT                          16
1324 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
1325 {
1326         return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
1327 }
1328
1329 #define REG_A3XX_RB_BLEND_GREEN                                 0x000020e5
1330 #define A3XX_RB_BLEND_GREEN_UINT__MASK                          0x000000ff
1331 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT                         0
1332 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
1333 {
1334         return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
1335 }
1336 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK                         0xffff0000
1337 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT                        16
1338 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
1339 {
1340         return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
1341 }
1342
1343 #define REG_A3XX_RB_BLEND_BLUE                                  0x000020e6
1344 #define A3XX_RB_BLEND_BLUE_UINT__MASK                           0x000000ff
1345 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT                          0
1346 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
1347 {
1348         return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
1349 }
1350 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK                          0xffff0000
1351 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT                         16
1352 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
1353 {
1354         return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
1355 }
1356
1357 #define REG_A3XX_RB_BLEND_ALPHA                                 0x000020e7
1358 #define A3XX_RB_BLEND_ALPHA_UINT__MASK                          0x000000ff
1359 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT                         0
1360 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1361 {
1362         return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
1363 }
1364 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK                         0xffff0000
1365 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT                        16
1366 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
1367 {
1368         return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
1369 }
1370
1371 #define REG_A3XX_RB_CLEAR_COLOR_DW0                             0x000020e8
1372
1373 #define REG_A3XX_RB_CLEAR_COLOR_DW1                             0x000020e9
1374
1375 #define REG_A3XX_RB_CLEAR_COLOR_DW2                             0x000020ea
1376
1377 #define REG_A3XX_RB_CLEAR_COLOR_DW3                             0x000020eb
1378
1379 #define REG_A3XX_RB_COPY_CONTROL                                0x000020ec
1380 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK                 0x00000003
1381 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT                0
1382 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1383 {
1384         return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1385 }
1386 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR                         0x00000008
1387 #define A3XX_RB_COPY_CONTROL_MODE__MASK                         0x00000070
1388 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT                        4
1389 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1390 {
1391         return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
1392 }
1393 #define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE               0x00000080
1394 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK                    0x00000f00
1395 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT                   8
1396 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1397 {
1398         return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1399 }
1400 #define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE                    0x00001000
1401 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK                    0xffffc000
1402 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT                   14
1403 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1404 {
1405         return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1406 }
1407
1408 #define REG_A3XX_RB_COPY_DEST_BASE                              0x000020ed
1409 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK                       0xfffffff0
1410 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT                      4
1411 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1412 {
1413         return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
1414 }
1415
1416 #define REG_A3XX_RB_COPY_DEST_PITCH                             0x000020ee
1417 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK                     0xffffffff
1418 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT                    0
1419 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1420 {
1421         return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1422 }
1423
1424 #define REG_A3XX_RB_COPY_DEST_INFO                              0x000020ef
1425 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK                       0x00000003
1426 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT                      0
1427 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
1428 {
1429         return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK;
1430 }
1431 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000fc
1432 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    2
1433 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
1434 {
1435         return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1436 }
1437 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
1438 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
1439 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1440 {
1441         return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
1442 }
1443 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK                0x00000c00
1444 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT               10
1445 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1446 {
1447         return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1448 }
1449 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK           0x0003c000
1450 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT          14
1451 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1452 {
1453         return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1454 }
1455 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK                     0x001c0000
1456 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT                    18
1457 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1458 {
1459         return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1460 }
1461
1462 #define REG_A3XX_RB_DEPTH_CONTROL                               0x00002100
1463 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z                     0x00000001
1464 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE                          0x00000002
1465 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE                    0x00000004
1466 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE                   0x00000008
1467 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK                       0x00000070
1468 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT                      4
1469 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1470 {
1471         return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1472 }
1473 #define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE                    0x00000080
1474 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE                     0x80000000
1475
1476 #define REG_A3XX_RB_DEPTH_CLEAR                                 0x00002101
1477
1478 #define REG_A3XX_RB_DEPTH_INFO                                  0x00002102
1479 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000003
1480 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
1481 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
1482 {
1483         return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1484 }
1485 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff800
1486 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    11
1487 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1488 {
1489         return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1490 }
1491
1492 #define REG_A3XX_RB_DEPTH_PITCH                                 0x00002103
1493 #define A3XX_RB_DEPTH_PITCH__MASK                               0xffffffff
1494 #define A3XX_RB_DEPTH_PITCH__SHIFT                              0
1495 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
1496 {
1497         return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
1498 }
1499
1500 #define REG_A3XX_RB_STENCIL_CONTROL                             0x00002104
1501 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
1502 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000002
1503 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ                    0x00000004
1504 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
1505 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
1506 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1507 {
1508         return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK;
1509 }
1510 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
1511 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
1512 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1513 {
1514         return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK;
1515 }
1516 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
1517 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
1518 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1519 {
1520         return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1521 }
1522 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
1523 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
1524 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1525 {
1526         return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1527 }
1528 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
1529 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
1530 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1531 {
1532         return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1533 }
1534 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
1535 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
1536 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1537 {
1538         return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1539 }
1540 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
1541 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
1542 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1543 {
1544         return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1545 }
1546 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
1547 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
1548 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1549 {
1550         return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1551 }
1552
1553 #define REG_A3XX_RB_STENCIL_CLEAR                               0x00002105
1554
1555 #define REG_A3XX_RB_STENCIL_INFO                                0x00002106
1556 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK                 0xfffff800
1557 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT                11
1558 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1559 {
1560         return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1561 }
1562
1563 #define REG_A3XX_RB_STENCIL_PITCH                               0x00002107
1564 #define A3XX_RB_STENCIL_PITCH__MASK                             0xffffffff
1565 #define A3XX_RB_STENCIL_PITCH__SHIFT                            0
1566 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
1567 {
1568         return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
1569 }
1570
1571 #define REG_A3XX_RB_STENCILREFMASK                              0x00002108
1572 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
1573 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
1574 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1575 {
1576         return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK;
1577 }
1578 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
1579 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
1580 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1581 {
1582         return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1583 }
1584 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
1585 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
1586 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1587 {
1588         return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1589 }
1590
1591 #define REG_A3XX_RB_STENCILREFMASK_BF                           0x00002109
1592 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
1593 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
1594 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1595 {
1596         return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1597 }
1598 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
1599 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
1600 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1601 {
1602         return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1603 }
1604 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
1605 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
1606 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1607 {
1608         return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1609 }
1610
1611 #define REG_A3XX_RB_LRZ_VSC_CONTROL                             0x0000210c
1612 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE                  0x00000002
1613
1614 #define REG_A3XX_RB_WINDOW_OFFSET                               0x0000210e
1615 #define A3XX_RB_WINDOW_OFFSET_X__MASK                           0x0000ffff
1616 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT                          0
1617 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
1618 {
1619         return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
1620 }
1621 #define A3XX_RB_WINDOW_OFFSET_Y__MASK                           0xffff0000
1622 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT                          16
1623 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
1624 {
1625         return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
1626 }
1627
1628 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL                        0x00002110
1629 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET                      0x00000001
1630 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY                       0x00000002
1631
1632 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR                           0x00002111
1633
1634 #define REG_A3XX_RB_Z_CLAMP_MIN                                 0x00002114
1635
1636 #define REG_A3XX_RB_Z_CLAMP_MAX                                 0x00002115
1637
1638 #define REG_A3XX_VGT_BIN_BASE                                   0x000021e1
1639
1640 #define REG_A3XX_VGT_BIN_SIZE                                   0x000021e2
1641
1642 #define REG_A3XX_PC_VSTREAM_CONTROL                             0x000021e4
1643 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK                      0x003f0000
1644 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT                     16
1645 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
1646 {
1647         return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK;
1648 }
1649 #define A3XX_PC_VSTREAM_CONTROL_N__MASK                         0x07c00000
1650 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT                        22
1651 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
1652 {
1653         return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK;
1654 }
1655
1656 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL                     0x000021ea
1657
1658 #define REG_A3XX_PC_PRIM_VTX_CNTL                               0x000021ec
1659 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK               0x0000001f
1660 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT              0
1661 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
1662 {
1663         return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK;
1664 }
1665 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK        0x000000e0
1666 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT       5
1667 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
1668 {
1669         return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK;
1670 }
1671 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK         0x00000700
1672 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT        8
1673 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
1674 {
1675         return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
1676 }
1677 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE                   0x00001000
1678 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART                 0x00100000
1679 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST                0x02000000
1680 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE                             0x04000000
1681
1682 #define REG_A3XX_PC_RESTART_INDEX                               0x000021ed
1683
1684 #define REG_A3XX_HLSQ_CONTROL_0_REG                             0x00002200
1685 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK              0x00000030
1686 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT             4
1687 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
1688 {
1689         return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
1690 }
1691 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE             0x00000040
1692 #define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE                     0x00000100
1693 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART                 0x00000200
1694 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2                       0x00000400
1695 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK      0x00fff000
1696 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT     12
1697 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
1698 {
1699         return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
1700 }
1701 #define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX                       0x02000000
1702 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE                    0x04000000
1703 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK                 0x08000000
1704 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT                27
1705 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
1706 {
1707         return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
1708 }
1709 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE               0x10000000
1710 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE               0x20000000
1711 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE                    0x40000000
1712 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT                   0x80000000
1713
1714 #define REG_A3XX_HLSQ_CONTROL_1_REG                             0x00002201
1715 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK              0x000000c0
1716 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT             6
1717 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
1718 {
1719         return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
1720 }
1721 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE             0x00000100
1722 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK          0x00ff0000
1723 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT         16
1724 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
1725 {
1726         return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
1727 }
1728 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK          0xff000000
1729 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT         24
1730 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
1731 {
1732         return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
1733 }
1734
1735 #define REG_A3XX_HLSQ_CONTROL_2_REG                             0x00002202
1736 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK             0x000003fc
1737 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT            2
1738 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
1739 {
1740         return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
1741 }
1742 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK             0x03fc0000
1743 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT            18
1744 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
1745 {
1746         return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
1747 }
1748 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK        0xfc000000
1749 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT       26
1750 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
1751 {
1752         return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
1753 }
1754
1755 #define REG_A3XX_HLSQ_CONTROL_3_REG                             0x00002203
1756 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK                     0x000000ff
1757 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT                    0
1758 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1759 {
1760         return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1761 }
1762
1763 #define REG_A3XX_HLSQ_VS_CONTROL_REG                            0x00002204
1764 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK              0x000003ff
1765 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT             0
1766 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1767 {
1768         return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
1769 }
1770 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK         0x001ff000
1771 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT        12
1772 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1773 {
1774         return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1775 }
1776 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
1777 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT             24
1778 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1779 {
1780         return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
1781 }
1782
1783 #define REG_A3XX_HLSQ_FS_CONTROL_REG                            0x00002205
1784 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK              0x000003ff
1785 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT             0
1786 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1787 {
1788         return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
1789 }
1790 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK         0x001ff000
1791 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT        12
1792 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1793 {
1794         return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1795 }
1796 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
1797 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT             24
1798 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1799 {
1800         return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
1801 }
1802
1803 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG                   0x00002206
1804 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK      0x000001ff
1805 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT     0
1806 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1807 {
1808         return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
1809 }
1810 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK        0x01ff0000
1811 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT       16
1812 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1813 {
1814         return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
1815 }
1816
1817 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG                   0x00002207
1818 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK      0x000001ff
1819 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT     0
1820 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1821 {
1822         return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
1823 }
1824 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK        0x01ff0000
1825 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT       16
1826 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1827 {
1828         return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
1829 }
1830
1831 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG                          0x0000220a
1832 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK                0x00000003
1833 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT               0
1834 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
1835 {
1836         return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
1837 }
1838 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK             0x00000ffc
1839 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT            2
1840 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
1841 {
1842         return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
1843 }
1844 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK             0x003ff000
1845 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT            12
1846 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
1847 {
1848         return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
1849 }
1850 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK             0xffc00000
1851 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT            22
1852 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
1853 {
1854         return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
1855 }
1856
1857 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1858
1859 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1860
1861 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
1862
1863 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG                          0x00002211
1864
1865 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG                          0x00002212
1866
1867 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG                       0x00002214
1868
1869 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1870
1871 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1872
1873 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG                     0x00002216
1874
1875 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG                     0x00002217
1876
1877 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG                          0x0000221a
1878
1879 #define REG_A3XX_VFD_CONTROL_0                                  0x00002240
1880 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK                  0x0003ffff
1881 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT                 0
1882 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1883 {
1884         return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1885 }
1886 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK                     0x003c0000
1887 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT                    18
1888 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
1889 {
1890         return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK;
1891 }
1892 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK                0x07c00000
1893 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT               22
1894 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1895 {
1896         return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1897 }
1898 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK              0xf8000000
1899 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT             27
1900 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1901 {
1902         return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1903 }
1904
1905 #define REG_A3XX_VFD_CONTROL_1                                  0x00002241
1906 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK                     0x0000000f
1907 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT                    0
1908 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1909 {
1910         return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1911 }
1912 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK                   0x000000f0
1913 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT                  4
1914 static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
1915 {
1916         return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
1917 }
1918 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK                   0x00000f00
1919 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT                  8
1920 static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
1921 {
1922         return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
1923 }
1924 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x00ff0000
1925 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     16
1926 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1927 {
1928         return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
1929 }
1930 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK                     0xff000000
1931 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT                    24
1932 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1933 {
1934         return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK;
1935 }
1936
1937 #define REG_A3XX_VFD_INDEX_MIN                                  0x00002242
1938
1939 #define REG_A3XX_VFD_INDEX_MAX                                  0x00002243
1940
1941 #define REG_A3XX_VFD_INSTANCEID_OFFSET                          0x00002244
1942
1943 #define REG_A3XX_VFD_INDEX_OFFSET                               0x00002245
1944
1945 #define REG_A3XX_VFD_INDEX_OFFSET                               0x00002245
1946
1947 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
1948
1949 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
1950 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK                  0x0000007f
1951 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT                 0
1952 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1953 {
1954         return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1955 }
1956 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK                  0x0000ff80
1957 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT                 7
1958 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1959 {
1960         return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1961 }
1962 #define A3XX_VFD_FETCH_INSTR_0_INSTANCED                        0x00010000
1963 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT                       0x00020000
1964 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK                  0x00fc0000
1965 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT                 18
1966 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
1967 {
1968         return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK;
1969 }
1970 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK                   0xff000000
1971 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT                  24
1972 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
1973 {
1974         return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
1975 }
1976
1977 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
1978
1979 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
1980
1981 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
1982 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK                   0x0000000f
1983 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT                  0
1984 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1985 {
1986         return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1987 }
1988 #define A3XX_VFD_DECODE_INSTR_CONSTFILL                         0x00000010
1989 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x00000fc0
1990 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     6
1991 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
1992 {
1993         return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK;
1994 }
1995 #define A3XX_VFD_DECODE_INSTR_REGID__MASK                       0x000ff000
1996 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT                      12
1997 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
1998 {
1999         return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
2000 }
2001 #define A3XX_VFD_DECODE_INSTR_INT                               0x00100000
2002 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK                        0x00c00000
2003 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT                       22
2004 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2005 {
2006         return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
2007 }
2008 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK                    0x1f000000
2009 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT                   24
2010 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
2011 {
2012         return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
2013 }
2014 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID                     0x20000000
2015 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT                        0x40000000
2016
2017 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD                     0x0000227e
2018 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK   0x0000000f
2019 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT  0
2020 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
2021 {
2022         return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK;
2023 }
2024 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK      0x0000ff00
2025 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT     8
2026 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
2027 {
2028         return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK;
2029 }
2030
2031 #define REG_A3XX_VPC_ATTR                                       0x00002280
2032 #define A3XX_VPC_ATTR_TOTALATTR__MASK                           0x000001ff
2033 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT                          0
2034 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
2035 {
2036         return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
2037 }
2038 #define A3XX_VPC_ATTR_PSIZE                                     0x00000200
2039 #define A3XX_VPC_ATTR_THRDASSIGN__MASK                          0x0ffff000
2040 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT                         12
2041 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2042 {
2043         return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK;
2044 }
2045 #define A3XX_VPC_ATTR_LMSIZE__MASK                              0xf0000000
2046 #define A3XX_VPC_ATTR_LMSIZE__SHIFT                             28
2047 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
2048 {
2049         return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK;
2050 }
2051
2052 #define REG_A3XX_VPC_PACK                                       0x00002281
2053 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK                      0x0000ff00
2054 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT                     8
2055 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2056 {
2057         return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2058 }
2059 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK                      0x00ff0000
2060 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT                     16
2061 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2062 {
2063         return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2064 }
2065
2066 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
2067
2068 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
2069 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK                   0x00000003
2070 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT                  0
2071 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val)
2072 {
2073         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK;
2074 }
2075 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK                   0x0000000c
2076 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT                  2
2077 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val)
2078 {
2079         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK;
2080 }
2081 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK                   0x00000030
2082 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT                  4
2083 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val)
2084 {
2085         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK;
2086 }
2087 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK                   0x000000c0
2088 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT                  6
2089 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val)
2090 {
2091         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK;
2092 }
2093 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK                   0x00000300
2094 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT                  8
2095 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val)
2096 {
2097         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK;
2098 }
2099 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK                   0x00000c00
2100 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT                  10
2101 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val)
2102 {
2103         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK;
2104 }
2105 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK                   0x00003000
2106 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT                  12
2107 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val)
2108 {
2109         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK;
2110 }
2111 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK                   0x0000c000
2112 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT                  14
2113 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val)
2114 {
2115         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK;
2116 }
2117 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK                   0x00030000
2118 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT                  16
2119 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val)
2120 {
2121         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK;
2122 }
2123 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK                   0x000c0000
2124 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT                  18
2125 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val)
2126 {
2127         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK;
2128 }
2129 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK                   0x00300000
2130 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT                  20
2131 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val)
2132 {
2133         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK;
2134 }
2135 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK                   0x00c00000
2136 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT                  22
2137 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val)
2138 {
2139         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK;
2140 }
2141 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK                   0x03000000
2142 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT                  24
2143 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val)
2144 {
2145         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK;
2146 }
2147 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK                   0x0c000000
2148 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT                  26
2149 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val)
2150 {
2151         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK;
2152 }
2153 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK                   0x30000000
2154 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT                  28
2155 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val)
2156 {
2157         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK;
2158 }
2159 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK                   0xc0000000
2160 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT                  30
2161 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
2162 {
2163         return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;
2164 }
2165
2166 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
2167
2168 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
2169 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK                  0x00000003
2170 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT                 0
2171 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
2172 {
2173         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
2174 }
2175 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK                  0x0000000c
2176 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT                 2
2177 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
2178 {
2179         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
2180 }
2181 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK                  0x00000030
2182 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT                 4
2183 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
2184 {
2185         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
2186 }
2187 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK                  0x000000c0
2188 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT                 6
2189 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
2190 {
2191         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
2192 }
2193 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK                  0x00000300
2194 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT                 8
2195 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
2196 {
2197         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
2198 }
2199 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK                  0x00000c00
2200 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT                 10
2201 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
2202 {
2203         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
2204 }
2205 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK                  0x00003000
2206 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT                 12
2207 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
2208 {
2209         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
2210 }
2211 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK                  0x0000c000
2212 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT                 14
2213 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
2214 {
2215         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
2216 }
2217 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK                  0x00030000
2218 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT                 16
2219 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
2220 {
2221         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
2222 }
2223 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK                  0x000c0000
2224 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT                 18
2225 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
2226 {
2227         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
2228 }
2229 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK                  0x00300000
2230 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT                 20
2231 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
2232 {
2233         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
2234 }
2235 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK                  0x00c00000
2236 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT                 22
2237 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
2238 {
2239         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
2240 }
2241 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK                  0x03000000
2242 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT                 24
2243 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
2244 {
2245         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
2246 }
2247 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK                  0x0c000000
2248 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT                 26
2249 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
2250 {
2251         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
2252 }
2253 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK                  0x30000000
2254 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT                 28
2255 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
2256 {
2257         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
2258 }
2259 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK                  0xc0000000
2260 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT                 30
2261 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
2262 {
2263         return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
2264 }
2265
2266 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0                      0x0000228a
2267
2268 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1                      0x0000228b
2269
2270 #define REG_A3XX_SP_SP_CTRL_REG                                 0x000022c0
2271 #define A3XX_SP_SP_CTRL_REG_RESOLVE                             0x00010000
2272 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK                     0x00040000
2273 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT                    18
2274 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
2275 {
2276         return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
2277 }
2278 #define A3XX_SP_SP_CTRL_REG_BINNING                             0x00080000
2279 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK                     0x00300000
2280 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT                    20
2281 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
2282 {
2283         return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
2284 }
2285 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK                        0x00c00000
2286 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT                       22
2287 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
2288 {
2289         return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
2290 }
2291
2292 #define REG_A3XX_SP_VS_CTRL_REG0                                0x000022c4
2293 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK                   0x00000001
2294 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT                  0
2295 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2296 {
2297         return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2298 }
2299 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK              0x00000002
2300 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT             1
2301 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2302 {
2303         return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2304 }
2305 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID                       0x00000004
2306 #define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE                         0x00000008
2307 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
2308 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
2309 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2310 {
2311         return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2312 }
2313 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
2314 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
2315 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2316 {
2317         return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2318 }
2319 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
2320 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  20
2321 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2322 {
2323         return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2324 }
2325 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
2326 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK                       0xff000000
2327 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT                      24
2328 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
2329 {
2330         return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
2331 }
2332
2333 #define REG_A3XX_SP_VS_CTRL_REG1                                0x000022c5
2334 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK                  0x000003ff
2335 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
2336 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2337 {
2338         return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2339 }
2340 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK               0x000ffc00
2341 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT              10
2342 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
2343 {
2344         return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2345 }
2346 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x7f000000
2347 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          24
2348 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2349 {
2350         return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2351 }
2352
2353 #define REG_A3XX_SP_VS_PARAM_REG                                0x000022c6
2354 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK                     0x000000ff
2355 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT                    0
2356 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2357 {
2358         return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
2359 }
2360 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK                   0x0000ff00
2361 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT                  8
2362 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2363 {
2364         return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2365 }
2366 #define A3XX_SP_VS_PARAM_REG_POS2DMODE                          0x00010000
2367 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK                0x01f00000
2368 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT               20
2369 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2370 {
2371         return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2372 }
2373
2374 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2375
2376 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2377 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000000ff
2378 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
2379 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2380 {
2381         return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
2382 }
2383 #define A3XX_SP_VS_OUT_REG_A_HALF                               0x00000100
2384 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00001e00
2385 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    9
2386 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2387 {
2388         return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2389 }
2390 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK                        0x00ff0000
2391 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
2392 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2393 {
2394         return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
2395 }
2396 #define A3XX_SP_VS_OUT_REG_B_HALF                               0x01000000
2397 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x1e000000
2398 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    25
2399 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2400 {
2401         return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2402 }
2403
2404 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2405
2406 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2407 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x0000007f
2408 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
2409 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2410 {
2411         return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2412 }
2413 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x00007f00
2414 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
2415 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2416 {
2417         return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2418 }
2419 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x007f0000
2420 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
2421 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2422 {
2423         return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2424 }
2425 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0x7f000000
2426 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
2427 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2428 {
2429         return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2430 }
2431
2432 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG                           0x000022d4
2433 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK    0x0000ffff
2434 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT   0
2435 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2436 {
2437         return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2438 }
2439 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
2440 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
2441 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2442 {
2443         return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2444 }
2445 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
2446 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
2447 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2448 {
2449         return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2450 }
2451
2452 #define REG_A3XX_SP_VS_OBJ_START_REG                            0x000022d5
2453
2454 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG                        0x000022d6
2455 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK       0x000000ff
2456 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT      0
2457 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2458 {
2459         return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2460 }
2461 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK        0x00ffff00
2462 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT       8
2463 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2464 {
2465         return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2466 }
2467 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
2468 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT        24
2469 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2470 {
2471         return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2472 }
2473
2474 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG                         0x000022d7
2475 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK              0x0000001f
2476 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT             0
2477 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2478 {
2479         return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2480 }
2481 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK    0xffffffe0
2482 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT   5
2483 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2484 {
2485         return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2486 }
2487
2488 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG                         0x000022d8
2489
2490 #define REG_A3XX_SP_VS_LENGTH_REG                               0x000022df
2491 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK                0xffffffff
2492 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT               0
2493 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2494 {
2495         return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK;
2496 }
2497
2498 #define REG_A3XX_SP_FS_CTRL_REG0                                0x000022e0
2499 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK                   0x00000001
2500 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT                  0
2501 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2502 {
2503         return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2504 }
2505 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK              0x00000002
2506 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT             1
2507 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2508 {
2509         return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2510 }
2511 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID                       0x00000004
2512 #define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE                         0x00000008
2513 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
2514 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
2515 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2516 {
2517         return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2518 }
2519 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
2520 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
2521 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2522 {
2523         return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2524 }
2525 #define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE                     0x00020000
2526 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP                    0x00040000
2527 #define A3XX_SP_FS_CTRL_REG0_OUTORDERED                         0x00080000
2528 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
2529 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  20
2530 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2531 {
2532         return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2533 }
2534 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
2535 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x00400000
2536 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE                        0x00800000
2537 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK                       0xff000000
2538 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT                      24
2539 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
2540 {
2541         return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK;
2542 }
2543
2544 #define REG_A3XX_SP_FS_CTRL_REG1                                0x000022e1
2545 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK                  0x000003ff
2546 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
2547 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2548 {
2549         return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2550 }
2551 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK               0x000ffc00
2552 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT              10
2553 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
2554 {
2555         return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2556 }
2557 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x00f00000
2558 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          20
2559 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2560 {
2561         return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2562 }
2563 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK            0x7f000000
2564 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT           24
2565 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
2566 {
2567         return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
2568 }
2569
2570 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG                           0x000022e2
2571 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK    0x0000ffff
2572 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT   0
2573 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2574 {
2575         return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2576 }
2577 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
2578 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
2579 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2580 {
2581         return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2582 }
2583 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
2584 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
2585 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2586 {
2587         return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2588 }
2589
2590 #define REG_A3XX_SP_FS_OBJ_START_REG                            0x000022e3
2591
2592 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG                        0x000022e4
2593 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK       0x000000ff
2594 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT      0
2595 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2596 {
2597         return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2598 }
2599 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK        0x00ffff00
2600 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT       8
2601 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2602 {
2603         return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2604 }
2605 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
2606 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT        24
2607 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2608 {
2609         return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2610 }
2611
2612 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG                         0x000022e5
2613 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK              0x0000001f
2614 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT             0
2615 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2616 {
2617         return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2618 }
2619 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK    0xffffffe0
2620 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT   5
2621 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2622 {
2623         return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2624 }
2625
2626 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG                         0x000022e6
2627
2628 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0                     0x000022e8
2629
2630 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1                     0x000022e9
2631
2632 #define REG_A3XX_SP_FS_OUTPUT_REG                               0x000022ec
2633 #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK                         0x00000003
2634 #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT                        0
2635 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2636 {
2637         return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
2638 }
2639 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE                      0x00000080
2640 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK                 0x0000ff00
2641 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT                8
2642 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2643 {
2644         return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2645 }
2646
2647 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
2648
2649 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
2650 #define A3XX_SP_FS_MRT_REG_REGID__MASK                          0x000000ff
2651 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT                         0
2652 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
2653 {
2654         return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK;
2655 }
2656 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION                       0x00000100
2657 #define A3XX_SP_FS_MRT_REG_SINT                                 0x00000400
2658 #define A3XX_SP_FS_MRT_REG_UINT                                 0x00000800
2659
2660 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
2661
2662 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
2663 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK             0x0000003f
2664 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT            0
2665 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
2666 {
2667         return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK;
2668 }
2669
2670 #define REG_A3XX_SP_FS_LENGTH_REG                               0x000022ff
2671 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK                0xffffffff
2672 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT               0
2673 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2674 {
2675         return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK;
2676 }
2677
2678 #define REG_A3XX_PA_SC_AA_CONFIG                                0x00002301
2679
2680 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET                          0x00002340
2681 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK          0x000000ff
2682 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT         0
2683 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
2684 {
2685         return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK;
2686 }
2687 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK           0x0000ff00
2688 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT          8
2689 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
2690 {
2691         return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK;
2692 }
2693 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK           0xffff0000
2694 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT          16
2695 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
2696 {
2697         return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK;
2698 }
2699
2700 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR              0x00002341
2701
2702 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET                          0x00002342
2703 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK          0x000000ff
2704 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT         0
2705 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
2706 {
2707         return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK;
2708 }
2709 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK           0x0000ff00
2710 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT          8
2711 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
2712 {
2713         return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK;
2714 }
2715 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK           0xffff0000
2716 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT          16
2717 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
2718 {
2719         return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK;
2720 }
2721
2722 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR              0x00002343
2723
2724 #define REG_A3XX_VBIF_CLKON                                     0x00003001
2725
2726 #define REG_A3XX_VBIF_FIXED_SORT_EN                             0x0000300c
2727
2728 #define REG_A3XX_VBIF_FIXED_SORT_SEL0                           0x0000300d
2729
2730 #define REG_A3XX_VBIF_FIXED_SORT_SEL1                           0x0000300e
2731
2732 #define REG_A3XX_VBIF_ABIT_SORT                                 0x0000301c
2733
2734 #define REG_A3XX_VBIF_ABIT_SORT_CONF                            0x0000301d
2735
2736 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
2737
2738 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0                           0x0000302c
2739
2740 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1                           0x0000302d
2741
2742 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0                           0x00003030
2743
2744 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1                           0x00003031
2745
2746 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0                          0x00003034
2747
2748 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0                          0x00003035
2749
2750 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST                         0x00003036
2751
2752 #define REG_A3XX_VBIF_ARB_CTL                                   0x0000303c
2753
2754 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB                       0x00003049
2755
2756 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0                    0x00003058
2757
2758 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN                           0x0000305e
2759
2760 #define REG_A3XX_VBIF_OUT_AXI_AOOO                              0x0000305f
2761
2762 #define REG_A3XX_VBIF_PERF_CNT_EN                               0x00003070
2763 #define A3XX_VBIF_PERF_CNT_EN_CNT0                              0x00000001
2764 #define A3XX_VBIF_PERF_CNT_EN_CNT1                              0x00000002
2765 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0                           0x00000004
2766 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1                           0x00000008
2767 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2                           0x00000010
2768
2769 #define REG_A3XX_VBIF_PERF_CNT_CLR                              0x00003071
2770 #define A3XX_VBIF_PERF_CNT_CLR_CNT0                             0x00000001
2771 #define A3XX_VBIF_PERF_CNT_CLR_CNT1                             0x00000002
2772 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0                          0x00000004
2773 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1                          0x00000008
2774 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2                          0x00000010
2775
2776 #define REG_A3XX_VBIF_PERF_CNT_SEL                              0x00003072
2777
2778 #define REG_A3XX_VBIF_PERF_CNT0_LO                              0x00003073
2779
2780 #define REG_A3XX_VBIF_PERF_CNT0_HI                              0x00003074
2781
2782 #define REG_A3XX_VBIF_PERF_CNT1_LO                              0x00003075
2783
2784 #define REG_A3XX_VBIF_PERF_CNT1_HI                              0x00003076
2785
2786 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO                          0x00003077
2787
2788 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI                          0x00003078
2789
2790 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO                          0x00003079
2791
2792 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI                          0x0000307a
2793
2794 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO                          0x0000307b
2795
2796 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI                          0x0000307c
2797
2798 #define REG_A3XX_VSC_BIN_SIZE                                   0x00000c01
2799 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK                           0x0000001f
2800 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
2801 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2802 {
2803         return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
2804 }
2805 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x000003e0
2806 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         5
2807 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2808 {
2809         return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
2810 }
2811
2812 #define REG_A3XX_VSC_SIZE_ADDRESS                               0x00000c02
2813
2814 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
2815
2816 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
2817 #define A3XX_VSC_PIPE_CONFIG_X__MASK                            0x000003ff
2818 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT                           0
2819 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
2820 {
2821         return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK;
2822 }
2823 #define A3XX_VSC_PIPE_CONFIG_Y__MASK                            0x000ffc00
2824 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT                           10
2825 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
2826 {
2827         return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK;
2828 }
2829 #define A3XX_VSC_PIPE_CONFIG_W__MASK                            0x00f00000
2830 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT                           20
2831 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
2832 {
2833         return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK;
2834 }
2835 #define A3XX_VSC_PIPE_CONFIG_H__MASK                            0x0f000000
2836 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT                           24
2837 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
2838 {
2839         return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
2840 }
2841
2842 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
2843
2844 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
2845
2846 #define REG_A3XX_VSC_BIN_CONTROL                                0x00000c3c
2847 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE                     0x00000001
2848
2849 #define REG_A3XX_UNKNOWN_0C3D                                   0x00000c3d
2850
2851 #define REG_A3XX_PC_PERFCOUNTER0_SELECT                         0x00000c48
2852
2853 #define REG_A3XX_PC_PERFCOUNTER1_SELECT                         0x00000c49
2854
2855 #define REG_A3XX_PC_PERFCOUNTER2_SELECT                         0x00000c4a
2856
2857 #define REG_A3XX_PC_PERFCOUNTER3_SELECT                         0x00000c4b
2858
2859 #define REG_A3XX_GRAS_TSE_DEBUG_ECO                             0x00000c81
2860
2861 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT                       0x00000c88
2862
2863 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT                       0x00000c89
2864
2865 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT                       0x00000c8a
2866
2867 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT                       0x00000c8b
2868
2869 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
2870
2871 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
2872
2873 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
2874
2875 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
2876
2877 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
2878
2879 #define REG_A3XX_RB_GMEM_BASE_ADDR                              0x00000cc0
2880
2881 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR                     0x00000cc1
2882
2883 #define REG_A3XX_RB_PERFCOUNTER0_SELECT                         0x00000cc6
2884
2885 #define REG_A3XX_RB_PERFCOUNTER1_SELECT                         0x00000cc7
2886
2887 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION                      0x00000ce0
2888 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK              0x00003fff
2889 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT             0
2890 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
2891 {
2892         return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
2893 }
2894 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK             0x0fffc000
2895 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT            14
2896 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
2897 {
2898         return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
2899 }
2900
2901 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT                       0x00000e00
2902
2903 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT                       0x00000e01
2904
2905 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT                       0x00000e02
2906
2907 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT                       0x00000e03
2908
2909 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT                       0x00000e04
2910
2911 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT                       0x00000e05
2912
2913 #define REG_A3XX_UNKNOWN_0E43                                   0x00000e43
2914
2915 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT                        0x00000e44
2916
2917 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT                        0x00000e45
2918
2919 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL                          0x00000e61
2920
2921 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ                         0x00000e62
2922
2923 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT                        0x00000e64
2924
2925 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT                        0x00000e65
2926
2927 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG                    0x00000e82
2928
2929 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT                       0x00000e84
2930
2931 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT                       0x00000e85
2932
2933 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT                       0x00000e86
2934
2935 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT                       0x00000e87
2936
2937 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT                       0x00000e88
2938
2939 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT                       0x00000e89
2940
2941 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG                     0x00000ea0
2942 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK              0x0fffffff
2943 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT             0
2944 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
2945 {
2946         return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK;
2947 }
2948
2949 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG                     0x00000ea1
2950 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK              0x0fffffff
2951 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT             0
2952 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
2953 {
2954         return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK;
2955 }
2956 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK            0x30000000
2957 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT           28
2958 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
2959 {
2960         return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK;
2961 }
2962 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE            0x80000000
2963
2964 #define REG_A3XX_UNKNOWN_0EA6                                   0x00000ea6
2965
2966 #define REG_A3XX_SP_PERFCOUNTER0_SELECT                         0x00000ec4
2967
2968 #define REG_A3XX_SP_PERFCOUNTER1_SELECT                         0x00000ec5
2969
2970 #define REG_A3XX_SP_PERFCOUNTER2_SELECT                         0x00000ec6
2971
2972 #define REG_A3XX_SP_PERFCOUNTER3_SELECT                         0x00000ec7
2973
2974 #define REG_A3XX_SP_PERFCOUNTER4_SELECT                         0x00000ec8
2975
2976 #define REG_A3XX_SP_PERFCOUNTER5_SELECT                         0x00000ec9
2977
2978 #define REG_A3XX_SP_PERFCOUNTER6_SELECT                         0x00000eca
2979
2980 #define REG_A3XX_SP_PERFCOUNTER7_SELECT                         0x00000ecb
2981
2982 #define REG_A3XX_UNKNOWN_0EE0                                   0x00000ee0
2983
2984 #define REG_A3XX_UNKNOWN_0F03                                   0x00000f03
2985
2986 #define REG_A3XX_TP_PERFCOUNTER0_SELECT                         0x00000f04
2987
2988 #define REG_A3XX_TP_PERFCOUNTER1_SELECT                         0x00000f05
2989
2990 #define REG_A3XX_TP_PERFCOUNTER2_SELECT                         0x00000f06
2991
2992 #define REG_A3XX_TP_PERFCOUNTER3_SELECT                         0x00000f07
2993
2994 #define REG_A3XX_TP_PERFCOUNTER4_SELECT                         0x00000f08
2995
2996 #define REG_A3XX_TP_PERFCOUNTER5_SELECT                         0x00000f09
2997
2998 #define REG_A3XX_VGT_CL_INITIATOR                               0x000021f0
2999
3000 #define REG_A3XX_VGT_EVENT_INITIATOR                            0x000021f9
3001
3002 #define REG_A3XX_VGT_DRAW_INITIATOR                             0x000021fc
3003 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK                 0x0000003f
3004 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT                0
3005 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
3006 {
3007         return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
3008 }
3009 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK             0x000000c0
3010 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT            6
3011 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
3012 {
3013         return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
3014 }
3015 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK                  0x00000600
3016 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT                 9
3017 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
3018 {
3019         return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
3020 }
3021 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK                0x00000800
3022 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT               11
3023 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
3024 {
3025         return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
3026 }
3027 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP                         0x00001000
3028 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX                     0x00002000
3029 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE       0x00004000
3030 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK             0xff000000
3031 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT            24
3032 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
3033 {
3034         return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
3035 }
3036
3037 #define REG_A3XX_VGT_IMMED_DATA                                 0x000021fd
3038
3039 #define REG_A3XX_TEX_SAMP_0                                     0x00000000
3040 #define A3XX_TEX_SAMP_0_CLAMPENABLE                             0x00000001
3041 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR                        0x00000002
3042 #define A3XX_TEX_SAMP_0_XY_MAG__MASK                            0x0000000c
3043 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT                           2
3044 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
3045 {
3046         return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK;
3047 }
3048 #define A3XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000030
3049 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT                           4
3050 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
3051 {
3052         return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK;
3053 }
3054 #define A3XX_TEX_SAMP_0_WRAP_S__MASK                            0x000001c0
3055 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT                           6
3056 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
3057 {
3058         return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK;
3059 }
3060 #define A3XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000e00
3061 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT                           9
3062 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
3063 {
3064         return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK;
3065 }
3066 #define A3XX_TEX_SAMP_0_WRAP_R__MASK                            0x00007000
3067 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT                           12
3068 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
3069 {
3070         return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
3071 }
3072 #define A3XX_TEX_SAMP_0_ANISO__MASK                             0x00038000
3073 #define A3XX_TEX_SAMP_0_ANISO__SHIFT                            15
3074 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
3075 {
3076         return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK;
3077 }
3078 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK                      0x00700000
3079 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT                     20
3080 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
3081 {
3082         return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
3083 }
3084 #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF                  0x01000000
3085 #define A3XX_TEX_SAMP_0_UNNORM_COORDS                           0x80000000
3086
3087 #define REG_A3XX_TEX_SAMP_1                                     0x00000001
3088 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK                          0x000007ff
3089 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT                         0
3090 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val)
3091 {
3092         return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK;
3093 }
3094 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK                           0x003ff000
3095 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT                          12
3096 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
3097 {
3098         return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
3099 }
3100 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK                           0xffc00000
3101 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT                          22
3102 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
3103 {
3104         return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
3105 }
3106
3107 #define REG_A3XX_TEX_CONST_0                                    0x00000000
3108 #define A3XX_TEX_CONST_0_TILED                                  0x00000001
3109 #define A3XX_TEX_CONST_0_SRGB                                   0x00000004
3110 #define A3XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
3111 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
3112 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
3113 {
3114         return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK;
3115 }
3116 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
3117 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
3118 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
3119 {
3120         return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK;
3121 }
3122 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
3123 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
3124 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
3125 {
3126         return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK;
3127 }
3128 #define A3XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
3129 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
3130 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
3131 {
3132         return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
3133 }
3134 #define A3XX_TEX_CONST_0_MIPLVLS__MASK                          0x000f0000
3135 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT                         16
3136 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
3137 {
3138         return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
3139 }
3140 #define A3XX_TEX_CONST_0_MSAATEX__MASK                          0x00300000
3141 #define A3XX_TEX_CONST_0_MSAATEX__SHIFT                         20
3142 static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
3143 {
3144         return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;
3145 }
3146 #define A3XX_TEX_CONST_0_FMT__MASK                              0x1fc00000
3147 #define A3XX_TEX_CONST_0_FMT__SHIFT                             22
3148 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
3149 {
3150         return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
3151 }
3152 #define A3XX_TEX_CONST_0_NOCONVERT                              0x20000000
3153 #define A3XX_TEX_CONST_0_TYPE__MASK                             0xc0000000
3154 #define A3XX_TEX_CONST_0_TYPE__SHIFT                            30
3155 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
3156 {
3157         return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
3158 }
3159
3160 #define REG_A3XX_TEX_CONST_1                                    0x00000001
3161 #define A3XX_TEX_CONST_1_HEIGHT__MASK                           0x00003fff
3162 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT                          0
3163 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
3164 {
3165         return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK;
3166 }
3167 #define A3XX_TEX_CONST_1_WIDTH__MASK                            0x0fffc000
3168 #define A3XX_TEX_CONST_1_WIDTH__SHIFT                           14
3169 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
3170 {
3171         return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
3172 }
3173 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK                        0xf0000000
3174 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT                       28
3175 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
3176 {
3177         return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK;
3178 }
3179
3180 #define REG_A3XX_TEX_CONST_2                                    0x00000002
3181 #define A3XX_TEX_CONST_2_INDX__MASK                             0x000001ff
3182 #define A3XX_TEX_CONST_2_INDX__SHIFT                            0
3183 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
3184 {
3185         return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK;
3186 }
3187 #define A3XX_TEX_CONST_2_PITCH__MASK                            0x3ffff000
3188 #define A3XX_TEX_CONST_2_PITCH__SHIFT                           12
3189 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
3190 {
3191         return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK;
3192 }
3193 #define A3XX_TEX_CONST_2_SWAP__MASK                             0xc0000000
3194 #define A3XX_TEX_CONST_2_SWAP__SHIFT                            30
3195 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
3196 {
3197         return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK;
3198 }
3199
3200 #define REG_A3XX_TEX_CONST_3                                    0x00000003
3201 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK                         0x0001ffff
3202 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT                        0
3203 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
3204 {
3205         return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
3206 }
3207 #define A3XX_TEX_CONST_3_DEPTH__MASK                            0x0ffe0000
3208 #define A3XX_TEX_CONST_3_DEPTH__SHIFT                           17
3209 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val)
3210 {
3211         return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK;
3212 }
3213 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK                         0xf0000000
3214 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT                        28
3215 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
3216 {
3217         return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
3218 }
3219
3220
3221 #endif /* A3XX_XML */