drivers/gpu/drm/msm/adreno/a5xx.xml.h

   1 #ifndef A5XX_XML
   2 #define A5XX_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
  12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
  13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
  14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
  15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
  16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
  17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
  18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
  19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
  20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
  21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
  22
  23 Copyright (C) 2013-2018 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26
  27 Permission is hereby granted, free of charge, to any person obtaining
  28 a copy of this software and associated documentation files (the
  29 "Software"), to deal in the Software without restriction, including
  30 without limitation the rights to use, copy, modify, merge, publish,
  31 distribute, sublicense, and/or sell copies of the Software, and to
  32 permit persons to whom the Software is furnished to do so, subject to
  33 the following conditions:
  34
  35 The above copyright notice and this permission notice (including the
  36 next paragraph) shall be included in all copies or substantial
  37 portions of the Software.
  38
  39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46 */
  47
  48
  49 enum a5xx_color_fmt {
  50         RB5_A8_UNORM = 2,
  51         RB5_R8_UNORM = 3,
  52         RB5_R8_SNORM = 4,
  53         RB5_R8_UINT = 5,
  54         RB5_R8_SINT = 6,
  55         RB5_R4G4B4A4_UNORM = 8,
  56         RB5_R5G5B5A1_UNORM = 10,
  57         RB5_R5G6B5_UNORM = 14,
  58         RB5_R8G8_UNORM = 15,
  59         RB5_R8G8_SNORM = 16,
  60         RB5_R8G8_UINT = 17,
  61         RB5_R8G8_SINT = 18,
  62         RB5_R16_UNORM = 21,
  63         RB5_R16_SNORM = 22,
  64         RB5_R16_FLOAT = 23,
  65         RB5_R16_UINT = 24,
  66         RB5_R16_SINT = 25,
  67         RB5_R8G8B8A8_UNORM = 48,
  68         RB5_R8G8B8_UNORM = 49,
  69         RB5_R8G8B8A8_SNORM = 50,
  70         RB5_R8G8B8A8_UINT = 51,
  71         RB5_R8G8B8A8_SINT = 52,
  72         RB5_R10G10B10A2_UNORM = 55,
  73         RB5_R10G10B10A2_UINT = 58,
  74         RB5_R11G11B10_FLOAT = 66,
  75         RB5_R16G16_UNORM = 67,
  76         RB5_R16G16_SNORM = 68,
  77         RB5_R16G16_FLOAT = 69,
  78         RB5_R16G16_UINT = 70,
  79         RB5_R16G16_SINT = 71,
  80         RB5_R32_FLOAT = 74,
  81         RB5_R32_UINT = 75,
  82         RB5_R32_SINT = 76,
  83         RB5_R16G16B16A16_UNORM = 96,
  84         RB5_R16G16B16A16_SNORM = 97,
  85         RB5_R16G16B16A16_FLOAT = 98,
  86         RB5_R16G16B16A16_UINT = 99,
  87         RB5_R16G16B16A16_SINT = 100,
  88         RB5_R32G32_FLOAT = 103,
  89         RB5_R32G32_UINT = 104,
  90         RB5_R32G32_SINT = 105,
  91         RB5_R32G32B32A32_FLOAT = 130,
  92         RB5_R32G32B32A32_UINT = 131,
  93         RB5_R32G32B32A32_SINT = 132,
  94 };
  95
  96 enum a5xx_tile_mode {
  97         TILE5_LINEAR = 0,
  98         TILE5_2 = 2,
  99         TILE5_3 = 3,
 100 };
 101
 102 enum a5xx_vtx_fmt {
 103         VFMT5_8_UNORM = 3,
 104         VFMT5_8_SNORM = 4,
 105         VFMT5_8_UINT = 5,
 106         VFMT5_8_SINT = 6,
 107         VFMT5_8_8_UNORM = 15,
 108         VFMT5_8_8_SNORM = 16,
 109         VFMT5_8_8_UINT = 17,
 110         VFMT5_8_8_SINT = 18,
 111         VFMT5_16_UNORM = 21,
 112         VFMT5_16_SNORM = 22,
 113         VFMT5_16_FLOAT = 23,
 114         VFMT5_16_UINT = 24,
 115         VFMT5_16_SINT = 25,
 116         VFMT5_8_8_8_UNORM = 33,
 117         VFMT5_8_8_8_SNORM = 34,
 118         VFMT5_8_8_8_UINT = 35,
 119         VFMT5_8_8_8_SINT = 36,
 120         VFMT5_8_8_8_8_UNORM = 48,
 121         VFMT5_8_8_8_8_SNORM = 50,
 122         VFMT5_8_8_8_8_UINT = 51,
 123         VFMT5_8_8_8_8_SINT = 52,
 124         VFMT5_10_10_10_2_UNORM = 54,
 125         VFMT5_10_10_10_2_SNORM = 57,
 126         VFMT5_10_10_10_2_UINT = 58,
 127         VFMT5_10_10_10_2_SINT = 59,
 128         VFMT5_11_11_10_FLOAT = 66,
 129         VFMT5_16_16_UNORM = 67,
 130         VFMT5_16_16_SNORM = 68,
 131         VFMT5_16_16_FLOAT = 69,
 132         VFMT5_16_16_UINT = 70,
 133         VFMT5_16_16_SINT = 71,
 134         VFMT5_32_UNORM = 72,
 135         VFMT5_32_SNORM = 73,
 136         VFMT5_32_FLOAT = 74,
 137         VFMT5_32_UINT = 75,
 138         VFMT5_32_SINT = 76,
 139         VFMT5_32_FIXED = 77,
 140         VFMT5_16_16_16_UNORM = 88,
 141         VFMT5_16_16_16_SNORM = 89,
 142         VFMT5_16_16_16_FLOAT = 90,
 143         VFMT5_16_16_16_UINT = 91,
 144         VFMT5_16_16_16_SINT = 92,
 145         VFMT5_16_16_16_16_UNORM = 96,
 146         VFMT5_16_16_16_16_SNORM = 97,
 147         VFMT5_16_16_16_16_FLOAT = 98,
 148         VFMT5_16_16_16_16_UINT = 99,
 149         VFMT5_16_16_16_16_SINT = 100,
 150         VFMT5_32_32_UNORM = 101,
 151         VFMT5_32_32_SNORM = 102,
 152         VFMT5_32_32_FLOAT = 103,
 153         VFMT5_32_32_UINT = 104,
 154         VFMT5_32_32_SINT = 105,
 155         VFMT5_32_32_FIXED = 106,
 156         VFMT5_32_32_32_UNORM = 112,
 157         VFMT5_32_32_32_SNORM = 113,
 158         VFMT5_32_32_32_UINT = 114,
 159         VFMT5_32_32_32_SINT = 115,
 160         VFMT5_32_32_32_FLOAT = 116,
 161         VFMT5_32_32_32_FIXED = 117,
 162         VFMT5_32_32_32_32_UNORM = 128,
 163         VFMT5_32_32_32_32_SNORM = 129,
 164         VFMT5_32_32_32_32_FLOAT = 130,
 165         VFMT5_32_32_32_32_UINT = 131,
 166         VFMT5_32_32_32_32_SINT = 132,
 167         VFMT5_32_32_32_32_FIXED = 133,
 168 };
 169
 170 enum a5xx_tex_fmt {
 171         TFMT5_A8_UNORM = 2,
 172         TFMT5_8_UNORM = 3,
 173         TFMT5_8_SNORM = 4,
 174         TFMT5_8_UINT = 5,
 175         TFMT5_8_SINT = 6,
 176         TFMT5_4_4_4_4_UNORM = 8,
 177         TFMT5_5_5_5_1_UNORM = 10,
 178         TFMT5_5_6_5_UNORM = 14,
 179         TFMT5_8_8_UNORM = 15,
 180         TFMT5_8_8_SNORM = 16,
 181         TFMT5_8_8_UINT = 17,
 182         TFMT5_8_8_SINT = 18,
 183         TFMT5_L8_A8_UNORM = 19,
 184         TFMT5_16_UNORM = 21,
 185         TFMT5_16_SNORM = 22,
 186         TFMT5_16_FLOAT = 23,
 187         TFMT5_16_UINT = 24,
 188         TFMT5_16_SINT = 25,
 189         TFMT5_8_8_8_8_UNORM = 48,
 190         TFMT5_8_8_8_UNORM = 49,
 191         TFMT5_8_8_8_8_SNORM = 50,
 192         TFMT5_8_8_8_8_UINT = 51,
 193         TFMT5_8_8_8_8_SINT = 52,
 194         TFMT5_9_9_9_E5_FLOAT = 53,
 195         TFMT5_10_10_10_2_UNORM = 54,
 196         TFMT5_10_10_10_2_UINT = 58,
 197         TFMT5_11_11_10_FLOAT = 66,
 198         TFMT5_16_16_UNORM = 67,
 199         TFMT5_16_16_SNORM = 68,
 200         TFMT5_16_16_FLOAT = 69,
 201         TFMT5_16_16_UINT = 70,
 202         TFMT5_16_16_SINT = 71,
 203         TFMT5_32_FLOAT = 74,
 204         TFMT5_32_UINT = 75,
 205         TFMT5_32_SINT = 76,
 206         TFMT5_16_16_16_16_UNORM = 96,
 207         TFMT5_16_16_16_16_SNORM = 97,
 208         TFMT5_16_16_16_16_FLOAT = 98,
 209         TFMT5_16_16_16_16_UINT = 99,
 210         TFMT5_16_16_16_16_SINT = 100,
 211         TFMT5_32_32_FLOAT = 103,
 212         TFMT5_32_32_UINT = 104,
 213         TFMT5_32_32_SINT = 105,
 214         TFMT5_32_32_32_UINT = 114,
 215         TFMT5_32_32_32_SINT = 115,
 216         TFMT5_32_32_32_FLOAT = 116,
 217         TFMT5_32_32_32_32_FLOAT = 130,
 218         TFMT5_32_32_32_32_UINT = 131,
 219         TFMT5_32_32_32_32_SINT = 132,
 220         TFMT5_X8Z24_UNORM = 160,
 221         TFMT5_ETC2_RG11_UNORM = 171,
 222         TFMT5_ETC2_RG11_SNORM = 172,
 223         TFMT5_ETC2_R11_UNORM = 173,
 224         TFMT5_ETC2_R11_SNORM = 174,
 225         TFMT5_ETC1 = 175,
 226         TFMT5_ETC2_RGB8 = 176,
 227         TFMT5_ETC2_RGBA8 = 177,
 228         TFMT5_ETC2_RGB8A1 = 178,
 229         TFMT5_DXT1 = 179,
 230         TFMT5_DXT3 = 180,
 231         TFMT5_DXT5 = 181,
 232         TFMT5_RGTC1_UNORM = 183,
 233         TFMT5_RGTC1_SNORM = 184,
 234         TFMT5_RGTC2_UNORM = 187,
 235         TFMT5_RGTC2_SNORM = 188,
 236         TFMT5_BPTC_UFLOAT = 190,
 237         TFMT5_BPTC_FLOAT = 191,
 238         TFMT5_BPTC = 192,
 239         TFMT5_ASTC_4x4 = 193,
 240         TFMT5_ASTC_5x4 = 194,
 241         TFMT5_ASTC_5x5 = 195,
 242         TFMT5_ASTC_6x5 = 196,
 243         TFMT5_ASTC_6x6 = 197,
 244         TFMT5_ASTC_8x5 = 198,
 245         TFMT5_ASTC_8x6 = 199,
 246         TFMT5_ASTC_8x8 = 200,
 247         TFMT5_ASTC_10x5 = 201,
 248         TFMT5_ASTC_10x6 = 202,
 249         TFMT5_ASTC_10x8 = 203,
 250         TFMT5_ASTC_10x10 = 204,
 251         TFMT5_ASTC_12x10 = 205,
 252         TFMT5_ASTC_12x12 = 206,
 253 };
 254
 255 enum a5xx_tex_fetchsize {
 256         TFETCH5_1_BYTE = 0,
 257         TFETCH5_2_BYTE = 1,
 258         TFETCH5_4_BYTE = 2,
 259         TFETCH5_8_BYTE = 3,
 260         TFETCH5_16_BYTE = 4,
 261 };
 262
 263 enum a5xx_depth_format {
 264         DEPTH5_NONE = 0,
 265         DEPTH5_16 = 1,
 266         DEPTH5_24_8 = 2,
 267         DEPTH5_32 = 4,
 268 };
 269
 270 enum a5xx_blit_buf {
 271         BLIT_MRT0 = 0,
 272         BLIT_MRT1 = 1,
 273         BLIT_MRT2 = 2,
 274         BLIT_MRT3 = 3,
 275         BLIT_MRT4 = 4,
 276         BLIT_MRT5 = 5,
 277         BLIT_MRT6 = 6,
 278         BLIT_MRT7 = 7,
 279         BLIT_ZS = 8,
 280         BLIT_S = 9,
 281 };
 282
 283 enum a5xx_cp_perfcounter_select {
 284         PERF_CP_ALWAYS_COUNT = 0,
 285         PERF_CP_BUSY_GFX_CORE_IDLE = 1,
 286         PERF_CP_BUSY_CYCLES = 2,
 287         PERF_CP_PFP_IDLE = 3,
 288         PERF_CP_PFP_BUSY_WORKING = 4,
 289         PERF_CP_PFP_STALL_CYCLES_ANY = 5,
 290         PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
 291         PERF_CP_PFP_ICACHE_MISS = 7,
 292         PERF_CP_PFP_ICACHE_HIT = 8,
 293         PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
 294         PERF_CP_ME_BUSY_WORKING = 10,
 295         PERF_CP_ME_IDLE = 11,
 296         PERF_CP_ME_STARVE_CYCLES_ANY = 12,
 297         PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
 298         PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
 299         PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
 300         PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
 301         PERF_CP_ME_STALL_CYCLES_ANY = 17,
 302         PERF_CP_ME_ICACHE_MISS = 18,
 303         PERF_CP_ME_ICACHE_HIT = 19,
 304         PERF_CP_NUM_PREEMPTIONS = 20,
 305         PERF_CP_PREEMPTION_REACTION_DELAY = 21,
 306         PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
 307         PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
 308         PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
 309         PERF_CP_PREDICATED_DRAWS_KILLED = 25,
 310         PERF_CP_MODE_SWITCH = 26,
 311         PERF_CP_ZPASS_DONE = 27,
 312         PERF_CP_CONTEXT_DONE = 28,
 313         PERF_CP_CACHE_FLUSH = 29,
 314         PERF_CP_LONG_PREEMPTIONS = 30,
 315 };
 316
 317 enum a5xx_rbbm_perfcounter_select {
 318         PERF_RBBM_ALWAYS_COUNT = 0,
 319         PERF_RBBM_ALWAYS_ON = 1,
 320         PERF_RBBM_TSE_BUSY = 2,
 321         PERF_RBBM_RAS_BUSY = 3,
 322         PERF_RBBM_PC_DCALL_BUSY = 4,
 323         PERF_RBBM_PC_VSD_BUSY = 5,
 324         PERF_RBBM_STATUS_MASKED = 6,
 325         PERF_RBBM_COM_BUSY = 7,
 326         PERF_RBBM_DCOM_BUSY = 8,
 327         PERF_RBBM_VBIF_BUSY = 9,
 328         PERF_RBBM_VSC_BUSY = 10,
 329         PERF_RBBM_TESS_BUSY = 11,
 330         PERF_RBBM_UCHE_BUSY = 12,
 331         PERF_RBBM_HLSQ_BUSY = 13,
 332 };
 333
 334 enum a5xx_pc_perfcounter_select {
 335         PERF_PC_BUSY_CYCLES = 0,
 336         PERF_PC_WORKING_CYCLES = 1,
 337         PERF_PC_STALL_CYCLES_VFD = 2,
 338         PERF_PC_STALL_CYCLES_TSE = 3,
 339         PERF_PC_STALL_CYCLES_VPC = 4,
 340         PERF_PC_STALL_CYCLES_UCHE = 5,
 341         PERF_PC_STALL_CYCLES_TESS = 6,
 342         PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
 343         PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
 344         PERF_PC_PASS1_TF_STALL_CYCLES = 9,
 345         PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
 346         PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
 347         PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
 348         PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
 349         PERF_PC_STARVE_CYCLES_DI = 14,
 350         PERF_PC_VIS_STREAMS_LOADED = 15,
 351         PERF_PC_INSTANCES = 16,
 352         PERF_PC_VPC_PRIMITIVES = 17,
 353         PERF_PC_DEAD_PRIM = 18,
 354         PERF_PC_LIVE_PRIM = 19,
 355         PERF_PC_VERTEX_HITS = 20,
 356         PERF_PC_IA_VERTICES = 21,
 357         PERF_PC_IA_PRIMITIVES = 22,
 358         PERF_PC_GS_PRIMITIVES = 23,
 359         PERF_PC_HS_INVOCATIONS = 24,
 360         PERF_PC_DS_INVOCATIONS = 25,
 361         PERF_PC_VS_INVOCATIONS = 26,
 362         PERF_PC_GS_INVOCATIONS = 27,
 363         PERF_PC_DS_PRIMITIVES = 28,
 364         PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
 365         PERF_PC_3D_DRAWCALLS = 30,
 366         PERF_PC_2D_DRAWCALLS = 31,
 367         PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
 368         PERF_TESS_BUSY_CYCLES = 33,
 369         PERF_TESS_WORKING_CYCLES = 34,
 370         PERF_TESS_STALL_CYCLES_PC = 35,
 371         PERF_TESS_STARVE_CYCLES_PC = 36,
 372 };
 373
 374 enum a5xx_vfd_perfcounter_select {
 375         PERF_VFD_BUSY_CYCLES = 0,
 376         PERF_VFD_STALL_CYCLES_UCHE = 1,
 377         PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
 378         PERF_VFD_STALL_CYCLES_MISS_VB = 3,
 379         PERF_VFD_STALL_CYCLES_MISS_Q = 4,
 380         PERF_VFD_STALL_CYCLES_SP_INFO = 5,
 381         PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
 382         PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
 383         PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
 384         PERF_VFD_DECODER_PACKER_STALL = 9,
 385         PERF_VFD_STARVE_CYCLES_UCHE = 10,
 386         PERF_VFD_RBUFFER_FULL = 11,
 387         PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
 388         PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
 389         PERF_VFD_NUM_ATTRIBUTES = 14,
 390         PERF_VFD_INSTRUCTIONS = 15,
 391         PERF_VFD_UPPER_SHADER_FIBERS = 16,
 392         PERF_VFD_LOWER_SHADER_FIBERS = 17,
 393         PERF_VFD_MODE_0_FIBERS = 18,
 394         PERF_VFD_MODE_1_FIBERS = 19,
 395         PERF_VFD_MODE_2_FIBERS = 20,
 396         PERF_VFD_MODE_3_FIBERS = 21,
 397         PERF_VFD_MODE_4_FIBERS = 22,
 398         PERF_VFD_TOTAL_VERTICES = 23,
 399         PERF_VFD_NUM_ATTR_MISS = 24,
 400         PERF_VFD_1_BURST_REQ = 25,
 401         PERF_VFDP_STALL_CYCLES_VFD = 26,
 402         PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
 403         PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
 404         PERF_VFDP_STARVE_CYCLES_PC = 29,
 405         PERF_VFDP_VS_STAGE_32_WAVES = 30,
 406 };
 407
 408 enum a5xx_hlsq_perfcounter_select {
 409         PERF_HLSQ_BUSY_CYCLES = 0,
 410         PERF_HLSQ_STALL_CYCLES_UCHE = 1,
 411         PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
 412         PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
 413         PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
 414         PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
 415         PERF_HLSQ_FS_STAGE_32_WAVES = 6,
 416         PERF_HLSQ_FS_STAGE_64_WAVES = 7,
 417         PERF_HLSQ_QUADS = 8,
 418         PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
 419         PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
 420         PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
 421         PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
 422         PERF_HLSQ_CS_INVOCATIONS = 13,
 423         PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
 424 };
 425
 426 enum a5xx_vpc_perfcounter_select {
 427         PERF_VPC_BUSY_CYCLES = 0,
 428         PERF_VPC_WORKING_CYCLES = 1,
 429         PERF_VPC_STALL_CYCLES_UCHE = 2,
 430         PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
 431         PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
 432         PERF_VPC_STALL_CYCLES_PC = 5,
 433         PERF_VPC_STALL_CYCLES_SP_LM = 6,
 434         PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
 435         PERF_VPC_STARVE_CYCLES_SP = 8,
 436         PERF_VPC_STARVE_CYCLES_LRZ = 9,
 437         PERF_VPC_PC_PRIMITIVES = 10,
 438         PERF_VPC_SP_COMPONENTS = 11,
 439         PERF_VPC_SP_LM_PRIMITIVES = 12,
 440         PERF_VPC_SP_LM_COMPONENTS = 13,
 441         PERF_VPC_SP_LM_DWORDS = 14,
 442         PERF_VPC_STREAMOUT_COMPONENTS = 15,
 443         PERF_VPC_GRANT_PHASES = 16,
 444 };
 445
 446 enum a5xx_tse_perfcounter_select {
 447         PERF_TSE_BUSY_CYCLES = 0,
 448         PERF_TSE_CLIPPING_CYCLES = 1,
 449         PERF_TSE_STALL_CYCLES_RAS = 2,
 450         PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
 451         PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
 452         PERF_TSE_STARVE_CYCLES_PC = 5,
 453         PERF_TSE_INPUT_PRIM = 6,
 454         PERF_TSE_INPUT_NULL_PRIM = 7,
 455         PERF_TSE_TRIVAL_REJ_PRIM = 8,
 456         PERF_TSE_CLIPPED_PRIM = 9,
 457         PERF_TSE_ZERO_AREA_PRIM = 10,
 458         PERF_TSE_FACENESS_CULLED_PRIM = 11,
 459         PERF_TSE_ZERO_PIXEL_PRIM = 12,
 460         PERF_TSE_OUTPUT_NULL_PRIM = 13,
 461         PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
 462         PERF_TSE_CINVOCATION = 15,
 463         PERF_TSE_CPRIMITIVES = 16,
 464         PERF_TSE_2D_INPUT_PRIM = 17,
 465         PERF_TSE_2D_ALIVE_CLCLES = 18,
 466 };
 467
 468 enum a5xx_ras_perfcounter_select {
 469         PERF_RAS_BUSY_CYCLES = 0,
 470         PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
 471         PERF_RAS_STALL_CYCLES_LRZ = 2,
 472         PERF_RAS_STARVE_CYCLES_TSE = 3,
 473         PERF_RAS_SUPER_TILES = 4,
 474         PERF_RAS_8X4_TILES = 5,
 475         PERF_RAS_MASKGEN_ACTIVE = 6,
 476         PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
 477         PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
 478         PERF_RAS_PRIM_KILLED_INVISILBE = 9,
 479 };
 480
 481 enum a5xx_lrz_perfcounter_select {
 482         PERF_LRZ_BUSY_CYCLES = 0,
 483         PERF_LRZ_STARVE_CYCLES_RAS = 1,
 484         PERF_LRZ_STALL_CYCLES_RB = 2,
 485         PERF_LRZ_STALL_CYCLES_VSC = 3,
 486         PERF_LRZ_STALL_CYCLES_VPC = 4,
 487         PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
 488         PERF_LRZ_STALL_CYCLES_UCHE = 6,
 489         PERF_LRZ_LRZ_READ = 7,
 490         PERF_LRZ_LRZ_WRITE = 8,
 491         PERF_LRZ_READ_LATENCY = 9,
 492         PERF_LRZ_MERGE_CACHE_UPDATING = 10,
 493         PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
 494         PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
 495         PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
 496         PERF_LRZ_FULL_8X8_TILES = 14,
 497         PERF_LRZ_PARTIAL_8X8_TILES = 15,
 498         PERF_LRZ_TILE_KILLED = 16,
 499         PERF_LRZ_TOTAL_PIXEL = 17,
 500         PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
 501 };
 502
 503 enum a5xx_uche_perfcounter_select {
 504         PERF_UCHE_BUSY_CYCLES = 0,
 505         PERF_UCHE_STALL_CYCLES_VBIF = 1,
 506         PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
 507         PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
 508         PERF_UCHE_VBIF_READ_BEATS_TP = 4,
 509         PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
 510         PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
 511         PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
 512         PERF_UCHE_VBIF_READ_BEATS_SP = 8,
 513         PERF_UCHE_READ_REQUESTS_TP = 9,
 514         PERF_UCHE_READ_REQUESTS_VFD = 10,
 515         PERF_UCHE_READ_REQUESTS_HLSQ = 11,
 516         PERF_UCHE_READ_REQUESTS_LRZ = 12,
 517         PERF_UCHE_READ_REQUESTS_SP = 13,
 518         PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
 519         PERF_UCHE_WRITE_REQUESTS_SP = 15,
 520         PERF_UCHE_WRITE_REQUESTS_VPC = 16,
 521         PERF_UCHE_WRITE_REQUESTS_VSC = 17,
 522         PERF_UCHE_EVICTS = 18,
 523         PERF_UCHE_BANK_REQ0 = 19,
 524         PERF_UCHE_BANK_REQ1 = 20,
 525         PERF_UCHE_BANK_REQ2 = 21,
 526         PERF_UCHE_BANK_REQ3 = 22,
 527         PERF_UCHE_BANK_REQ4 = 23,
 528         PERF_UCHE_BANK_REQ5 = 24,
 529         PERF_UCHE_BANK_REQ6 = 25,
 530         PERF_UCHE_BANK_REQ7 = 26,
 531         PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
 532         PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
 533         PERF_UCHE_GMEM_READ_BEATS = 29,
 534         PERF_UCHE_FLAG_COUNT = 30,
 535 };
 536
 537 enum a5xx_tp_perfcounter_select {
 538         PERF_TP_BUSY_CYCLES = 0,
 539         PERF_TP_STALL_CYCLES_UCHE = 1,
 540         PERF_TP_LATENCY_CYCLES = 2,
 541         PERF_TP_LATENCY_TRANS = 3,
 542         PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
 543         PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
 544         PERF_TP_L1_CACHELINE_REQUESTS = 6,
 545         PERF_TP_L1_CACHELINE_MISSES = 7,
 546         PERF_TP_SP_TP_TRANS = 8,
 547         PERF_TP_TP_SP_TRANS = 9,
 548         PERF_TP_OUTPUT_PIXELS = 10,
 549         PERF_TP_FILTER_WORKLOAD_16BIT = 11,
 550         PERF_TP_FILTER_WORKLOAD_32BIT = 12,
 551         PERF_TP_QUADS_RECEIVED = 13,
 552         PERF_TP_QUADS_OFFSET = 14,
 553         PERF_TP_QUADS_SHADOW = 15,
 554         PERF_TP_QUADS_ARRAY = 16,
 555         PERF_TP_QUADS_GRADIENT = 17,
 556         PERF_TP_QUADS_1D = 18,
 557         PERF_TP_QUADS_2D = 19,
 558         PERF_TP_QUADS_BUFFER = 20,
 559         PERF_TP_QUADS_3D = 21,
 560         PERF_TP_QUADS_CUBE = 22,
 561         PERF_TP_STATE_CACHE_REQUESTS = 23,
 562         PERF_TP_STATE_CACHE_MISSES = 24,
 563         PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
 564         PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
 565         PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
 566         PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
 567         PERF_TP_OUTPUT_PIXELS_POINT = 29,
 568         PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
 569         PERF_TP_OUTPUT_PIXELS_MIP = 31,
 570         PERF_TP_OUTPUT_PIXELS_ANISO = 32,
 571         PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
 572         PERF_TP_FLAG_CACHE_REQUESTS = 34,
 573         PERF_TP_FLAG_CACHE_MISSES = 35,
 574         PERF_TP_L1_5_L2_REQUESTS = 36,
 575         PERF_TP_2D_OUTPUT_PIXELS = 37,
 576         PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
 577         PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
 578         PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
 579         PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
 580 };
 581
 582 enum a5xx_sp_perfcounter_select {
 583         PERF_SP_BUSY_CYCLES = 0,
 584         PERF_SP_ALU_WORKING_CYCLES = 1,
 585         PERF_SP_EFU_WORKING_CYCLES = 2,
 586         PERF_SP_STALL_CYCLES_VPC = 3,
 587         PERF_SP_STALL_CYCLES_TP = 4,
 588         PERF_SP_STALL_CYCLES_UCHE = 5,
 589         PERF_SP_STALL_CYCLES_RB = 6,
 590         PERF_SP_SCHEDULER_NON_WORKING = 7,
 591         PERF_SP_WAVE_CONTEXTS = 8,
 592         PERF_SP_WAVE_CONTEXT_CYCLES = 9,
 593         PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
 594         PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
 595         PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
 596         PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
 597         PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
 598         PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
 599         PERF_SP_WAVE_CTRL_CYCLES = 16,
 600         PERF_SP_WAVE_LOAD_CYCLES = 17,
 601         PERF_SP_WAVE_EMIT_CYCLES = 18,
 602         PERF_SP_WAVE_NOP_CYCLES = 19,
 603         PERF_SP_WAVE_WAIT_CYCLES = 20,
 604         PERF_SP_WAVE_FETCH_CYCLES = 21,
 605         PERF_SP_WAVE_IDLE_CYCLES = 22,
 606         PERF_SP_WAVE_END_CYCLES = 23,
 607         PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
 608         PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
 609         PERF_SP_WAVE_JOIN_CYCLES = 26,
 610         PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
 611         PERF_SP_LM_STORE_INSTRUCTIONS = 28,
 612         PERF_SP_LM_ATOMICS = 29,
 613         PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
 614         PERF_SP_GM_STORE_INSTRUCTIONS = 31,
 615         PERF_SP_GM_ATOMICS = 32,
 616         PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
 617         PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
 618         PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
 619         PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
 620         PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
 621         PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
 622         PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
 623         PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
 624         PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
 625         PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
 626         PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
 627         PERF_SP_VS_INSTRUCTIONS = 44,
 628         PERF_SP_FS_INSTRUCTIONS = 45,
 629         PERF_SP_ADDR_LOCK_COUNT = 46,
 630         PERF_SP_UCHE_READ_TRANS = 47,
 631         PERF_SP_UCHE_WRITE_TRANS = 48,
 632         PERF_SP_EXPORT_VPC_TRANS = 49,
 633         PERF_SP_EXPORT_RB_TRANS = 50,
 634         PERF_SP_PIXELS_KILLED = 51,
 635         PERF_SP_ICL1_REQUESTS = 52,
 636         PERF_SP_ICL1_MISSES = 53,
 637         PERF_SP_ICL0_REQUESTS = 54,
 638         PERF_SP_ICL0_MISSES = 55,
 639         PERF_SP_HS_INSTRUCTIONS = 56,
 640         PERF_SP_DS_INSTRUCTIONS = 57,
 641         PERF_SP_GS_INSTRUCTIONS = 58,
 642         PERF_SP_CS_INSTRUCTIONS = 59,
 643         PERF_SP_GPR_READ = 60,
 644         PERF_SP_GPR_WRITE = 61,
 645         PERF_SP_LM_CH0_REQUESTS = 62,
 646         PERF_SP_LM_CH1_REQUESTS = 63,
 647         PERF_SP_LM_BANK_CONFLICTS = 64,
 648 };
 649
 650 enum a5xx_rb_perfcounter_select {
 651         PERF_RB_BUSY_CYCLES = 0,
 652         PERF_RB_STALL_CYCLES_CCU = 1,
 653         PERF_RB_STALL_CYCLES_HLSQ = 2,
 654         PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
 655         PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
 656         PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
 657         PERF_RB_STARVE_CYCLES_SP = 6,
 658         PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
 659         PERF_RB_STARVE_CYCLES_CCU = 8,
 660         PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
 661         PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
 662         PERF_RB_Z_WORKLOAD = 11,
 663         PERF_RB_HLSQ_ACTIVE = 12,
 664         PERF_RB_Z_READ = 13,
 665         PERF_RB_Z_WRITE = 14,
 666         PERF_RB_C_READ = 15,
 667         PERF_RB_C_WRITE = 16,
 668         PERF_RB_TOTAL_PASS = 17,
 669         PERF_RB_Z_PASS = 18,
 670         PERF_RB_Z_FAIL = 19,
 671         PERF_RB_S_FAIL = 20,
 672         PERF_RB_BLENDED_FXP_COMPONENTS = 21,
 673         PERF_RB_BLENDED_FP16_COMPONENTS = 22,
 674         RB_RESERVED = 23,
 675         PERF_RB_2D_ALIVE_CYCLES = 24,
 676         PERF_RB_2D_STALL_CYCLES_A2D = 25,
 677         PERF_RB_2D_STARVE_CYCLES_SRC = 26,
 678         PERF_RB_2D_STARVE_CYCLES_SP = 27,
 679         PERF_RB_2D_STARVE_CYCLES_DST = 28,
 680         PERF_RB_2D_VALID_PIXELS = 29,
 681 };
 682
 683 enum a5xx_rb_samples_perfcounter_select {
 684         TOTAL_SAMPLES = 0,
 685         ZPASS_SAMPLES = 1,
 686         ZFAIL_SAMPLES = 2,
 687         SFAIL_SAMPLES = 3,
 688 };
 689
 690 enum a5xx_vsc_perfcounter_select {
 691         PERF_VSC_BUSY_CYCLES = 0,
 692         PERF_VSC_WORKING_CYCLES = 1,
 693         PERF_VSC_STALL_CYCLES_UCHE = 2,
 694         PERF_VSC_EOT_NUM = 3,
 695 };
 696
 697 enum a5xx_ccu_perfcounter_select {
 698         PERF_CCU_BUSY_CYCLES = 0,
 699         PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
 700         PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
 701         PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
 702         PERF_CCU_DEPTH_BLOCKS = 4,
 703         PERF_CCU_COLOR_BLOCKS = 5,
 704         PERF_CCU_DEPTH_BLOCK_HIT = 6,
 705         PERF_CCU_COLOR_BLOCK_HIT = 7,
 706         PERF_CCU_PARTIAL_BLOCK_READ = 8,
 707         PERF_CCU_GMEM_READ = 9,
 708         PERF_CCU_GMEM_WRITE = 10,
 709         PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
 710         PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
 711         PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
 712         PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
 713         PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
 714         PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
 715         PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
 716         PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
 717         PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
 718         PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
 719         PERF_CCU_2D_BUSY_CYCLES = 21,
 720         PERF_CCU_2D_RD_REQ = 22,
 721         PERF_CCU_2D_WR_REQ = 23,
 722         PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
 723         PERF_CCU_2D_PIXELS = 25,
 724 };
 725
 726 enum a5xx_cmp_perfcounter_select {
 727         PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
 728         PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
 729         PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
 730         PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
 731         PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
 732         PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
 733         PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
 734         PERF_CMPDECMP_VBIF_READ_DATA = 7,
 735         PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
 736         PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
 737         PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
 738         PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
 739         PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
 740         PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
 741         PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
 742         PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
 743         PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
 744         PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
 745         PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
 746         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
 747         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
 748         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
 749         PERF_CMPDECMP_2D_RD_DATA = 22,
 750         PERF_CMPDECMP_2D_WR_DATA = 23,
 751 };
 752
 753 enum a5xx_vbif_perfcounter_select {
 754         AXI_READ_REQUESTS_ID_0 = 0,
 755         AXI_READ_REQUESTS_ID_1 = 1,
 756         AXI_READ_REQUESTS_ID_2 = 2,
 757         AXI_READ_REQUESTS_ID_3 = 3,
 758         AXI_READ_REQUESTS_ID_4 = 4,
 759         AXI_READ_REQUESTS_ID_5 = 5,
 760         AXI_READ_REQUESTS_ID_6 = 6,
 761         AXI_READ_REQUESTS_ID_7 = 7,
 762         AXI_READ_REQUESTS_ID_8 = 8,
 763         AXI_READ_REQUESTS_ID_9 = 9,
 764         AXI_READ_REQUESTS_ID_10 = 10,
 765         AXI_READ_REQUESTS_ID_11 = 11,
 766         AXI_READ_REQUESTS_ID_12 = 12,
 767         AXI_READ_REQUESTS_ID_13 = 13,
 768         AXI_READ_REQUESTS_ID_14 = 14,
 769         AXI_READ_REQUESTS_ID_15 = 15,
 770         AXI0_READ_REQUESTS_TOTAL = 16,
 771         AXI1_READ_REQUESTS_TOTAL = 17,
 772         AXI2_READ_REQUESTS_TOTAL = 18,
 773         AXI3_READ_REQUESTS_TOTAL = 19,
 774         AXI_READ_REQUESTS_TOTAL = 20,
 775         AXI_WRITE_REQUESTS_ID_0 = 21,
 776         AXI_WRITE_REQUESTS_ID_1 = 22,
 777         AXI_WRITE_REQUESTS_ID_2 = 23,
 778         AXI_WRITE_REQUESTS_ID_3 = 24,
 779         AXI_WRITE_REQUESTS_ID_4 = 25,
 780         AXI_WRITE_REQUESTS_ID_5 = 26,
 781         AXI_WRITE_REQUESTS_ID_6 = 27,
 782         AXI_WRITE_REQUESTS_ID_7 = 28,
 783         AXI_WRITE_REQUESTS_ID_8 = 29,
 784         AXI_WRITE_REQUESTS_ID_9 = 30,
 785         AXI_WRITE_REQUESTS_ID_10 = 31,
 786         AXI_WRITE_REQUESTS_ID_11 = 32,
 787         AXI_WRITE_REQUESTS_ID_12 = 33,
 788         AXI_WRITE_REQUESTS_ID_13 = 34,
 789         AXI_WRITE_REQUESTS_ID_14 = 35,
 790         AXI_WRITE_REQUESTS_ID_15 = 36,
 791         AXI0_WRITE_REQUESTS_TOTAL = 37,
 792         AXI1_WRITE_REQUESTS_TOTAL = 38,
 793         AXI2_WRITE_REQUESTS_TOTAL = 39,
 794         AXI3_WRITE_REQUESTS_TOTAL = 40,
 795         AXI_WRITE_REQUESTS_TOTAL = 41,
 796         AXI_TOTAL_REQUESTS = 42,
 797         AXI_READ_DATA_BEATS_ID_0 = 43,
 798         AXI_READ_DATA_BEATS_ID_1 = 44,
 799         AXI_READ_DATA_BEATS_ID_2 = 45,
 800         AXI_READ_DATA_BEATS_ID_3 = 46,
 801         AXI_READ_DATA_BEATS_ID_4 = 47,
 802         AXI_READ_DATA_BEATS_ID_5 = 48,
 803         AXI_READ_DATA_BEATS_ID_6 = 49,
 804         AXI_READ_DATA_BEATS_ID_7 = 50,
 805         AXI_READ_DATA_BEATS_ID_8 = 51,
 806         AXI_READ_DATA_BEATS_ID_9 = 52,
 807         AXI_READ_DATA_BEATS_ID_10 = 53,
 808         AXI_READ_DATA_BEATS_ID_11 = 54,
 809         AXI_READ_DATA_BEATS_ID_12 = 55,
 810         AXI_READ_DATA_BEATS_ID_13 = 56,
 811         AXI_READ_DATA_BEATS_ID_14 = 57,
 812         AXI_READ_DATA_BEATS_ID_15 = 58,
 813         AXI0_READ_DATA_BEATS_TOTAL = 59,
 814         AXI1_READ_DATA_BEATS_TOTAL = 60,
 815         AXI2_READ_DATA_BEATS_TOTAL = 61,
 816         AXI3_READ_DATA_BEATS_TOTAL = 62,
 817         AXI_READ_DATA_BEATS_TOTAL = 63,
 818         AXI_WRITE_DATA_BEATS_ID_0 = 64,
 819         AXI_WRITE_DATA_BEATS_ID_1 = 65,
 820         AXI_WRITE_DATA_BEATS_ID_2 = 66,
 821         AXI_WRITE_DATA_BEATS_ID_3 = 67,
 822         AXI_WRITE_DATA_BEATS_ID_4 = 68,
 823         AXI_WRITE_DATA_BEATS_ID_5 = 69,
 824         AXI_WRITE_DATA_BEATS_ID_6 = 70,
 825         AXI_WRITE_DATA_BEATS_ID_7 = 71,
 826         AXI_WRITE_DATA_BEATS_ID_8 = 72,
 827         AXI_WRITE_DATA_BEATS_ID_9 = 73,
 828         AXI_WRITE_DATA_BEATS_ID_10 = 74,
 829         AXI_WRITE_DATA_BEATS_ID_11 = 75,
 830         AXI_WRITE_DATA_BEATS_ID_12 = 76,
 831         AXI_WRITE_DATA_BEATS_ID_13 = 77,
 832         AXI_WRITE_DATA_BEATS_ID_14 = 78,
 833         AXI_WRITE_DATA_BEATS_ID_15 = 79,
 834         AXI0_WRITE_DATA_BEATS_TOTAL = 80,
 835         AXI1_WRITE_DATA_BEATS_TOTAL = 81,
 836         AXI2_WRITE_DATA_BEATS_TOTAL = 82,
 837         AXI3_WRITE_DATA_BEATS_TOTAL = 83,
 838         AXI_WRITE_DATA_BEATS_TOTAL = 84,
 839         AXI_DATA_BEATS_TOTAL = 85,
 840 };
 841
 842 enum a5xx_tex_filter {
 843         A5XX_TEX_NEAREST = 0,
 844         A5XX_TEX_LINEAR = 1,
 845         A5XX_TEX_ANISO = 2,
 846 };
 847
 848 enum a5xx_tex_clamp {
 849         A5XX_TEX_REPEAT = 0,
 850         A5XX_TEX_CLAMP_TO_EDGE = 1,
 851         A5XX_TEX_MIRROR_REPEAT = 2,
 852         A5XX_TEX_CLAMP_TO_BORDER = 3,
 853         A5XX_TEX_MIRROR_CLAMP = 4,
 854 };
 855
 856 enum a5xx_tex_aniso {
 857         A5XX_TEX_ANISO_1 = 0,
 858         A5XX_TEX_ANISO_2 = 1,
 859         A5XX_TEX_ANISO_4 = 2,
 860         A5XX_TEX_ANISO_8 = 3,
 861         A5XX_TEX_ANISO_16 = 4,
 862 };
 863
 864 enum a5xx_tex_swiz {
 865         A5XX_TEX_X = 0,
 866         A5XX_TEX_Y = 1,
 867         A5XX_TEX_Z = 2,
 868         A5XX_TEX_W = 3,
 869         A5XX_TEX_ZERO = 4,
 870         A5XX_TEX_ONE = 5,
 871 };
 872
 873 enum a5xx_tex_type {
 874         A5XX_TEX_1D = 0,
 875         A5XX_TEX_2D = 1,
 876         A5XX_TEX_CUBE = 2,
 877         A5XX_TEX_3D = 3,
 878 };
 879
 880 #define A5XX_INT0_RBBM_GPU_IDLE                                 0x00000001
 881 #define A5XX_INT0_RBBM_AHB_ERROR                                0x00000002
 882 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT                         0x00000004
 883 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT                            0x00000008
 884 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT                           0x00000010
 885 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT                           0x00000020
 886 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW                       0x00000040
 887 #define A5XX_INT0_RBBM_GPC_ERROR                                0x00000080
 888 #define A5XX_INT0_CP_SW                                         0x00000100
 889 #define A5XX_INT0_CP_HW_ERROR                                   0x00000200
 890 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS                         0x00000400
 891 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS                         0x00000800
 892 #define A5XX_INT0_CP_CCU_RESOLVE_TS                             0x00001000
 893 #define A5XX_INT0_CP_IB2                                        0x00002000
 894 #define A5XX_INT0_CP_IB1                                        0x00004000
 895 #define A5XX_INT0_CP_RB                                         0x00008000
 896 #define A5XX_INT0_CP_UNUSED_1                                   0x00010000
 897 #define A5XX_INT0_CP_RB_DONE_TS                                 0x00020000
 898 #define A5XX_INT0_CP_WT_DONE_TS                                 0x00040000
 899 #define A5XX_INT0_UNKNOWN_1                                     0x00080000
 900 #define A5XX_INT0_CP_CACHE_FLUSH_TS                             0x00100000
 901 #define A5XX_INT0_UNUSED_2                                      0x00200000
 902 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW                         0x00400000
 903 #define A5XX_INT0_MISC_HANG_DETECT                              0x00800000
 904 #define A5XX_INT0_UCHE_OOB_ACCESS                               0x01000000
 905 #define A5XX_INT0_UCHE_TRAP_INTR                                0x02000000
 906 #define A5XX_INT0_DEBBUS_INTR_0                                 0x04000000
 907 #define A5XX_INT0_DEBBUS_INTR_1                                 0x08000000
 908 #define A5XX_INT0_GPMU_VOLTAGE_DROOP                            0x10000000
 909 #define A5XX_INT0_GPMU_FIRMWARE                                 0x20000000
 910 #define A5XX_INT0_ISDB_CPU_IRQ                                  0x40000000
 911 #define A5XX_INT0_ISDB_UNDER_DEBUG                              0x80000000
 912 #define A5XX_CP_INT_CP_OPCODE_ERROR                             0x00000001
 913 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR                       0x00000002
 914 #define A5XX_CP_INT_CP_HW_FAULT_ERROR                           0x00000004
 915 #define A5XX_CP_INT_CP_DMA_ERROR                                0x00000008
 916 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR                0x00000010
 917 #define A5XX_CP_INT_CP_AHB_ERROR                                0x00000020
 918 #define REG_A5XX_CP_RB_BASE                                     0x00000800
 919
 920 #define REG_A5XX_CP_RB_BASE_HI                                  0x00000801
 921
 922 #define REG_A5XX_CP_RB_CNTL                                     0x00000802
 923
 924 #define REG_A5XX_CP_RB_RPTR_ADDR                                0x00000804
 925
 926 #define REG_A5XX_CP_RB_RPTR_ADDR_HI                             0x00000805
 927
 928 #define REG_A5XX_CP_RB_RPTR                                     0x00000806
 929
 930 #define REG_A5XX_CP_RB_WPTR                                     0x00000807
 931
 932 #define REG_A5XX_CP_PFP_STAT_ADDR                               0x00000808
 933
 934 #define REG_A5XX_CP_PFP_STAT_DATA                               0x00000809
 935
 936 #define REG_A5XX_CP_DRAW_STATE_ADDR                             0x0000080b
 937
 938 #define REG_A5XX_CP_DRAW_STATE_DATA                             0x0000080c
 939
 940 #define REG_A5XX_CP_ME_NRT_ADDR_LO                              0x0000080d
 941
 942 #define REG_A5XX_CP_ME_NRT_ADDR_HI                              0x0000080e
 943
 944 #define REG_A5XX_CP_ME_NRT_DATA                                 0x00000810
 945
 946 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO                        0x00000817
 947
 948 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI                        0x00000818
 949
 950 #define REG_A5XX_CP_CRASH_DUMP_CNTL                             0x00000819
 951
 952 #define REG_A5XX_CP_ME_STAT_ADDR                                0x0000081a
 953
 954 #define REG_A5XX_CP_ROQ_THRESHOLDS_1                            0x0000081f
 955
 956 #define REG_A5XX_CP_ROQ_THRESHOLDS_2                            0x00000820
 957
 958 #define REG_A5XX_CP_ROQ_DBG_ADDR                                0x00000821
 959
 960 #define REG_A5XX_CP_ROQ_DBG_DATA                                0x00000822
 961
 962 #define REG_A5XX_CP_MEQ_DBG_ADDR                                0x00000823
 963
 964 #define REG_A5XX_CP_MEQ_DBG_DATA                                0x00000824
 965
 966 #define REG_A5XX_CP_MEQ_THRESHOLDS                              0x00000825
 967
 968 #define REG_A5XX_CP_MERCIU_SIZE                                 0x00000826
 969
 970 #define REG_A5XX_CP_MERCIU_DBG_ADDR                             0x00000827
 971
 972 #define REG_A5XX_CP_MERCIU_DBG_DATA_1                           0x00000828
 973
 974 #define REG_A5XX_CP_MERCIU_DBG_DATA_2                           0x00000829
 975
 976 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR                          0x0000082a
 977
 978 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA                          0x0000082b
 979
 980 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR                           0x0000082f
 981
 982 #define REG_A5XX_CP_ME_UCODE_DBG_DATA                           0x00000830
 983
 984 #define REG_A5XX_CP_CNTL                                        0x00000831
 985
 986 #define REG_A5XX_CP_PFP_ME_CNTL                                 0x00000832
 987
 988 #define REG_A5XX_CP_CHICKEN_DBG                                 0x00000833
 989
 990 #define REG_A5XX_CP_PFP_INSTR_BASE_LO                           0x00000835
 991
 992 #define REG_A5XX_CP_PFP_INSTR_BASE_HI                           0x00000836
 993
 994 #define REG_A5XX_CP_ME_INSTR_BASE_LO                            0x00000838
 995
 996 #define REG_A5XX_CP_ME_INSTR_BASE_HI                            0x00000839
 997
 998 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL                         0x0000083b
 999
1000 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO              0x0000083c
1001
1002 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI              0x0000083d
1003
1004 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO                 0x0000083e
1005
1006 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI                 0x0000083f
1007
1008 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO                 0x00000840
1009
1010 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI                 0x00000841
1011
1012 #define REG_A5XX_CP_ADDR_MODE_CNTL                              0x00000860
1013
1014 #define REG_A5XX_CP_ME_STAT_DATA                                0x00000b14
1015
1016 #define REG_A5XX_CP_WFI_PEND_CTR                                0x00000b15
1017
1018 #define REG_A5XX_CP_INTERRUPT_STATUS                            0x00000b18
1019
1020 #define REG_A5XX_CP_HW_FAULT                                    0x00000b1a
1021
1022 #define REG_A5XX_CP_PROTECT_STATUS                              0x00000b1c
1023
1024 #define REG_A5XX_CP_IB1_BASE                                    0x00000b1f
1025
1026 #define REG_A5XX_CP_IB1_BASE_HI                                 0x00000b20
1027
1028 #define REG_A5XX_CP_IB1_BUFSZ                                   0x00000b21
1029
1030 #define REG_A5XX_CP_IB2_BASE                                    0x00000b22
1031
1032 #define REG_A5XX_CP_IB2_BASE_HI                                 0x00000b23
1033
1034 #define REG_A5XX_CP_IB2_BUFSZ                                   0x00000b24
1035
1036 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1037
1038 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1039
1040 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1041
1042 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1043 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK                     0x0001ffff
1044 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT                    0
1045 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1046 {
1047         return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1048 }
1049 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK                      0x1f000000
1050 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT                     24
1051 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1052 {
1053         return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
1054 }
1055 #define A5XX_CP_PROTECT_REG_TRAP_WRITE                          0x20000000
1056 #define A5XX_CP_PROTECT_REG_TRAP_READ                           0x40000000
1057
1058 #define REG_A5XX_CP_PROTECT_CNTL                                0x000008a0
1059
1060 #define REG_A5XX_CP_AHB_FAULT                                   0x00000b1b
1061
1062 #define REG_A5XX_CP_PERFCTR_CP_SEL_0                            0x00000bb0
1063
1064 #define REG_A5XX_CP_PERFCTR_CP_SEL_1                            0x00000bb1
1065
1066 #define REG_A5XX_CP_PERFCTR_CP_SEL_2                            0x00000bb2
1067
1068 #define REG_A5XX_CP_PERFCTR_CP_SEL_3                            0x00000bb3
1069
1070 #define REG_A5XX_CP_PERFCTR_CP_SEL_4                            0x00000bb4
1071
1072 #define REG_A5XX_CP_PERFCTR_CP_SEL_5                            0x00000bb5
1073
1074 #define REG_A5XX_CP_PERFCTR_CP_SEL_6                            0x00000bb6
1075
1076 #define REG_A5XX_CP_PERFCTR_CP_SEL_7                            0x00000bb7
1077
1078 #define REG_A5XX_VSC_ADDR_MODE_CNTL                             0x00000bc1
1079
1080 #define REG_A5XX_CP_POWERCTR_CP_SEL_0                           0x00000bba
1081
1082 #define REG_A5XX_CP_POWERCTR_CP_SEL_1                           0x00000bbb
1083
1084 #define REG_A5XX_CP_POWERCTR_CP_SEL_2                           0x00000bbc
1085
1086 #define REG_A5XX_CP_POWERCTR_CP_SEL_3                           0x00000bbd
1087
1088 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A                          0x00000004
1089
1090 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B                          0x00000005
1091
1092 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C                          0x00000006
1093
1094 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D                          0x00000007
1095
1096 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT                          0x00000008
1097
1098 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM                          0x00000009
1099
1100 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT             0x00000018
1101
1102 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL                            0x0000000a
1103
1104 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE                            0x0000000b
1105
1106 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0                         0x0000000c
1107
1108 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1                         0x0000000d
1109
1110 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2                         0x0000000e
1111
1112 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3                         0x0000000f
1113
1114 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0                        0x00000010
1115
1116 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1                        0x00000011
1117
1118 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2                        0x00000012
1119
1120 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3                        0x00000013
1121
1122 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0                        0x00000014
1123
1124 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1                        0x00000015
1125
1126 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0                         0x00000016
1127
1128 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1                         0x00000017
1129
1130 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2                         0x00000018
1131
1132 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3                         0x00000019
1133
1134 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0                        0x0000001a
1135
1136 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1                        0x0000001b
1137
1138 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2                        0x0000001c
1139
1140 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3                        0x0000001d
1141
1142 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE                        0x0000001e
1143
1144 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0                          0x0000001f
1145
1146 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1                          0x00000020
1147
1148 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG                        0x00000021
1149
1150 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX                            0x00000022
1151
1152 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC                           0x00000023
1153
1154 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT                        0x00000024
1155
1156 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL                   0x0000002f
1157
1158 #define REG_A5XX_RBBM_INT_CLEAR_CMD                             0x00000037
1159
1160 #define REG_A5XX_RBBM_INT_0_MASK                                0x00000038
1161 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE                      0x00000001
1162 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR                     0x00000002
1163 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT              0x00000004
1164 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT                 0x00000008
1165 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT                0x00000010
1166 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT                0x00000020
1167 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW            0x00000040
1168 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR                     0x00000080
1169 #define A5XX_RBBM_INT_0_MASK_CP_SW                              0x00000100
1170 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR                        0x00000200
1171 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS              0x00000400
1172 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS              0x00000800
1173 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS                  0x00001000
1174 #define A5XX_RBBM_INT_0_MASK_CP_IB2                             0x00002000
1175 #define A5XX_RBBM_INT_0_MASK_CP_IB1                             0x00004000
1176 #define A5XX_RBBM_INT_0_MASK_CP_RB                              0x00008000
1177 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS                      0x00020000
1178 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS                      0x00040000
1179 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS                  0x00100000
1180 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW              0x00400000
1181 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT                   0x00800000
1182 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS                    0x01000000
1183 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR                     0x02000000
1184 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0                      0x04000000
1185 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1                      0x08000000
1186 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP                 0x10000000
1187 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE                      0x20000000
1188 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ                       0x40000000
1189 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG                   0x80000000
1190
1191 #define REG_A5XX_RBBM_AHB_DBG_CNTL                              0x0000003f
1192
1193 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL                         0x00000041
1194
1195 #define REG_A5XX_RBBM_SW_RESET_CMD                              0x00000043
1196
1197 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD                        0x00000045
1198
1199 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2                       0x00000046
1200
1201 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO                            0x00000048
1202
1203 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL                        0x00000049
1204
1205 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0                            0x0000004a
1206
1207 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1                            0x0000004b
1208
1209 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2                            0x0000004c
1210
1211 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3                            0x0000004d
1212
1213 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0                           0x0000004e
1214
1215 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1                           0x0000004f
1216
1217 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2                           0x00000050
1218
1219 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3                           0x00000051
1220
1221 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0                           0x00000052
1222
1223 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1                           0x00000053
1224
1225 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2                           0x00000054
1226
1227 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3                           0x00000055
1228
1229 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG                      0x00000059
1230
1231 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE                           0x0000005a
1232
1233 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE                          0x0000005b
1234
1235 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE                          0x0000005c
1236
1237 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE                          0x0000005d
1238
1239 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE                           0x0000005e
1240
1241 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE                          0x0000005f
1242
1243 #define REG_A5XX_RBBM_CLOCK_MODE_GPC                            0x00000060
1244
1245 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC                           0x00000061
1246
1247 #define REG_A5XX_RBBM_CLOCK_HYST_GPC                            0x00000062
1248
1249 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM                   0x00000063
1250
1251 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM                   0x00000064
1252
1253 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM                  0x00000065
1254
1255 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ                          0x00000066
1256
1257 #define REG_A5XX_RBBM_CLOCK_CNTL                                0x00000067
1258
1259 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0                            0x00000068
1260
1261 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1                            0x00000069
1262
1263 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2                            0x0000006a
1264
1265 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3                            0x0000006b
1266
1267 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0                           0x0000006c
1268
1269 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1                           0x0000006d
1270
1271 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2                           0x0000006e
1272
1273 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3                           0x0000006f
1274
1275 #define REG_A5XX_RBBM_CLOCK_HYST_SP0                            0x00000070
1276
1277 #define REG_A5XX_RBBM_CLOCK_HYST_SP1                            0x00000071
1278
1279 #define REG_A5XX_RBBM_CLOCK_HYST_SP2                            0x00000072
1280
1281 #define REG_A5XX_RBBM_CLOCK_HYST_SP3                            0x00000073
1282
1283 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0                           0x00000074
1284
1285 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1                           0x00000075
1286
1287 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2                           0x00000076
1288
1289 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3                           0x00000077
1290
1291 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0                            0x00000078
1292
1293 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1                            0x00000079
1294
1295 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2                            0x0000007a
1296
1297 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3                            0x0000007b
1298
1299 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0                           0x0000007c
1300
1301 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1                           0x0000007d
1302
1303 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2                           0x0000007e
1304
1305 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3                           0x0000007f
1306
1307 #define REG_A5XX_RBBM_CLOCK_HYST_RAC                            0x00000080
1308
1309 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC                           0x00000081
1310
1311 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0                           0x00000082
1312
1313 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1                           0x00000083
1314
1315 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2                           0x00000084
1316
1317 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3                           0x00000085
1318
1319 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0                        0x00000086
1320
1321 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1                        0x00000087
1322
1323 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2                        0x00000088
1324
1325 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3                        0x00000089
1326
1327 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC                            0x0000008a
1328
1329 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC                           0x0000008b
1330
1331 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0                   0x0000008c
1332
1333 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1                   0x0000008d
1334
1335 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2                   0x0000008e
1336
1337 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3                   0x0000008f
1338
1339 #define REG_A5XX_RBBM_CLOCK_HYST_VFD                            0x00000090
1340
1341 #define REG_A5XX_RBBM_CLOCK_MODE_VFD                            0x00000091
1342
1343 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD                           0x00000092
1344
1345 #define REG_A5XX_RBBM_AHB_CNTL0                                 0x00000093
1346
1347 #define REG_A5XX_RBBM_AHB_CNTL1                                 0x00000094
1348
1349 #define REG_A5XX_RBBM_AHB_CNTL2                                 0x00000095
1350
1351 #define REG_A5XX_RBBM_AHB_CMD                                   0x00000096
1352
1353 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11                0x0000009c
1354
1355 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12                0x0000009d
1356
1357 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13                0x0000009e
1358
1359 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14                0x0000009f
1360
1361 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15                0x000000a0
1362
1363 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16                0x000000a1
1364
1365 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17                0x000000a2
1366
1367 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18                0x000000a3
1368
1369 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0                           0x000000a4
1370
1371 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1                           0x000000a5
1372
1373 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2                           0x000000a6
1374
1375 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3                           0x000000a7
1376
1377 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0                          0x000000a8
1378
1379 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1                          0x000000a9
1380
1381 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2                          0x000000aa
1382
1383 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3                          0x000000ab
1384
1385 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0                          0x000000ac
1386
1387 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1                          0x000000ad
1388
1389 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2                          0x000000ae
1390
1391 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3                          0x000000af
1392
1393 #define REG_A5XX_RBBM_CLOCK_HYST_TP0                            0x000000b0
1394
1395 #define REG_A5XX_RBBM_CLOCK_HYST_TP1                            0x000000b1
1396
1397 #define REG_A5XX_RBBM_CLOCK_HYST_TP2                            0x000000b2
1398
1399 #define REG_A5XX_RBBM_CLOCK_HYST_TP3                            0x000000b3
1400
1401 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0                           0x000000b4
1402
1403 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1                           0x000000b5
1404
1405 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2                           0x000000b6
1406
1407 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3                           0x000000b7
1408
1409 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0                           0x000000b8
1410
1411 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1                           0x000000b9
1412
1413 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2                           0x000000ba
1414
1415 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3                           0x000000bb
1416
1417 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU                           0x000000c8
1418
1419 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU                          0x000000c9
1420
1421 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU                           0x000000ca
1422
1423 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO                           0x000003a0
1424
1425 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI                           0x000003a1
1426
1427 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO                           0x000003a2
1428
1429 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI                           0x000003a3
1430
1431 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO                           0x000003a4
1432
1433 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI                           0x000003a5
1434
1435 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO                           0x000003a6
1436
1437 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI                           0x000003a7
1438
1439 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO                           0x000003a8
1440
1441 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI                           0x000003a9
1442
1443 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO                           0x000003aa
1444
1445 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI                           0x000003ab
1446
1447 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO                           0x000003ac
1448
1449 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI                           0x000003ad
1450
1451 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO                           0x000003ae
1452
1453 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI                           0x000003af
1454
1455 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO                         0x000003b0
1456
1457 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI                         0x000003b1
1458
1459 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO                         0x000003b2
1460
1461 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI                         0x000003b3
1462
1463 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO                         0x000003b4
1464
1465 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI                         0x000003b5
1466
1467 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO                         0x000003b6
1468
1469 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI                         0x000003b7
1470
1471 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO                           0x000003b8
1472
1473 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI                           0x000003b9
1474
1475 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO                           0x000003ba
1476
1477 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI                           0x000003bb
1478
1479 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO                           0x000003bc
1480
1481 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI                           0x000003bd
1482
1483 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO                           0x000003be
1484
1485 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI                           0x000003bf
1486
1487 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO                           0x000003c0
1488
1489 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI                           0x000003c1
1490
1491 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO                           0x000003c2
1492
1493 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI                           0x000003c3
1494
1495 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO                           0x000003c4
1496
1497 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI                           0x000003c5
1498
1499 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO                           0x000003c6
1500
1501 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI                           0x000003c7
1502
1503 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO                          0x000003c8
1504
1505 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI                          0x000003c9
1506
1507 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO                          0x000003ca
1508
1509 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI                          0x000003cb
1510
1511 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO                          0x000003cc
1512
1513 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI                          0x000003cd
1514
1515 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO                          0x000003ce
1516
1517 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI                          0x000003cf
1518
1519 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO                          0x000003d0
1520
1521 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI                          0x000003d1
1522
1523 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO                          0x000003d2
1524
1525 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI                          0x000003d3
1526
1527 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO                          0x000003d4
1528
1529 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI                          0x000003d5
1530
1531 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO                          0x000003d6
1532
1533 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI                          0x000003d7
1534
1535 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO                         0x000003d8
1536
1537 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI                         0x000003d9
1538
1539 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO                         0x000003da
1540
1541 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI                         0x000003db
1542
1543 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO                         0x000003dc
1544
1545 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI                         0x000003dd
1546
1547 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO                         0x000003de
1548
1549 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI                         0x000003df
1550
1551 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO                         0x000003e0
1552
1553 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI                         0x000003e1
1554
1555 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO                         0x000003e2
1556
1557 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI                         0x000003e3
1558
1559 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO                         0x000003e4
1560
1561 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI                         0x000003e5
1562
1563 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO                         0x000003e6
1564
1565 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI                         0x000003e7
1566
1567 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO                          0x000003e8
1568
1569 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI                          0x000003e9
1570
1571 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO                          0x000003ea
1572
1573 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI                          0x000003eb
1574
1575 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO                          0x000003ec
1576
1577 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI                          0x000003ed
1578
1579 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO                          0x000003ee
1580
1581 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI                          0x000003ef
1582
1583 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO                          0x000003f0
1584
1585 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI                          0x000003f1
1586
1587 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO                          0x000003f2
1588
1589 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI                          0x000003f3
1590
1591 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO                          0x000003f4
1592
1593 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI                          0x000003f5
1594
1595 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO                          0x000003f6
1596
1597 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI                          0x000003f7
1598
1599 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO                          0x000003f8
1600
1601 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI                          0x000003f9
1602
1603 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO                          0x000003fa
1604
1605 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI                          0x000003fb
1606
1607 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO                          0x000003fc
1608
1609 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI                          0x000003fd
1610
1611 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO                          0x000003fe
1612
1613 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI                          0x000003ff
1614
1615 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO                          0x00000400
1616
1617 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI                          0x00000401
1618
1619 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO                          0x00000402
1620
1621 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI                          0x00000403
1622
1623 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO                          0x00000404
1624
1625 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI                          0x00000405
1626
1627 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO                          0x00000406
1628
1629 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI                          0x00000407
1630
1631 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO                         0x00000408
1632
1633 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI                         0x00000409
1634
1635 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO                         0x0000040a
1636
1637 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI                         0x0000040b
1638
1639 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO                         0x0000040c
1640
1641 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI                         0x0000040d
1642
1643 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO                         0x0000040e
1644
1645 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI                         0x0000040f
1646
1647 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO                         0x00000410
1648
1649 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI                         0x00000411
1650
1651 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO                         0x00000412
1652
1653 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI                         0x00000413
1654
1655 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO                         0x00000414
1656
1657 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI                         0x00000415
1658
1659 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO                         0x00000416
1660
1661 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI                         0x00000417
1662
1663 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO                           0x00000418
1664
1665 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI                           0x00000419
1666
1667 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO                           0x0000041a
1668
1669 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI                           0x0000041b
1670
1671 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO                           0x0000041c
1672
1673 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI                           0x0000041d
1674
1675 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO                           0x0000041e
1676
1677 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI                           0x0000041f
1678
1679 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO                           0x00000420
1680
1681 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI                           0x00000421
1682
1683 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO                           0x00000422
1684
1685 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI                           0x00000423
1686
1687 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO                           0x00000424
1688
1689 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI                           0x00000425
1690
1691 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO                           0x00000426
1692
1693 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI                           0x00000427
1694
1695 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO                           0x00000428
1696
1697 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI                           0x00000429
1698
1699 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO                           0x0000042a
1700
1701 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI                           0x0000042b
1702
1703 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO                           0x0000042c
1704
1705 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI                           0x0000042d
1706
1707 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO                           0x0000042e
1708
1709 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI                           0x0000042f
1710
1711 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO                           0x00000430
1712
1713 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI                           0x00000431
1714
1715 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO                           0x00000432
1716
1717 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI                           0x00000433
1718
1719 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO                           0x00000434
1720
1721 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI                           0x00000435
1722
1723 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO                           0x00000436
1724
1725 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI                           0x00000437
1726
1727 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO                           0x00000438
1728
1729 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI                           0x00000439
1730
1731 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO                           0x0000043a
1732
1733 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI                           0x0000043b
1734
1735 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO                          0x0000043c
1736
1737 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI                          0x0000043d
1738
1739 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO                          0x0000043e
1740
1741 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI                          0x0000043f
1742
1743 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO                           0x00000440
1744
1745 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI                           0x00000441
1746
1747 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO                           0x00000442
1748
1749 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI                           0x00000443
1750
1751 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO                           0x00000444
1752
1753 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI                           0x00000445
1754
1755 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO                           0x00000446
1756
1757 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI                           0x00000447
1758
1759 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO                           0x00000448
1760
1761 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI                           0x00000449
1762
1763 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO                           0x0000044a
1764
1765 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI                           0x0000044b
1766
1767 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO                           0x0000044c
1768
1769 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI                           0x0000044d
1770
1771 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO                           0x0000044e
1772
1773 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI                           0x0000044f
1774
1775 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO                          0x00000450
1776
1777 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI                          0x00000451
1778
1779 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO                          0x00000452
1780
1781 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI                          0x00000453
1782
1783 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO                          0x00000454
1784
1785 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI                          0x00000455
1786
1787 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO                          0x00000456
1788
1789 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI                          0x00000457
1790
1791 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO                          0x00000458
1792
1793 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI                          0x00000459
1794
1795 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO                          0x0000045a
1796
1797 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI                          0x0000045b
1798
1799 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO                          0x0000045c
1800
1801 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI                          0x0000045d
1802
1803 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO                          0x0000045e
1804
1805 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI                          0x0000045f
1806
1807 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO                          0x00000460
1808
1809 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI                          0x00000461
1810
1811 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO                          0x00000462
1812
1813 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI                          0x00000463
1814
1815 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0                        0x0000046b
1816
1817 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1                        0x0000046c
1818
1819 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2                        0x0000046d
1820
1821 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3                        0x0000046e
1822
1823 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO                       0x000004d2
1824
1825 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI                       0x000004d3
1826
1827 #define REG_A5XX_RBBM_STATUS                                    0x000004f5
1828 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB                       0x80000000
1829 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP                    0x40000000
1830 #define A5XX_RBBM_STATUS_HLSQ_BUSY                              0x20000000
1831 #define A5XX_RBBM_STATUS_VSC_BUSY                               0x10000000
1832 #define A5XX_RBBM_STATUS_TPL1_BUSY                              0x08000000
1833 #define A5XX_RBBM_STATUS_SP_BUSY                                0x04000000
1834 #define A5XX_RBBM_STATUS_UCHE_BUSY                              0x02000000
1835 #define A5XX_RBBM_STATUS_VPC_BUSY                               0x01000000
1836 #define A5XX_RBBM_STATUS_VFDP_BUSY                              0x00800000
1837 #define A5XX_RBBM_STATUS_VFD_BUSY                               0x00400000
1838 #define A5XX_RBBM_STATUS_TESS_BUSY                              0x00200000
1839 #define A5XX_RBBM_STATUS_PC_VSD_BUSY                            0x00100000
1840 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00080000
1841 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY                        0x00040000
1842 #define A5XX_RBBM_STATUS_DCOM_BUSY                              0x00020000
1843 #define A5XX_RBBM_STATUS_COM_BUSY                               0x00010000
1844 #define A5XX_RBBM_STATUS_LRZ_BUZY                               0x00008000
1845 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY                           0x00004000
1846 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY                           0x00002000
1847 #define A5XX_RBBM_STATUS_RB_BUSY                                0x00001000
1848 #define A5XX_RBBM_STATUS_RAS_BUSY                               0x00000800
1849 #define A5XX_RBBM_STATUS_TSE_BUSY                               0x00000400
1850 #define A5XX_RBBM_STATUS_VBIF_BUSY                              0x00000200
1851 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST                  0x00000100
1852 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST                       0x00000080
1853 #define A5XX_RBBM_STATUS_CP_BUSY                                0x00000040
1854 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY                       0x00000020
1855 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY                          0x00000010
1856 #define A5XX_RBBM_STATUS_CP_ETS_BUSY                            0x00000008
1857 #define A5XX_RBBM_STATUS_CP_PFP_BUSY                            0x00000004
1858 #define A5XX_RBBM_STATUS_CP_ME_BUSY                             0x00000002
1859 #define A5XX_RBBM_STATUS_HI_BUSY                                0x00000001
1860
1861 #define REG_A5XX_RBBM_STATUS3                                   0x00000530
1862
1863 #define REG_A5XX_RBBM_INT_0_STATUS                              0x000004e1
1864
1865 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS                       0x000004f0
1866
1867 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS                      0x000004f1
1868
1869 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS                      0x000004f3
1870
1871 #define REG_A5XX_RBBM_AHB_ERROR_STATUS                          0x000004f4
1872
1873 #define REG_A5XX_RBBM_PERFCTR_CNTL                              0x00000464
1874
1875 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000465
1876
1877 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000466
1878
1879 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2                         0x00000467
1880
1881 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3                         0x00000468
1882
1883 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000469
1884
1885 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x0000046a
1886
1887 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0                        0x0000046b
1888
1889 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1                        0x0000046c
1890
1891 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2                        0x0000046d
1892
1893 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3                        0x0000046e
1894
1895 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED                   0x0000046f
1896
1897 #define REG_A5XX_RBBM_AHB_ERROR                                 0x000004ed
1898
1899 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC                    0x00000504
1900
1901 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER                           0x00000505
1902
1903 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0                         0x00000506
1904
1905 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1                         0x00000507
1906
1907 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2                         0x00000508
1908
1909 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3                         0x00000509
1910
1911 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4                         0x0000050a
1912
1913 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5                         0x0000050b
1914
1915 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR                     0x0000050c
1916
1917 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0                     0x0000050d
1918
1919 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1                     0x0000050e
1920
1921 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2                     0x0000050f
1922
1923 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3                     0x00000510
1924
1925 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4                     0x00000511
1926
1927 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0                          0x00000512
1928
1929 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1                          0x00000513
1930
1931 #define REG_A5XX_RBBM_ISDB_CNT                                  0x00000533
1932
1933 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG                       0x0000f000
1934
1935 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL                         0x0000f400
1936
1937 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO                0x0000f800
1938
1939 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI                0x0000f801
1940
1941 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE                   0x0000f802
1942
1943 #define REG_A5XX_RBBM_SECVID_TSB_CNTL                           0x0000f803
1944
1945 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO                 0x0000f804
1946
1947 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI                 0x0000f805
1948
1949 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO                 0x0000f806
1950
1951 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI                 0x0000f807
1952
1953 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL                 0x0000f810
1954
1955 #define REG_A5XX_VSC_BIN_SIZE                                   0x00000bc2
1956 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK                           0x000000ff
1957 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
1958 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1959 {
1960         return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
1961 }
1962 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x0001fe00
1963 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         9
1964 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1965 {
1966         return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
1967 }
1968
1969 #define REG_A5XX_VSC_SIZE_ADDRESS_LO                            0x00000bc3
1970
1971 #define REG_A5XX_VSC_SIZE_ADDRESS_HI                            0x00000bc4
1972
1973 #define REG_A5XX_UNKNOWN_0BC5                                   0x00000bc5
1974
1975 #define REG_A5XX_UNKNOWN_0BC6                                   0x00000bc6
1976
1977 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
1978
1979 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
1980 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK                        0x000003ff
1981 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT                       0
1982 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1983 {
1984         return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
1985 }
1986 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK                        0x000ffc00
1987 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT                       10
1988 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1989 {
1990         return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1991 }
1992 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK                        0x00f00000
1993 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT                       20
1994 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1995 {
1996         return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
1997 }
1998 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK                        0x0f000000
1999 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT                       24
2000 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2001 {
2002         return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
2003 }
2004
2005 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2006
2007 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2008
2009 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
2010
2011 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2012
2013 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2014
2015 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0                          0x00000c60
2016
2017 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1                          0x00000c61
2018
2019 #define REG_A5XX_VSC_RESOLVE_CNTL                               0x00000cdd
2020 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE             0x80000000
2021 #define A5XX_VSC_RESOLVE_CNTL_X__MASK                           0x00007fff
2022 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT                          0
2023 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
2024 {
2025         return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
2026 }
2027 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK                           0x7fff0000
2028 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT                          16
2029 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
2030 {
2031         return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
2032 }
2033
2034 #define REG_A5XX_GRAS_ADDR_MODE_CNTL                            0x00000c81
2035
2036 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0                         0x00000c90
2037
2038 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1                         0x00000c91
2039
2040 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2                         0x00000c92
2041
2042 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3                         0x00000c93
2043
2044 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0                         0x00000c94
2045
2046 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1                         0x00000c95
2047
2048 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2                         0x00000c96
2049
2050 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3                         0x00000c97
2051
2052 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0                         0x00000c98
2053
2054 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1                         0x00000c99
2055
2056 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2                         0x00000c9a
2057
2058 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3                         0x00000c9b
2059
2060 #define REG_A5XX_RB_DBG_ECO_CNTL                                0x00000cc4
2061
2062 #define REG_A5XX_RB_ADDR_MODE_CNTL                              0x00000cc5
2063
2064 #define REG_A5XX_RB_MODE_CNTL                                   0x00000cc6
2065
2066 #define REG_A5XX_RB_CCU_CNTL                                    0x00000cc7
2067
2068 #define REG_A5XX_RB_PERFCTR_RB_SEL_0                            0x00000cd0
2069
2070 #define REG_A5XX_RB_PERFCTR_RB_SEL_1                            0x00000cd1
2071
2072 #define REG_A5XX_RB_PERFCTR_RB_SEL_2                            0x00000cd2
2073
2074 #define REG_A5XX_RB_PERFCTR_RB_SEL_3                            0x00000cd3
2075
2076 #define REG_A5XX_RB_PERFCTR_RB_SEL_4                            0x00000cd4
2077
2078 #define REG_A5XX_RB_PERFCTR_RB_SEL_5                            0x00000cd5
2079
2080 #define REG_A5XX_RB_PERFCTR_RB_SEL_6                            0x00000cd6
2081
2082 #define REG_A5XX_RB_PERFCTR_RB_SEL_7                            0x00000cd7
2083
2084 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0                           0x00000cd8
2085
2086 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1                           0x00000cd9
2087
2088 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2                           0x00000cda
2089
2090 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3                           0x00000cdb
2091
2092 #define REG_A5XX_RB_POWERCTR_RB_SEL_0                           0x00000ce0
2093
2094 #define REG_A5XX_RB_POWERCTR_RB_SEL_1                           0x00000ce1
2095
2096 #define REG_A5XX_RB_POWERCTR_RB_SEL_2                           0x00000ce2
2097
2098 #define REG_A5XX_RB_POWERCTR_RB_SEL_3                           0x00000ce3
2099
2100 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0                          0x00000ce4
2101
2102 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1                          0x00000ce5
2103
2104 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0                           0x00000cec
2105
2106 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1                           0x00000ced
2107
2108 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2                           0x00000cee
2109
2110 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3                           0x00000cef
2111
2112 #define REG_A5XX_PC_DBG_ECO_CNTL                                0x00000d00
2113 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI                      0x00000100
2114
2115 #define REG_A5XX_PC_ADDR_MODE_CNTL                              0x00000d01
2116
2117 #define REG_A5XX_PC_MODE_CNTL                                   0x00000d02
2118
2119 #define REG_A5XX_PC_INDEX_BUF_LO                                0x00000d04
2120
2121 #define REG_A5XX_PC_INDEX_BUF_HI                                0x00000d05
2122
2123 #define REG_A5XX_PC_START_INDEX                                 0x00000d06
2124
2125 #define REG_A5XX_PC_MAX_INDEX                                   0x00000d07
2126
2127 #define REG_A5XX_PC_TESSFACTOR_ADDR_LO                          0x00000d08
2128
2129 #define REG_A5XX_PC_TESSFACTOR_ADDR_HI                          0x00000d09
2130
2131 #define REG_A5XX_PC_PERFCTR_PC_SEL_0                            0x00000d10
2132
2133 #define REG_A5XX_PC_PERFCTR_PC_SEL_1                            0x00000d11
2134
2135 #define REG_A5XX_PC_PERFCTR_PC_SEL_2                            0x00000d12
2136
2137 #define REG_A5XX_PC_PERFCTR_PC_SEL_3                            0x00000d13
2138
2139 #define REG_A5XX_PC_PERFCTR_PC_SEL_4                            0x00000d14
2140
2141 #define REG_A5XX_PC_PERFCTR_PC_SEL_5                            0x00000d15
2142
2143 #define REG_A5XX_PC_PERFCTR_PC_SEL_6                            0x00000d16
2144
2145 #define REG_A5XX_PC_PERFCTR_PC_SEL_7                            0x00000d17
2146
2147 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0                       0x00000e00
2148
2149 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1                       0x00000e01
2150
2151 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL                            0x00000e05
2152
2153 #define REG_A5XX_HLSQ_MODE_CNTL                                 0x00000e06
2154
2155 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0                        0x00000e10
2156
2157 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1                        0x00000e11
2158
2159 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2                        0x00000e12
2160
2161 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3                        0x00000e13
2162
2163 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4                        0x00000e14
2164
2165 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5                        0x00000e15
2166
2167 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6                        0x00000e16
2168
2169 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7                        0x00000e17
2170
2171 #define REG_A5XX_HLSQ_SPTP_RDSEL                                0x00000f08
2172
2173 #define REG_A5XX_HLSQ_DBG_READ_SEL                              0x0000bc00
2174
2175 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE                     0x0000a000
2176
2177 #define REG_A5XX_VFD_ADDR_MODE_CNTL                             0x00000e41
2178
2179 #define REG_A5XX_VFD_MODE_CNTL                                  0x00000e42
2180
2181 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0                          0x00000e50
2182
2183 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1                          0x00000e51
2184
2185 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2                          0x00000e52
2186
2187 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3                          0x00000e53
2188
2189 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4                          0x00000e54
2190
2191 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5                          0x00000e55
2192
2193 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6                          0x00000e56
2194
2195 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7                          0x00000e57
2196
2197 #define REG_A5XX_VPC_DBG_ECO_CNTL                               0x00000e60
2198
2199 #define REG_A5XX_VPC_ADDR_MODE_CNTL                             0x00000e61
2200
2201 #define REG_A5XX_VPC_MODE_CNTL                                  0x00000e62
2202 #define A5XX_VPC_MODE_CNTL_BINNING_PASS                         0x00000001
2203
2204 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0                          0x00000e64
2205
2206 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1                          0x00000e65
2207
2208 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2                          0x00000e66
2209
2210 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3                          0x00000e67
2211
2212 #define REG_A5XX_UCHE_ADDR_MODE_CNTL                            0x00000e80
2213
2214 #define REG_A5XX_UCHE_SVM_CNTL                                  0x00000e82
2215
2216 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO                        0x00000e87
2217
2218 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI                        0x00000e88
2219
2220 #define REG_A5XX_UCHE_TRAP_BASE_LO                              0x00000e89
2221
2222 #define REG_A5XX_UCHE_TRAP_BASE_HI                              0x00000e8a
2223
2224 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO                         0x00000e8b
2225
2226 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI                         0x00000e8c
2227
2228 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO                         0x00000e8d
2229
2230 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI                         0x00000e8e
2231
2232 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2                            0x00000e8f
2233
2234 #define REG_A5XX_UCHE_DBG_ECO_CNTL                              0x00000e90
2235
2236 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO                   0x00000e91
2237
2238 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI                   0x00000e92
2239
2240 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO                   0x00000e93
2241
2242 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI                   0x00000e94
2243
2244 #define REG_A5XX_UCHE_CACHE_INVALIDATE                          0x00000e95
2245
2246 #define REG_A5XX_UCHE_CACHE_WAYS                                0x00000e96
2247
2248 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0                        0x00000ea0
2249
2250 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1                        0x00000ea1
2251
2252 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2                        0x00000ea2
2253
2254 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3                        0x00000ea3
2255
2256 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4                        0x00000ea4
2257
2258 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5                        0x00000ea5
2259
2260 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6                        0x00000ea6
2261
2262 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7                        0x00000ea7
2263
2264 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0                       0x00000ea8
2265
2266 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1                       0x00000ea9
2267
2268 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2                       0x00000eaa
2269
2270 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3                       0x00000eab
2271
2272 #define REG_A5XX_UCHE_TRAP_LOG_LO                               0x00000eb1
2273
2274 #define REG_A5XX_UCHE_TRAP_LOG_HI                               0x00000eb2
2275
2276 #define REG_A5XX_SP_DBG_ECO_CNTL                                0x00000ec0
2277
2278 #define REG_A5XX_SP_ADDR_MODE_CNTL                              0x00000ec1
2279
2280 #define REG_A5XX_SP_MODE_CNTL                                   0x00000ec2
2281
2282 #define REG_A5XX_SP_PERFCTR_SP_SEL_0                            0x00000ed0
2283
2284 #define REG_A5XX_SP_PERFCTR_SP_SEL_1                            0x00000ed1
2285
2286 #define REG_A5XX_SP_PERFCTR_SP_SEL_2                            0x00000ed2
2287
2288 #define REG_A5XX_SP_PERFCTR_SP_SEL_3                            0x00000ed3
2289
2290 #define REG_A5XX_SP_PERFCTR_SP_SEL_4                            0x00000ed4
2291
2292 #define REG_A5XX_SP_PERFCTR_SP_SEL_5                            0x00000ed5
2293
2294 #define REG_A5XX_SP_PERFCTR_SP_SEL_6                            0x00000ed6
2295
2296 #define REG_A5XX_SP_PERFCTR_SP_SEL_7                            0x00000ed7
2297
2298 #define REG_A5XX_SP_PERFCTR_SP_SEL_8                            0x00000ed8
2299
2300 #define REG_A5XX_SP_PERFCTR_SP_SEL_9                            0x00000ed9
2301
2302 #define REG_A5XX_SP_PERFCTR_SP_SEL_10                           0x00000eda
2303
2304 #define REG_A5XX_SP_PERFCTR_SP_SEL_11                           0x00000edb
2305
2306 #define REG_A5XX_SP_POWERCTR_SP_SEL_0                           0x00000edc
2307
2308 #define REG_A5XX_SP_POWERCTR_SP_SEL_1                           0x00000edd
2309
2310 #define REG_A5XX_SP_POWERCTR_SP_SEL_2                           0x00000ede
2311
2312 #define REG_A5XX_SP_POWERCTR_SP_SEL_3                           0x00000edf
2313
2314 #define REG_A5XX_TPL1_ADDR_MODE_CNTL                            0x00000f01
2315
2316 #define REG_A5XX_TPL1_MODE_CNTL                                 0x00000f02
2317
2318 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0                          0x00000f10
2319
2320 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1                          0x00000f11
2321
2322 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2                          0x00000f12
2323
2324 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3                          0x00000f13
2325
2326 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4                          0x00000f14
2327
2328 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5                          0x00000f15
2329
2330 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6                          0x00000f16
2331
2332 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7                          0x00000f17
2333
2334 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0                         0x00000f18
2335
2336 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1                         0x00000f19
2337
2338 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2                         0x00000f1a
2339
2340 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3                         0x00000f1b
2341
2342 #define REG_A5XX_VBIF_VERSION                                   0x00003000
2343
2344 #define REG_A5XX_VBIF_CLKON                                     0x00003001
2345
2346 #define REG_A5XX_VBIF_ABIT_SORT                                 0x00003028
2347
2348 #define REG_A5XX_VBIF_ABIT_SORT_CONF                            0x00003029
2349
2350 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB                       0x00003049
2351
2352 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
2353
2354 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0                           0x0000302c
2355
2356 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1                           0x0000302d
2357
2358 #define REG_A5XX_VBIF_XIN_HALT_CTRL0                            0x00003080
2359
2360 #define REG_A5XX_VBIF_XIN_HALT_CTRL1                            0x00003081
2361
2362 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL                         0x00003084
2363
2364 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0                           0x00003085
2365
2366 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1                           0x00003086
2367
2368 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0                           0x00003087
2369
2370 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1                           0x00003088
2371
2372 #define REG_A5XX_VBIF_TEST_BUS_OUT                              0x0000308c
2373
2374 #define REG_A5XX_VBIF_PERF_CNT_EN0                              0x000030c0
2375
2376 #define REG_A5XX_VBIF_PERF_CNT_EN1                              0x000030c1
2377
2378 #define REG_A5XX_VBIF_PERF_CNT_EN2                              0x000030c2
2379
2380 #define REG_A5XX_VBIF_PERF_CNT_EN3                              0x000030c3
2381
2382 #define REG_A5XX_VBIF_PERF_CNT_CLR0                             0x000030c8
2383
2384 #define REG_A5XX_VBIF_PERF_CNT_CLR1                             0x000030c9
2385
2386 #define REG_A5XX_VBIF_PERF_CNT_CLR2                             0x000030ca
2387
2388 #define REG_A5XX_VBIF_PERF_CNT_CLR3                             0x000030cb
2389
2390 #define REG_A5XX_VBIF_PERF_CNT_SEL0                             0x000030d0
2391
2392 #define REG_A5XX_VBIF_PERF_CNT_SEL1                             0x000030d1
2393
2394 #define REG_A5XX_VBIF_PERF_CNT_SEL2                             0x000030d2
2395
2396 #define REG_A5XX_VBIF_PERF_CNT_SEL3                             0x000030d3
2397
2398 #define REG_A5XX_VBIF_PERF_CNT_LOW0                             0x000030d8
2399
2400 #define REG_A5XX_VBIF_PERF_CNT_LOW1                             0x000030d9
2401
2402 #define REG_A5XX_VBIF_PERF_CNT_LOW2                             0x000030da
2403
2404 #define REG_A5XX_VBIF_PERF_CNT_LOW3                             0x000030db
2405
2406 #define REG_A5XX_VBIF_PERF_CNT_HIGH0                            0x000030e0
2407
2408 #define REG_A5XX_VBIF_PERF_CNT_HIGH1                            0x000030e1
2409
2410 #define REG_A5XX_VBIF_PERF_CNT_HIGH2                            0x000030e2
2411
2412 #define REG_A5XX_VBIF_PERF_CNT_HIGH3                            0x000030e3
2413
2414 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0                          0x00003100
2415
2416 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1                          0x00003101
2417
2418 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2                          0x00003102
2419
2420 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0                         0x00003110
2421
2422 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1                         0x00003111
2423
2424 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2                         0x00003112
2425
2426 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0                        0x00003118
2427
2428 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1                        0x00003119
2429
2430 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2                        0x0000311a
2431
2432 #define REG_A5XX_GPMU_INST_RAM_BASE                             0x00008800
2433
2434 #define REG_A5XX_GPMU_DATA_RAM_BASE                             0x00009800
2435
2436 #define REG_A5XX_GPMU_SP_POWER_CNTL                             0x0000a881
2437
2438 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL                          0x0000a886
2439
2440 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL                          0x0000a887
2441
2442 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS                         0x0000a88b
2443 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON                      0x00100000
2444
2445 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS                      0x0000a88d
2446 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON                   0x00100000
2447
2448 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY                     0x0000a891
2449
2450 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL                  0x0000a892
2451
2452 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST                  0x0000a893
2453
2454 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL                      0x0000a894
2455
2456 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL                       0x0000a8a3
2457
2458 #define REG_A5XX_GPMU_WFI_CONFIG                                0x0000a8c1
2459
2460 #define REG_A5XX_GPMU_RBBM_INTR_INFO                            0x0000a8d6
2461
2462 #define REG_A5XX_GPMU_CM3_SYSRESET                              0x0000a8d8
2463
2464 #define REG_A5XX_GPMU_GENERAL_0                                 0x0000a8e0
2465
2466 #define REG_A5XX_GPMU_GENERAL_1                                 0x0000a8e1
2467
2468 #define REG_A5XX_SP_POWER_COUNTER_0_LO                          0x0000a840
2469
2470 #define REG_A5XX_SP_POWER_COUNTER_0_HI                          0x0000a841
2471
2472 #define REG_A5XX_SP_POWER_COUNTER_1_LO                          0x0000a842
2473
2474 #define REG_A5XX_SP_POWER_COUNTER_1_HI                          0x0000a843
2475
2476 #define REG_A5XX_SP_POWER_COUNTER_2_LO                          0x0000a844
2477
2478 #define REG_A5XX_SP_POWER_COUNTER_2_HI                          0x0000a845
2479
2480 #define REG_A5XX_SP_POWER_COUNTER_3_LO                          0x0000a846
2481
2482 #define REG_A5XX_SP_POWER_COUNTER_3_HI                          0x0000a847
2483
2484 #define REG_A5XX_TP_POWER_COUNTER_0_LO                          0x0000a848
2485
2486 #define REG_A5XX_TP_POWER_COUNTER_0_HI                          0x0000a849
2487
2488 #define REG_A5XX_TP_POWER_COUNTER_1_LO                          0x0000a84a
2489
2490 #define REG_A5XX_TP_POWER_COUNTER_1_HI                          0x0000a84b
2491
2492 #define REG_A5XX_TP_POWER_COUNTER_2_LO                          0x0000a84c
2493
2494 #define REG_A5XX_TP_POWER_COUNTER_2_HI                          0x0000a84d
2495
2496 #define REG_A5XX_TP_POWER_COUNTER_3_LO                          0x0000a84e
2497
2498 #define REG_A5XX_TP_POWER_COUNTER_3_HI                          0x0000a84f
2499
2500 #define REG_A5XX_RB_POWER_COUNTER_0_LO                          0x0000a850
2501
2502 #define REG_A5XX_RB_POWER_COUNTER_0_HI                          0x0000a851
2503
2504 #define REG_A5XX_RB_POWER_COUNTER_1_LO                          0x0000a852
2505
2506 #define REG_A5XX_RB_POWER_COUNTER_1_HI                          0x0000a853
2507
2508 #define REG_A5XX_RB_POWER_COUNTER_2_LO                          0x0000a854
2509
2510 #define REG_A5XX_RB_POWER_COUNTER_2_HI                          0x0000a855
2511
2512 #define REG_A5XX_RB_POWER_COUNTER_3_LO                          0x0000a856
2513
2514 #define REG_A5XX_RB_POWER_COUNTER_3_HI                          0x0000a857
2515
2516 #define REG_A5XX_CCU_POWER_COUNTER_0_LO                         0x0000a858
2517
2518 #define REG_A5XX_CCU_POWER_COUNTER_0_HI                         0x0000a859
2519
2520 #define REG_A5XX_CCU_POWER_COUNTER_1_LO                         0x0000a85a
2521
2522 #define REG_A5XX_CCU_POWER_COUNTER_1_HI                         0x0000a85b
2523
2524 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO                        0x0000a85c
2525
2526 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI                        0x0000a85d
2527
2528 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO                        0x0000a85e
2529
2530 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI                        0x0000a85f
2531
2532 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO                        0x0000a860
2533
2534 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI                        0x0000a861
2535
2536 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO                        0x0000a862
2537
2538 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI                        0x0000a863
2539
2540 #define REG_A5XX_CP_POWER_COUNTER_0_LO                          0x0000a864
2541
2542 #define REG_A5XX_CP_POWER_COUNTER_0_HI                          0x0000a865
2543
2544 #define REG_A5XX_CP_POWER_COUNTER_1_LO                          0x0000a866
2545
2546 #define REG_A5XX_CP_POWER_COUNTER_1_HI                          0x0000a867
2547
2548 #define REG_A5XX_CP_POWER_COUNTER_2_LO                          0x0000a868
2549
2550 #define REG_A5XX_CP_POWER_COUNTER_2_HI                          0x0000a869
2551
2552 #define REG_A5XX_CP_POWER_COUNTER_3_LO                          0x0000a86a
2553
2554 #define REG_A5XX_CP_POWER_COUNTER_3_HI                          0x0000a86b
2555
2556 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO                        0x0000a86c
2557
2558 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI                        0x0000a86d
2559
2560 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO                        0x0000a86e
2561
2562 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI                        0x0000a86f
2563
2564 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO                        0x0000a870
2565
2566 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI                        0x0000a871
2567
2568 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO                        0x0000a872
2569
2570 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI                        0x0000a873
2571
2572 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO                        0x0000a874
2573
2574 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI                        0x0000a875
2575
2576 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO                        0x0000a876
2577
2578 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI                        0x0000a877
2579
2580 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE                      0x0000a878
2581
2582 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO                      0x0000a879
2583
2584 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI                      0x0000a87a
2585
2586 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET                   0x0000a87b
2587
2588 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0                    0x0000a87c
2589
2590 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1                    0x0000a87d
2591
2592 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL                       0x0000a8a3
2593
2594 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL                0x0000a8a8
2595
2596 #define REG_A5XX_GPMU_TEMP_SENSOR_ID                            0x0000ac00
2597
2598 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG                        0x0000ac01
2599
2600 #define REG_A5XX_GPMU_TEMP_VAL                                  0x0000ac02
2601
2602 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD                      0x0000ac03
2603
2604 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS                0x0000ac05
2605
2606 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK               0x0000ac06
2607
2608 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1                    0x0000ac40
2609
2610 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3                    0x0000ac41
2611
2612 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1                     0x0000ac42
2613
2614 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3                     0x0000ac43
2615
2616 #define REG_A5XX_GPMU_BASE_LEAKAGE                              0x0000ac46
2617
2618 #define REG_A5XX_GPMU_GPMU_VOLTAGE                              0x0000ac60
2619
2620 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS                  0x0000ac61
2621
2622 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK                 0x0000ac62
2623
2624 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD                        0x0000ac80
2625
2626 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL                   0x0000acc4
2627
2628 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS                 0x0000acc5
2629
2630 #define REG_A5XX_GDPM_CONFIG1                                   0x0000b80c
2631
2632 #define REG_A5XX_GDPM_CONFIG2                                   0x0000b80d
2633
2634 #define REG_A5XX_GDPM_INT_EN                                    0x0000b80f
2635
2636 #define REG_A5XX_GDPM_INT_MASK                                  0x0000b811
2637
2638 #define REG_A5XX_GPMU_BEC_ENABLE                                0x0000b9a0
2639
2640 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS                   0x0000c41a
2641
2642 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0               0x0000c41d
2643
2644 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2               0x0000c41f
2645
2646 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4               0x0000c421
2647
2648 #define REG_A5XX_GPU_CS_ENABLE_REG                              0x0000c520
2649
2650 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1                0x0000c557
2651
2652 #define REG_A5XX_GRAS_CL_CNTL                                   0x0000e000
2653 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z                       0x00000040
2654
2655 #define REG_A5XX_UNKNOWN_E001                                   0x0000e001
2656
2657 #define REG_A5XX_UNKNOWN_E004                                   0x0000e004
2658
2659 #define REG_A5XX_GRAS_CNTL                                      0x0000e005
2660 #define A5XX_GRAS_CNTL_VARYING                                  0x00000001
2661 #define A5XX_GRAS_CNTL_UNK3                                     0x00000008
2662 #define A5XX_GRAS_CNTL_XCOORD                                   0x00000040
2663 #define A5XX_GRAS_CNTL_YCOORD                                   0x00000080
2664 #define A5XX_GRAS_CNTL_ZCOORD                                   0x00000100
2665 #define A5XX_GRAS_CNTL_WCOORD                                   0x00000200
2666
2667 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ                     0x0000e006
2668 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK              0x000003ff
2669 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT             0
2670 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2671 {
2672         return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2673 }
2674 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK              0x000ffc00
2675 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT             10
2676 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2677 {
2678         return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2679 }
2680
2681 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0                        0x0000e010
2682 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK                      0xffffffff
2683 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT                     0
2684 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2685 {
2686         return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2687 }
2688
2689 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0                         0x0000e011
2690 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK                       0xffffffff
2691 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT                      0
2692 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
2693 {
2694         return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2695 }
2696
2697 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0                        0x0000e012
2698 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK                      0xffffffff
2699 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT                     0
2700 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2701 {
2702         return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2703 }
2704
2705 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0                         0x0000e013
2706 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK                       0xffffffff
2707 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT                      0
2708 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
2709 {
2710         return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2711 }
2712
2713 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0                        0x0000e014
2714 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK                      0xffffffff
2715 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT                     0
2716 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2717 {
2718         return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2719 }
2720
2721 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0                         0x0000e015
2722 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK                       0xffffffff
2723 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT                      0
2724 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2725 {
2726         return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2727 }
2728
2729 #define REG_A5XX_GRAS_SU_CNTL                                   0x0000e090
2730 #define A5XX_GRAS_SU_CNTL_CULL_FRONT                            0x00000001
2731 #define A5XX_GRAS_SU_CNTL_CULL_BACK                             0x00000002
2732 #define A5XX_GRAS_SU_CNTL_FRONT_CW                              0x00000004
2733 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK                   0x000007f8
2734 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT                  3
2735 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2736 {
2737         return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2738 }
2739 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET                           0x00000800
2740 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE                           0x00002000
2741
2742 #define REG_A5XX_GRAS_SU_POINT_MINMAX                           0x0000e091
2743 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK                     0x0000ffff
2744 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT                    0
2745 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2746 {
2747         return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2748 }
2749 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK                     0xffff0000
2750 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT                    16
2751 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2752 {
2753         return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2754 }
2755
2756 #define REG_A5XX_GRAS_SU_POINT_SIZE                             0x0000e092
2757 #define A5XX_GRAS_SU_POINT_SIZE__MASK                           0xffffffff
2758 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT                          0
2759 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2760 {
2761         return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2762 }
2763
2764 #define REG_A5XX_GRAS_SU_LAYERED                                0x0000e093
2765
2766 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL                       0x0000e094
2767 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z             0x00000001
2768 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1                      0x00000002
2769
2770 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE                      0x0000e095
2771 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK                    0xffffffff
2772 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT                   0
2773 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2774 {
2775         return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2776 }
2777
2778 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x0000e096
2779 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
2780 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
2781 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2782 {
2783         return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2784 }
2785
2786 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP               0x0000e097
2787 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK             0xffffffff
2788 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT            0
2789 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2790 {
2791         return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2792 }
2793
2794 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO                      0x0000e098
2795 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK       0x00000007
2796 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT      0
2797 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2798 {
2799         return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2800 }
2801
2802 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL                  0x0000e099
2803
2804 #define REG_A5XX_GRAS_SC_CNTL                                   0x0000e0a0
2805 #define A5XX_GRAS_SC_CNTL_BINNING_PASS                          0x00000001
2806 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED                        0x00008000
2807
2808 #define REG_A5XX_GRAS_SC_BIN_CNTL                               0x0000e0a1
2809
2810 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL                          0x0000e0a2
2811 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK                0x00000003
2812 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT               0
2813 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2814 {
2815         return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2816 }
2817
2818 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL                         0x0000e0a3
2819 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK               0x00000003
2820 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT              0
2821 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2822 {
2823         return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2824 }
2825 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE                0x00000004
2826
2827 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL                    0x0000e0a4
2828
2829 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0                    0x0000e0aa
2830 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE  0x80000000
2831 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK                0x00007fff
2832 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT               0
2833 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2834 {
2835         return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2836 }
2837 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK                0x7fff0000
2838 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT               16
2839 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2840 {
2841         return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2842 }
2843
2844 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0                    0x0000e0ab
2845 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE  0x80000000
2846 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK                0x00007fff
2847 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT               0
2848 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2849 {
2850         return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2851 }
2852 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK                0x7fff0000
2853 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT               16
2854 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2855 {
2856         return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2857 }
2858
2859 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0                  0x0000e0ca
2860 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE        0x80000000
2861 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK              0x00007fff
2862 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT             0
2863 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2864 {
2865         return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2866 }
2867 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK              0x7fff0000
2868 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT             16
2869 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2870 {
2871         return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2872 }
2873
2874 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0                  0x0000e0cb
2875 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE        0x80000000
2876 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK              0x00007fff
2877 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT             0
2878 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2879 {
2880         return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2881 }
2882 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK              0x7fff0000
2883 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT             16
2884 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2885 {
2886         return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2887 }
2888
2889 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x0000e0ea
2890 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
2891 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
2892 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
2893 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2894 {
2895         return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2896 }
2897 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
2898 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
2899 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2900 {
2901         return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2902 }
2903
2904 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x0000e0eb
2905 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
2906 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
2907 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
2908 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2909 {
2910         return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2911 }
2912 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
2913 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
2914 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2915 {
2916         return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2917 }
2918
2919 #define REG_A5XX_GRAS_LRZ_CNTL                                  0x0000e100
2920 #define A5XX_GRAS_LRZ_CNTL_ENABLE                               0x00000001
2921 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE                            0x00000002
2922 #define A5XX_GRAS_LRZ_CNTL_GREATER                              0x00000004
2923
2924 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO                        0x0000e101
2925
2926 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI                        0x0000e102
2927
2928 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH                          0x0000e103
2929 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK                        0xffffffff
2930 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT                       0
2931 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
2932 {
2933         return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
2934 }
2935
2936 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO             0x0000e104
2937
2938 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI             0x0000e105
2939
2940 #define REG_A5XX_RB_CNTL                                        0x0000e140
2941 #define A5XX_RB_CNTL_WIDTH__MASK                                0x000000ff
2942 #define A5XX_RB_CNTL_WIDTH__SHIFT                               0
2943 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
2944 {
2945         return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
2946 }
2947 #define A5XX_RB_CNTL_HEIGHT__MASK                               0x0001fe00
2948 #define A5XX_RB_CNTL_HEIGHT__SHIFT                              9
2949 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
2950 {
2951         return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
2952 }
2953 #define A5XX_RB_CNTL_BYPASS                                     0x00020000
2954
2955 #define REG_A5XX_RB_RENDER_CNTL                                 0x0000e141
2956 #define A5XX_RB_RENDER_CNTL_BINNING_PASS                        0x00000001
2957 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED                      0x00000040
2958 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE                  0x00000080
2959 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH                          0x00004000
2960 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2                         0x00008000
2961 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK                     0x00ff0000
2962 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT                    16
2963 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2964 {
2965         return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2966 }
2967 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK                    0xff000000
2968 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT                   24
2969 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
2970 {
2971         return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
2972 }
2973
2974 #define REG_A5XX_RB_RAS_MSAA_CNTL                               0x0000e142
2975 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK                     0x00000003
2976 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT                    0
2977 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2978 {
2979         return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2980 }
2981
2982 #define REG_A5XX_RB_DEST_MSAA_CNTL                              0x0000e143
2983 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK                    0x00000003
2984 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT                   0
2985 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2986 {
2987         return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2988 }
2989 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE                     0x00000004
2990
2991 #define REG_A5XX_RB_RENDER_CONTROL0                             0x0000e144
2992 #define A5XX_RB_RENDER_CONTROL0_VARYING                         0x00000001
2993 #define A5XX_RB_RENDER_CONTROL0_UNK3                            0x00000008
2994 #define A5XX_RB_RENDER_CONTROL0_XCOORD                          0x00000040
2995 #define A5XX_RB_RENDER_CONTROL0_YCOORD                          0x00000080
2996 #define A5XX_RB_RENDER_CONTROL0_ZCOORD                          0x00000100
2997 #define A5XX_RB_RENDER_CONTROL0_WCOORD                          0x00000200
2998
2999 #define REG_A5XX_RB_RENDER_CONTROL1                             0x0000e145
3000 #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK                      0x00000001
3001 #define A5XX_RB_RENDER_CONTROL1_FACENESS                        0x00000002
3002 #define A5XX_RB_RENDER_CONTROL1_SAMPLEID                        0x00000004
3003
3004 #define REG_A5XX_RB_FS_OUTPUT_CNTL                              0x0000e146
3005 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK                        0x0000000f
3006 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT                       0
3007 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
3008 {
3009         return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
3010 }
3011 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z                    0x00000020
3012
3013 #define REG_A5XX_RB_RENDER_COMPONENTS                           0x0000e147
3014 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK                     0x0000000f
3015 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT                    0
3016 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3017 {
3018         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
3019 }
3020 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK                     0x000000f0
3021 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT                    4
3022 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3023 {
3024         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
3025 }
3026 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK                     0x00000f00
3027 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT                    8
3028 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3029 {
3030         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
3031 }
3032 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK                     0x0000f000
3033 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT                    12
3034 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3035 {
3036         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
3037 }
3038 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK                     0x000f0000
3039 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT                    16
3040 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3041 {
3042         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
3043 }
3044 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK                     0x00f00000
3045 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT                    20
3046 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3047 {
3048         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
3049 }
3050 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK                     0x0f000000
3051 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT                    24
3052 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3053 {
3054         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
3055 }
3056 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK                     0xf0000000
3057 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT                    28
3058 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3059 {
3060         return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
3061 }
3062
3063 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3064
3065 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3066 #define A5XX_RB_MRT_CONTROL_BLEND                               0x00000001
3067 #define A5XX_RB_MRT_CONTROL_BLEND2                              0x00000002
3068 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE                          0x00000004
3069 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK                      0x00000078
3070 #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                     3
3071 static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3072 {
3073         return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3074 }
3075 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x00000780
3076 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             7
3077 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3078 {
3079         return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3080 }
3081
3082 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
3083 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
3084 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
3085 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3086 {
3087         return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3088 }
3089 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
3090 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
3091 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3092 {
3093         return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3094 }
3095 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
3096 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
3097 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3098 {
3099         return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3100 }
3101 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
3102 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
3103 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3104 {
3105         return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3106 }
3107 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
3108 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
3109 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3110 {
3111         return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3112 }
3113 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
3114 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
3115 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3116 {
3117         return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3118 }
3119
3120 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
3121 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x000000ff
3122 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
3123 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3124 {
3125         return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3126 }
3127 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK              0x00000300
3128 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT             8
3129 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
3130 {
3131         return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3132 }
3133 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK                  0x00001800
3134 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT                 11
3135 static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
3136 {
3137         return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
3138 }
3139 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00006000
3140 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  13
3141 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3142 {
3143         return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3144 }
3145 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB                         0x00008000
3146
3147 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
3148 #define A5XX_RB_MRT_PITCH__MASK                                 0xffffffff
3149 #define A5XX_RB_MRT_PITCH__SHIFT                                0
3150 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
3151 {
3152         return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
3153 }
3154
3155 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
3156 #define A5XX_RB_MRT_ARRAY_PITCH__MASK                           0xffffffff
3157 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT                          0
3158 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3159 {
3160         return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
3161 }
3162
3163 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
3164
3165 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
3166
3167 #define REG_A5XX_RB_BLEND_RED                                   0x0000e1a0
3168 #define A5XX_RB_BLEND_RED_UINT__MASK                            0x000000ff
3169 #define A5XX_RB_BLEND_RED_UINT__SHIFT                           0
3170 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
3171 {
3172         return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
3173 }
3174 #define A5XX_RB_BLEND_RED_SINT__MASK                            0x0000ff00
3175 #define A5XX_RB_BLEND_RED_SINT__SHIFT                           8
3176 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3177 {
3178         return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3179 }
3180 #define A5XX_RB_BLEND_RED_FLOAT__MASK                           0xffff0000
3181 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT                          16
3182 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3183 {
3184         return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3185 }
3186
3187 #define REG_A5XX_RB_BLEND_RED_F32                               0x0000e1a1
3188 #define A5XX_RB_BLEND_RED_F32__MASK                             0xffffffff
3189 #define A5XX_RB_BLEND_RED_F32__SHIFT                            0
3190 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3191 {
3192         return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
3193 }
3194
3195 #define REG_A5XX_RB_BLEND_GREEN                                 0x0000e1a2
3196 #define A5XX_RB_BLEND_GREEN_UINT__MASK                          0x000000ff
3197 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT                         0
3198 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
3199 {
3200         return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
3201 }
3202 #define A5XX_RB_BLEND_GREEN_SINT__MASK                          0x0000ff00
3203 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT                         8
3204 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3205 {
3206         return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3207 }
3208 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK                         0xffff0000
3209 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT                        16
3210 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3211 {
3212         return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3213 }
3214
3215 #define REG_A5XX_RB_BLEND_GREEN_F32                             0x0000e1a3
3216 #define A5XX_RB_BLEND_GREEN_F32__MASK                           0xffffffff
3217 #define A5XX_RB_BLEND_GREEN_F32__SHIFT                          0
3218 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3219 {
3220         return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
3221 }
3222
3223 #define REG_A5XX_RB_BLEND_BLUE                                  0x0000e1a4
3224 #define A5XX_RB_BLEND_BLUE_UINT__MASK                           0x000000ff
3225 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT                          0
3226 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
3227 {
3228         return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
3229 }
3230 #define A5XX_RB_BLEND_BLUE_SINT__MASK                           0x0000ff00
3231 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT                          8
3232 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3233 {
3234         return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3235 }
3236 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK                          0xffff0000
3237 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT                         16
3238 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3239 {
3240         return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3241 }
3242
3243 #define REG_A5XX_RB_BLEND_BLUE_F32                              0x0000e1a5
3244 #define A5XX_RB_BLEND_BLUE_F32__MASK                            0xffffffff
3245 #define A5XX_RB_BLEND_BLUE_F32__SHIFT                           0
3246 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3247 {
3248         return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
3249 }
3250
3251 #define REG_A5XX_RB_BLEND_ALPHA                                 0x0000e1a6
3252 #define A5XX_RB_BLEND_ALPHA_UINT__MASK                          0x000000ff
3253 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT                         0
3254 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
3255 {
3256         return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
3257 }
3258 #define A5XX_RB_BLEND_ALPHA_SINT__MASK                          0x0000ff00
3259 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT                         8
3260 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3261 {
3262         return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3263 }
3264 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK                         0xffff0000
3265 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT                        16
3266 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3267 {
3268         return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3269 }
3270
3271 #define REG_A5XX_RB_BLEND_ALPHA_F32                             0x0000e1a7
3272 #define A5XX_RB_BLEND_ALPHA_F32__MASK                           0xffffffff
3273 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT                          0
3274 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3275 {
3276         return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
3277 }
3278
3279 #define REG_A5XX_RB_ALPHA_CONTROL                               0x0000e1a8
3280 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK                   0x000000ff
3281 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT                  0
3282 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3283 {
3284         return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3285 }
3286 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST                        0x00000100
3287 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK             0x00000e00
3288 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT            9
3289 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3290 {
3291         return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3292 }
3293
3294 #define REG_A5XX_RB_BLEND_CNTL                                  0x0000e1a9
3295 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK                   0x000000ff
3296 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT                  0
3297 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3298 {
3299         return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3300 }
3301 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND                    0x00000100
3302 #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE                    0x00000400
3303 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK                    0xffff0000
3304 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT                   16
3305 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3306 {
3307         return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3308 }
3309
3310 #define REG_A5XX_RB_DEPTH_PLANE_CNTL                            0x0000e1b0
3311 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z                  0x00000001
3312 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1                           0x00000002
3313
3314 #define REG_A5XX_RB_DEPTH_CNTL                                  0x0000e1b1
3315 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE                             0x00000001
3316 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE                       0x00000002
3317 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK                          0x0000001c
3318 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT                         2
3319 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3320 {
3321         return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3322 }
3323 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE                        0x00000040
3324
3325 #define REG_A5XX_RB_DEPTH_BUFFER_INFO                           0x0000e1b2
3326 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK            0x00000007
3327 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT           0
3328 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
3329 {
3330         return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3331 }
3332
3333 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO                        0x0000e1b3
3334
3335 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI                        0x0000e1b4
3336
3337 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH                          0x0000e1b5
3338 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK                        0xffffffff
3339 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT                       0
3340 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3341 {
3342         return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
3343 }
3344
3345 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH                    0x0000e1b6
3346 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK                  0xffffffff
3347 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT                 0
3348 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3349 {
3350         return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3351 }
3352
3353 #define REG_A5XX_RB_STENCIL_CONTROL                             0x0000e1c0
3354 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
3355 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000002
3356 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ                    0x00000004
3357 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
3358 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
3359 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3360 {
3361         return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
3362 }
3363 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
3364 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
3365 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3366 {
3367         return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
3368 }
3369 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
3370 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
3371 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3372 {
3373         return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3374 }
3375 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
3376 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
3377 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3378 {
3379         return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3380 }
3381 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
3382 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
3383 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3384 {
3385         return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3386 }
3387 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
3388 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
3389 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3390 {
3391         return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3392 }
3393 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
3394 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
3395 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3396 {
3397         return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3398 }
3399 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
3400 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
3401 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3402 {
3403         return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3404 }
3405
3406 #define REG_A5XX_RB_STENCIL_INFO                                0x0000e1c1
3407 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL                   0x00000001
3408
3409 #define REG_A5XX_RB_STENCIL_BASE_LO                             0x0000e1c2
3410
3411 #define REG_A5XX_RB_STENCIL_BASE_HI                             0x0000e1c3
3412
3413 #define REG_A5XX_RB_STENCIL_PITCH                               0x0000e1c4
3414 #define A5XX_RB_STENCIL_PITCH__MASK                             0xffffffff
3415 #define A5XX_RB_STENCIL_PITCH__SHIFT                            0
3416 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
3417 {
3418         return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
3419 }
3420
3421 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH                         0x0000e1c5
3422 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK                       0xffffffff
3423 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT                      0
3424 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
3425 {
3426         return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
3427 }
3428
3429 #define REG_A5XX_RB_STENCILREFMASK                              0x0000e1c6
3430 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
3431 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
3432 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
3433 {
3434         return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
3435 }
3436 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
3437 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
3438 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
3439 {
3440         return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
3441 }
3442 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
3443 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
3444 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
3445 {
3446         return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
3447 }
3448
3449 #define REG_A5XX_RB_STENCILREFMASK_BF                           0x0000e1c7
3450 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
3451 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
3452 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
3453 {
3454         return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
3455 }
3456 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
3457 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
3458 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
3459 {
3460         return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
3461 }
3462 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
3463 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
3464 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
3465 {
3466         return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
3467 }
3468
3469 #define REG_A5XX_RB_WINDOW_OFFSET                               0x0000e1d0
3470 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE             0x80000000
3471 #define A5XX_RB_WINDOW_OFFSET_X__MASK                           0x00007fff
3472 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT                          0
3473 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
3474 {
3475         return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
3476 }
3477 #define A5XX_RB_WINDOW_OFFSET_Y__MASK                           0x7fff0000
3478 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT                          16
3479 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3480 {
3481         return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
3482 }
3483
3484 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL                        0x0000e1d1
3485 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY                       0x00000002
3486
3487 #define REG_A5XX_RB_BLIT_CNTL                                   0x0000e210
3488 #define A5XX_RB_BLIT_CNTL_BUF__MASK                             0x0000000f
3489 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT                            0
3490 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
3491 {
3492         return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
3493 }
3494
3495 #define REG_A5XX_RB_RESOLVE_CNTL_1                              0x0000e211
3496 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE            0x80000000
3497 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK                          0x00007fff
3498 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT                         0
3499 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
3500 {
3501         return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
3502 }
3503 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK                          0x7fff0000
3504 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT                         16
3505 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
3506 {
3507         return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
3508 }
3509
3510 #define REG_A5XX_RB_RESOLVE_CNTL_2                              0x0000e212
3511 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE            0x80000000
3512 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK                          0x00007fff
3513 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT                         0
3514 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
3515 {
3516         return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
3517 }
3518 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK                          0x7fff0000
3519 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT                         16
3520 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
3521 {
3522         return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
3523 }
3524
3525 #define REG_A5XX_RB_RESOLVE_CNTL_3                              0x0000e213
3526 #define A5XX_RB_RESOLVE_CNTL_3_TILED                            0x00000001
3527
3528 #define REG_A5XX_RB_BLIT_DST_LO                                 0x0000e214
3529
3530 #define REG_A5XX_RB_BLIT_DST_HI                                 0x0000e215
3531
3532 #define REG_A5XX_RB_BLIT_DST_PITCH                              0x0000e216
3533 #define A5XX_RB_BLIT_DST_PITCH__MASK                            0xffffffff
3534 #define A5XX_RB_BLIT_DST_PITCH__SHIFT                           0
3535 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
3536 {
3537         return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
3538 }
3539
3540 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH                        0x0000e217
3541 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK                      0xffffffff
3542 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT                     0
3543 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3544 {
3545         return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3546 }
3547
3548 #define REG_A5XX_RB_CLEAR_COLOR_DW0                             0x0000e218
3549
3550 #define REG_A5XX_RB_CLEAR_COLOR_DW1                             0x0000e219
3551
3552 #define REG_A5XX_RB_CLEAR_COLOR_DW2                             0x0000e21a
3553
3554 #define REG_A5XX_RB_CLEAR_COLOR_DW3                             0x0000e21b
3555
3556 #define REG_A5XX_RB_CLEAR_CNTL                                  0x0000e21c
3557 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR                           0x00000002
3558 #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE                         0x00000004
3559 #define A5XX_RB_CLEAR_CNTL_MASK__MASK                           0x000000f0
3560 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT                          4
3561 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
3562 {
3563         return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
3564 }
3565
3566 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO                   0x0000e240
3567
3568 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI                   0x0000e241
3569
3570 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH                     0x0000e242
3571
3572 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3573
3574 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3575
3576 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
3577
3578 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
3579 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK                     0xffffffff
3580 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT                    0
3581 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
3582 {
3583         return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
3584 }
3585
3586 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
3587 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK               0xffffffff
3588 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT              0
3589 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
3590 {
3591         return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
3592 }
3593
3594 #define REG_A5XX_RB_BLIT_FLAG_DST_LO                            0x0000e263
3595
3596 #define REG_A5XX_RB_BLIT_FLAG_DST_HI                            0x0000e264
3597
3598 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH                         0x0000e265
3599 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK                       0xffffffff
3600 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT                      0
3601 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
3602 {
3603         return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
3604 }
3605
3606 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH                   0x0000e266
3607 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK                 0xffffffff
3608 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT                0
3609 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
3610 {
3611         return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
3612 }
3613
3614 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO                        0x0000e267
3615
3616 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI                        0x0000e268
3617
3618 #define REG_A5XX_VPC_CNTL_0                                     0x0000e280
3619 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK                     0x0000007f
3620 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT                    0
3621 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
3622 {
3623         return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
3624 }
3625 #define A5XX_VPC_CNTL_0_VARYING                                 0x00000800
3626
3627 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3628
3629 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3630
3631 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3632
3633 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3634
3635 #define REG_A5XX_UNKNOWN_E292                                   0x0000e292
3636
3637 #define REG_A5XX_UNKNOWN_E293                                   0x0000e293
3638
3639 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3640
3641 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3642
3643 #define REG_A5XX_VPC_GS_SIV_CNTL                                0x0000e298
3644
3645 #define REG_A5XX_UNKNOWN_E29A                                   0x0000e29a
3646
3647 #define REG_A5XX_VPC_PACK                                       0x0000e29d
3648 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK                        0x000000ff
3649 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT                       0
3650 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3651 {
3652         return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3653 }
3654 #define A5XX_VPC_PACK_PSIZELOC__MASK                            0x0000ff00
3655 #define A5XX_VPC_PACK_PSIZELOC__SHIFT                           8
3656 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
3657 {
3658         return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
3659 }
3660
3661 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL                        0x0000e2a0
3662
3663 #define REG_A5XX_VPC_SO_BUF_CNTL                                0x0000e2a1
3664 #define A5XX_VPC_SO_BUF_CNTL_BUF0                               0x00000001
3665 #define A5XX_VPC_SO_BUF_CNTL_BUF1                               0x00000008
3666 #define A5XX_VPC_SO_BUF_CNTL_BUF2                               0x00000040
3667 #define A5XX_VPC_SO_BUF_CNTL_BUF3                               0x00000200
3668 #define A5XX_VPC_SO_BUF_CNTL_ENABLE                             0x00008000
3669
3670 #define REG_A5XX_VPC_SO_OVERRIDE                                0x0000e2a2
3671 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE                         0x00000001
3672
3673 #define REG_A5XX_VPC_SO_CNTL                                    0x0000e2a3
3674 #define A5XX_VPC_SO_CNTL_ENABLE                                 0x00010000
3675
3676 #define REG_A5XX_VPC_SO_PROG                                    0x0000e2a4
3677 #define A5XX_VPC_SO_PROG_A_BUF__MASK                            0x00000003
3678 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT                           0
3679 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
3680 {
3681         return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
3682 }
3683 #define A5XX_VPC_SO_PROG_A_OFF__MASK                            0x000007fc
3684 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT                           2
3685 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
3686 {
3687         return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
3688 }
3689 #define A5XX_VPC_SO_PROG_A_EN                                   0x00000800
3690 #define A5XX_VPC_SO_PROG_B_BUF__MASK                            0x00003000
3691 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT                           12
3692 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
3693 {
3694         return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
3695 }
3696 #define A5XX_VPC_SO_PROG_B_OFF__MASK                            0x007fc000
3697 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT                           14
3698 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
3699 {
3700         return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
3701 }
3702 #define A5XX_VPC_SO_PROG_B_EN                                   0x00800000
3703
3704 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3705
3706 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3707
3708 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
3709
3710 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
3711
3712 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
3713
3714 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
3715
3716 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
3717
3718 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
3719
3720 #define REG_A5XX_PC_PRIMITIVE_CNTL                              0x0000e384
3721 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK              0x0000007f
3722 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT             0
3723 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3724 {
3725         return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3726 }
3727 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART                0x00000100
3728 #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES                 0x00000200
3729 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST               0x00000400
3730
3731 #define REG_A5XX_PC_PRIM_VTX_CNTL                               0x0000e385
3732 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE                             0x00000800
3733
3734 #define REG_A5XX_PC_RASTER_CNTL                                 0x0000e388
3735 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK          0x00000007
3736 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT         0
3737 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3738 {
3739         return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
3740 }
3741 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK           0x00000038
3742 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT          3
3743 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3744 {
3745         return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3746 }
3747 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE                     0x00000040
3748
3749 #define REG_A5XX_UNKNOWN_E389                                   0x0000e389
3750
3751 #define REG_A5XX_PC_RESTART_INDEX                               0x0000e38c
3752
3753 #define REG_A5XX_PC_GS_LAYERED                                  0x0000e38d
3754
3755 #define REG_A5XX_PC_GS_PARAM                                    0x0000e38e
3756 #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK                     0x000003ff
3757 #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT                    0
3758 static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3759 {
3760         return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3761 }
3762 #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK                      0x0000f800
3763 #define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT                     11
3764 static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3765 {
3766         return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
3767 }
3768 #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK                         0x01800000
3769 #define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT                        23
3770 static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3771 {
3772         return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
3773 }
3774
3775 #define REG_A5XX_PC_HS_PARAM                                    0x0000e38f
3776 #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK                     0x0000003f
3777 #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT                    0
3778 static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3779 {
3780         return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3781 }
3782 #define A5XX_PC_HS_PARAM_SPACING__MASK                          0x00600000
3783 #define A5XX_PC_HS_PARAM_SPACING__SHIFT                         21
3784 static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3785 {
3786         return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
3787 }
3788 #define A5XX_PC_HS_PARAM_CW                                     0x00800000
3789 #define A5XX_PC_HS_PARAM_CONNECTED                              0x01000000
3790
3791 #define REG_A5XX_PC_POWER_CNTL                                  0x0000e3b0
3792
3793 #define REG_A5XX_VFD_CONTROL_0                                  0x0000e400
3794 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK                         0x0000003f
3795 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT                        0
3796 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3797 {
3798         return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
3799 }
3800
3801 #define REG_A5XX_VFD_CONTROL_1                                  0x0000e401
3802 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x000000ff
3803 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     0
3804 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
3805 {
3806         return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
3807 }
3808 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK                     0x0000ff00
3809 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT                    8
3810 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
3811 {
3812         return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
3813 }
3814 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK                   0x00ff0000
3815 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT                  16
3816 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
3817 {
3818         return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
3819 }
3820
3821 #define REG_A5XX_VFD_CONTROL_2                                  0x0000e402
3822 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK                  0x000000ff
3823 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT                 0
3824 static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
3825 {
3826         return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
3827 }
3828
3829 #define REG_A5XX_VFD_CONTROL_3                                  0x0000e403
3830 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK                  0x0000ff00
3831 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT                 8
3832 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
3833 {
3834         return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
3835 }
3836 #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK                    0x00ff0000
3837 #define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT                   16
3838 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
3839 {
3840         return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
3841 }
3842 #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK                    0xff000000
3843 #define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT                   24
3844 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
3845 {
3846         return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
3847 }
3848
3849 #define REG_A5XX_VFD_CONTROL_4                                  0x0000e404
3850
3851 #define REG_A5XX_VFD_CONTROL_5                                  0x0000e405
3852
3853 #define REG_A5XX_VFD_INDEX_OFFSET                               0x0000e408
3854
3855 #define REG_A5XX_VFD_INSTANCE_START_OFFSET                      0x0000e409
3856
3857 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
3858
3859 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
3860
3861 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
3862
3863 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
3864
3865 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
3866
3867 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
3868
3869 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
3870 #define A5XX_VFD_DECODE_INSTR_IDX__MASK                         0x0000001f
3871 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT                        0
3872 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
3873 {
3874         return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
3875 }
3876 #define A5XX_VFD_DECODE_INSTR_INSTANCED                         0x00020000
3877 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x0ff00000
3878 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     20
3879 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
3880 {
3881         return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
3882 }
3883 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK                        0x30000000
3884 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT                       28
3885 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3886 {
3887         return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
3888 }
3889 #define A5XX_VFD_DECODE_INSTR_UNK30                             0x40000000
3890 #define A5XX_VFD_DECODE_INSTR_FLOAT                             0x80000000
3891
3892 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
3893
3894 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
3895
3896 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
3897 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK                0x0000000f
3898 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT               0
3899 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
3900 {
3901         return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
3902 }
3903 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK                    0x00000ff0
3904 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT                   4
3905 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
3906 {
3907         return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
3908 }
3909
3910 #define REG_A5XX_VFD_POWER_CNTL                                 0x0000e4f0
3911
3912 #define REG_A5XX_SP_SP_CNTL                                     0x0000e580
3913
3914 #define REG_A5XX_SP_VS_CONFIG                                   0x0000e584
3915 #define A5XX_SP_VS_CONFIG_ENABLED                               0x00000001
3916 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK               0x000000fe
3917 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT              1
3918 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3919 {
3920         return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
3921 }
3922 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK                 0x00007f00
3923 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT                8
3924 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3925 {
3926         return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
3927 }
3928
3929 #define REG_A5XX_SP_FS_CONFIG                                   0x0000e585
3930 #define A5XX_SP_FS_CONFIG_ENABLED                               0x00000001
3931 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK               0x000000fe
3932 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT              1
3933 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3934 {
3935         return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
3936 }
3937 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK                 0x00007f00
3938 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT                8
3939 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3940 {
3941         return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
3942 }
3943
3944 #define REG_A5XX_SP_HS_CONFIG                                   0x0000e586
3945 #define A5XX_SP_HS_CONFIG_ENABLED                               0x00000001
3946 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK               0x000000fe
3947 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT              1
3948 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3949 {
3950         return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
3951 }
3952 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK                 0x00007f00
3953 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT                8
3954 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3955 {
3956         return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
3957 }
3958
3959 #define REG_A5XX_SP_DS_CONFIG                                   0x0000e587
3960 #define A5XX_SP_DS_CONFIG_ENABLED                               0x00000001
3961 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK               0x000000fe
3962 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT              1
3963 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3964 {
3965         return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
3966 }
3967 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK                 0x00007f00
3968 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT                8
3969 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3970 {
3971         return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
3972 }
3973
3974 #define REG_A5XX_SP_GS_CONFIG                                   0x0000e588
3975 #define A5XX_SP_GS_CONFIG_ENABLED                               0x00000001
3976 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK               0x000000fe
3977 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT              1
3978 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3979 {
3980         return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
3981 }
3982 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK                 0x00007f00
3983 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT                8
3984 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3985 {
3986         return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
3987 }
3988
3989 #define REG_A5XX_SP_CS_CONFIG                                   0x0000e589
3990 #define A5XX_SP_CS_CONFIG_ENABLED                               0x00000001
3991 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK               0x000000fe
3992 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT              1
3993 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3994 {
3995         return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
3996 }
3997 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK                 0x00007f00
3998 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT                8
3999 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4000 {
4001         return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
4002 }
4003
4004 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST                         0x0000e58a
4005
4006 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST                         0x0000e58b
4007
4008 #define REG_A5XX_SP_VS_CTRL_REG0                                0x0000e590
4009 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00000008
4010 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  3
4011 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4012 {
4013         return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4014 }
4015 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
4016 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
4017 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4018 {
4019         return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4020 }
4021 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
4022 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
4023 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4024 {
4025         return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4026 }
4027 #define A5XX_SP_VS_CTRL_REG0_VARYING                            0x00010000
4028 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE                       0x00100000
4029 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK                  0xfe000000
4030 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT                 25
4031 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4032 {
4033         return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4034 }
4035
4036 #define REG_A5XX_SP_PRIMITIVE_CNTL                              0x0000e592
4037 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK                      0x0000001f
4038 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT                     0
4039 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4040 {
4041         return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4042 }
4043
4044 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4045
4046 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4047 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000000ff
4048 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
4049 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4050 {
4051         return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
4052 }
4053 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00000f00
4054 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    8
4055 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4056 {
4057         return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4058 }
4059 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK                        0x00ff0000
4060 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
4061 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4062 {
4063         return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
4064 }
4065 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x0f000000
4066 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    24
4067 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4068 {
4069         return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4070 }
4071
4072 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4073
4074 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4075 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
4076 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
4077 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4078 {
4079         return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4080 }
4081 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
4082 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
4083 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4084 {
4085         return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4086 }
4087 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
4088 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
4089 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4090 {
4091         return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4092 }
4093 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
4094 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
4095 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4096 {
4097         return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4098 }
4099
4100 #define REG_A5XX_UNKNOWN_E5AB                                   0x0000e5ab
4101
4102 #define REG_A5XX_SP_VS_OBJ_START_LO                             0x0000e5ac
4103
4104 #define REG_A5XX_SP_VS_OBJ_START_HI                             0x0000e5ad
4105
4106 #define REG_A5XX_SP_FS_CTRL_REG0                                0x0000e5c0
4107 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00000008
4108 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  3
4109 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4110 {
4111         return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4112 }
4113 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
4114 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
4115 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4116 {
4117         return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4118 }
4119 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
4120 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
4121 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4122 {
4123         return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4124 }
4125 #define A5XX_SP_FS_CTRL_REG0_VARYING                            0x00010000
4126 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x00100000
4127 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK                  0xfe000000
4128 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT                 25
4129 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4130 {
4131         return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4132 }
4133
4134 #define REG_A5XX_UNKNOWN_E5C2                                   0x0000e5c2
4135
4136 #define REG_A5XX_SP_FS_OBJ_START_LO                             0x0000e5c3
4137
4138 #define REG_A5XX_SP_FS_OBJ_START_HI                             0x0000e5c4
4139
4140 #define REG_A5XX_SP_BLEND_CNTL                                  0x0000e5c9
4141 #define A5XX_SP_BLEND_CNTL_ENABLED                              0x00000001
4142 #define A5XX_SP_BLEND_CNTL_UNK8                                 0x00000100
4143 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE                    0x00000400
4144
4145 #define REG_A5XX_SP_FS_OUTPUT_CNTL                              0x0000e5ca
4146 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK                        0x0000000f
4147 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT                       0
4148 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4149 {
4150         return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
4151 }
4152 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK                0x00001fe0
4153 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT               5
4154 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
4155 {
4156         return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
4157 }
4158 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK           0x001fe000
4159 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT          13
4160 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
4161 {
4162         return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
4163 }
4164
4165 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4166
4167 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4168 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK                       0x000000ff
4169 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT                      0
4170 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4171 {
4172         return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
4173 }
4174 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION                    0x00000100
4175
4176 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4177
4178 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4179 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK                   0x000000ff
4180 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT                  0
4181 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
4182 {
4183         return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4184 }
4185 #define A5XX_SP_FS_MRT_REG_COLOR_SINT                           0x00000100
4186 #define A5XX_SP_FS_MRT_REG_COLOR_UINT                           0x00000200
4187 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB                           0x00000400
4188
4189 #define REG_A5XX_UNKNOWN_E5DB                                   0x0000e5db
4190
4191 #define REG_A5XX_SP_CS_CTRL_REG0                                0x0000e5f0
4192 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK                   0x00000008
4193 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT                  3
4194 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4195 {
4196         return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4197 }
4198 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
4199 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
4200 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4201 {
4202         return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4203 }
4204 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
4205 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
4206 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4207 {
4208         return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4209 }
4210 #define A5XX_SP_CS_CTRL_REG0_VARYING                            0x00010000
4211 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE                       0x00100000
4212 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK                  0xfe000000
4213 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT                 25
4214 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4215 {
4216         return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4217 }
4218
4219 #define REG_A5XX_UNKNOWN_E5F2                                   0x0000e5f2
4220
4221 #define REG_A5XX_SP_CS_OBJ_START_LO                             0x0000e5f3
4222
4223 #define REG_A5XX_SP_CS_OBJ_START_HI                             0x0000e5f4
4224
4225 #define REG_A5XX_SP_HS_CTRL_REG0                                0x0000e600
4226 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK                   0x00000008
4227 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT                  3
4228 static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4229 {
4230         return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4231 }
4232 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
4233 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
4234 static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4235 {
4236         return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4237 }
4238 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
4239 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
4240 static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4241 {
4242         return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4243 }
4244 #define A5XX_SP_HS_CTRL_REG0_VARYING                            0x00010000
4245 #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE                       0x00100000
4246 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK                  0xfe000000
4247 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT                 25
4248 static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4249 {
4250         return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4251 }
4252
4253 #define REG_A5XX_UNKNOWN_E602                                   0x0000e602
4254
4255 #define REG_A5XX_SP_HS_OBJ_START_LO                             0x0000e603
4256
4257 #define REG_A5XX_SP_HS_OBJ_START_HI                             0x0000e604
4258
4259 #define REG_A5XX_SP_DS_CTRL_REG0                                0x0000e610
4260 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK                   0x00000008
4261 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT                  3
4262 static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4263 {
4264         return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4265 }
4266 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
4267 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
4268 static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4269 {
4270         return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4271 }
4272 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
4273 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
4274 static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4275 {
4276         return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4277 }
4278 #define A5XX_SP_DS_CTRL_REG0_VARYING                            0x00010000
4279 #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE                       0x00100000
4280 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK                  0xfe000000
4281 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT                 25
4282 static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4283 {
4284         return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4285 }
4286
4287 #define REG_A5XX_UNKNOWN_E62B                                   0x0000e62b
4288
4289 #define REG_A5XX_SP_DS_OBJ_START_LO                             0x0000e62c
4290
4291 #define REG_A5XX_SP_DS_OBJ_START_HI                             0x0000e62d
4292
4293 #define REG_A5XX_SP_GS_CTRL_REG0                                0x0000e640
4294 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK                   0x00000008
4295 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT                  3
4296 static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4297 {
4298         return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4299 }
4300 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
4301 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
4302 static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4303 {
4304         return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4305 }
4306 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0000fc00
4307 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
4308 static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4309 {
4310         return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4311 }
4312 #define A5XX_SP_GS_CTRL_REG0_VARYING                            0x00010000
4313 #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE                       0x00100000
4314 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK                  0xfe000000
4315 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT                 25
4316 static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4317 {
4318         return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4319 }
4320
4321 #define REG_A5XX_UNKNOWN_E65B                                   0x0000e65b
4322
4323 #define REG_A5XX_SP_GS_OBJ_START_LO                             0x0000e65c
4324
4325 #define REG_A5XX_SP_GS_OBJ_START_HI                             0x0000e65d
4326
4327 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL                          0x0000e704
4328 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK                0x00000003
4329 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT               0
4330 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4331 {
4332         return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4333 }
4334
4335 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL                         0x0000e705
4336 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK               0x00000003
4337 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT              0
4338 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4339 {
4340         return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4341 }
4342 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE                0x00000004
4343
4344 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO              0x0000e706
4345
4346 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI              0x0000e707
4347
4348 #define REG_A5XX_TPL1_VS_TEX_COUNT                              0x0000e700
4349
4350 #define REG_A5XX_TPL1_HS_TEX_COUNT                              0x0000e701
4351
4352 #define REG_A5XX_TPL1_DS_TEX_COUNT                              0x0000e702
4353
4354 #define REG_A5XX_TPL1_GS_TEX_COUNT                              0x0000e703
4355
4356 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO                            0x0000e722
4357
4358 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI                            0x0000e723
4359
4360 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO                            0x0000e724
4361
4362 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI                            0x0000e725
4363
4364 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO                            0x0000e726
4365
4366 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI                            0x0000e727
4367
4368 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO                            0x0000e728
4369
4370 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI                            0x0000e729
4371
4372 #define REG_A5XX_TPL1_VS_TEX_CONST_LO                           0x0000e72a
4373
4374 #define REG_A5XX_TPL1_VS_TEX_CONST_HI                           0x0000e72b
4375
4376 #define REG_A5XX_TPL1_HS_TEX_CONST_LO                           0x0000e72c
4377
4378 #define REG_A5XX_TPL1_HS_TEX_CONST_HI                           0x0000e72d
4379
4380 #define REG_A5XX_TPL1_DS_TEX_CONST_LO                           0x0000e72e
4381
4382 #define REG_A5XX_TPL1_DS_TEX_CONST_HI                           0x0000e72f
4383
4384 #define REG_A5XX_TPL1_GS_TEX_CONST_LO                           0x0000e730
4385
4386 #define REG_A5XX_TPL1_GS_TEX_CONST_HI                           0x0000e731
4387
4388 #define REG_A5XX_TPL1_FS_TEX_COUNT                              0x0000e750
4389
4390 #define REG_A5XX_TPL1_CS_TEX_COUNT                              0x0000e751
4391
4392 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO                            0x0000e75a
4393
4394 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI                            0x0000e75b
4395
4396 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO                            0x0000e75c
4397
4398 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI                            0x0000e75d
4399
4400 #define REG_A5XX_TPL1_FS_TEX_CONST_LO                           0x0000e75e
4401
4402 #define REG_A5XX_TPL1_FS_TEX_CONST_HI                           0x0000e75f
4403
4404 #define REG_A5XX_TPL1_CS_TEX_CONST_LO                           0x0000e760
4405
4406 #define REG_A5XX_TPL1_CS_TEX_CONST_HI                           0x0000e761
4407
4408 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL                       0x0000e764
4409
4410 #define REG_A5XX_HLSQ_CONTROL_0_REG                             0x0000e784
4411 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK              0x00000001
4412 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT             0
4413 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
4414 {
4415         return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
4416 }
4417 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK              0x00000004
4418 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT             2
4419 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
4420 {
4421         return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
4422 }
4423
4424 #define REG_A5XX_HLSQ_CONTROL_1_REG                             0x0000e785
4425 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK        0x0000003f
4426 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT       0
4427 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
4428 {
4429         return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
4430 }
4431
4432 #define REG_A5XX_HLSQ_CONTROL_2_REG                             0x0000e786
4433 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK                 0x000000ff
4434 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT                0
4435 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4436 {
4437         return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4438 }
4439 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK                  0x0000ff00
4440 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT                 8
4441 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4442 {
4443         return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4444 }
4445 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK                0x00ff0000
4446 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT               16
4447 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4448 {
4449         return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4450 }
4451
4452 #define REG_A5XX_HLSQ_CONTROL_3_REG                             0x0000e787
4453 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK          0x000000ff
4454 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT         0
4455 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
4456 {
4457         return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
4458 }
4459
4460 #define REG_A5XX_HLSQ_CONTROL_4_REG                             0x0000e788
4461 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK              0x00ff0000
4462 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT             16
4463 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4464 {
4465         return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4466 }
4467 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK              0xff000000
4468 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT             24
4469 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4470 {
4471         return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4472 }
4473
4474 #define REG_A5XX_HLSQ_UPDATE_CNTL                               0x0000e78a
4475
4476 #define REG_A5XX_HLSQ_VS_CONFIG                                 0x0000e78b
4477 #define A5XX_HLSQ_VS_CONFIG_ENABLED                             0x00000001
4478 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK             0x000000fe
4479 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT            1
4480 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4481 {
4482         return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4483 }
4484 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK               0x00007f00
4485 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT              8
4486 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4487 {
4488         return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
4489 }
4490
4491 #define REG_A5XX_HLSQ_FS_CONFIG                                 0x0000e78c
4492 #define A5XX_HLSQ_FS_CONFIG_ENABLED                             0x00000001
4493 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK             0x000000fe
4494 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT            1
4495 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4496 {
4497         return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4498 }
4499 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK               0x00007f00
4500 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT              8
4501 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4502 {
4503         return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
4504 }
4505
4506 #define REG_A5XX_HLSQ_HS_CONFIG                                 0x0000e78d
4507 #define A5XX_HLSQ_HS_CONFIG_ENABLED                             0x00000001
4508 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK             0x000000fe
4509 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT            1
4510 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4511 {
4512         return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4513 }
4514 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK               0x00007f00
4515 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT              8
4516 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4517 {
4518         return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
4519 }
4520
4521 #define REG_A5XX_HLSQ_DS_CONFIG                                 0x0000e78e
4522 #define A5XX_HLSQ_DS_CONFIG_ENABLED                             0x00000001
4523 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK             0x000000fe
4524 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT            1
4525 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4526 {
4527         return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4528 }
4529 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK               0x00007f00
4530 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT              8
4531 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4532 {
4533         return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
4534 }
4535
4536 #define REG_A5XX_HLSQ_GS_CONFIG                                 0x0000e78f
4537 #define A5XX_HLSQ_GS_CONFIG_ENABLED                             0x00000001
4538 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK             0x000000fe
4539 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT            1
4540 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4541 {
4542         return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4543 }
4544 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK               0x00007f00
4545 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT              8
4546 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4547 {
4548         return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
4549 }
4550
4551 #define REG_A5XX_HLSQ_CS_CONFIG                                 0x0000e790
4552 #define A5XX_HLSQ_CS_CONFIG_ENABLED                             0x00000001
4553 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK             0x000000fe
4554 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT            1
4555 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4556 {
4557         return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4558 }
4559 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK               0x00007f00
4560 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT              8
4561 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4562 {
4563         return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
4564 }
4565
4566 #define REG_A5XX_HLSQ_VS_CNTL                                   0x0000e791
4567 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE                           0x00000001
4568 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK                        0xfffffffe
4569 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT                       1
4570 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
4571 {
4572         return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
4573 }
4574
4575 #define REG_A5XX_HLSQ_FS_CNTL                                   0x0000e792
4576 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE                           0x00000001
4577 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK                        0xfffffffe
4578 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT                       1
4579 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
4580 {
4581         return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
4582 }
4583
4584 #define REG_A5XX_HLSQ_HS_CNTL                                   0x0000e793
4585 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE                           0x00000001
4586 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK                        0xfffffffe
4587 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT                       1
4588 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
4589 {
4590         return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
4591 }
4592
4593 #define REG_A5XX_HLSQ_DS_CNTL                                   0x0000e794
4594 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE                           0x00000001
4595 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK                        0xfffffffe
4596 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT                       1
4597 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
4598 {
4599         return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
4600 }
4601
4602 #define REG_A5XX_HLSQ_GS_CNTL                                   0x0000e795
4603 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE                           0x00000001
4604 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK                        0xfffffffe
4605 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT                       1
4606 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
4607 {
4608         return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
4609 }
4610
4611 #define REG_A5XX_HLSQ_CS_CNTL                                   0x0000e796
4612 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE                           0x00000001
4613 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK                        0xfffffffe
4614 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT                       1
4615 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
4616 {
4617         return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
4618 }
4619
4620 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X                         0x0000e7b9
4621
4622 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y                         0x0000e7ba
4623
4624 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z                         0x0000e7bb
4625
4626 #define REG_A5XX_HLSQ_CS_NDRANGE_0                              0x0000e7b0
4627 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK                  0x00000003
4628 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT                 0
4629 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4630 {
4631         return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4632 }
4633 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK                 0x00000ffc
4634 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT                2
4635 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4636 {
4637         return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4638 }
4639 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK                 0x003ff000
4640 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT                12
4641 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4642 {
4643         return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4644 }
4645 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK                 0xffc00000
4646 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT                22
4647 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4648 {
4649         return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4650 }
4651
4652 #define REG_A5XX_HLSQ_CS_NDRANGE_1                              0x0000e7b1
4653 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK               0xffffffff
4654 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT              0
4655 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4656 {
4657         return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4658 }
4659
4660 #define REG_A5XX_HLSQ_CS_NDRANGE_2                              0x0000e7b2
4661 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK                0xffffffff
4662 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT               0
4663 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4664 {
4665         return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4666 }
4667
4668 #define REG_A5XX_HLSQ_CS_NDRANGE_3                              0x0000e7b3
4669 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK               0xffffffff
4670 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT              0
4671 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4672 {
4673         return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4674 }
4675
4676 #define REG_A5XX_HLSQ_CS_NDRANGE_4                              0x0000e7b4
4677 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK                0xffffffff
4678 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT               0
4679 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
4680 {
4681         return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
4682 }
4683
4684 #define REG_A5XX_HLSQ_CS_NDRANGE_5                              0x0000e7b5
4685 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK               0xffffffff
4686 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT              0
4687 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
4688 {
4689         return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
4690 }
4691
4692 #define REG_A5XX_HLSQ_CS_NDRANGE_6                              0x0000e7b6
4693 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK                0xffffffff
4694 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT               0
4695 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
4696 {
4697         return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
4698 }
4699
4700 #define REG_A5XX_HLSQ_CS_CNTL_0                                 0x0000e7b7
4701 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK                   0x000000ff
4702 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT                  0
4703 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4704 {
4705         return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4706 }
4707 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK                          0x0000ff00
4708 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT                         8
4709 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4710 {
4711         return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4712 }
4713 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK                          0x00ff0000
4714 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT                         16
4715 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4716 {
4717         return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4718 }
4719 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK                  0xff000000
4720 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT                 24
4721 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4722 {
4723         return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4724 }
4725
4726 #define REG_A5XX_HLSQ_CS_CNTL_1                                 0x0000e7b8
4727
4728 #define REG_A5XX_UNKNOWN_E7C0                                   0x0000e7c0
4729
4730 #define REG_A5XX_HLSQ_VS_CONSTLEN                               0x0000e7c3
4731
4732 #define REG_A5XX_HLSQ_VS_INSTRLEN                               0x0000e7c4
4733
4734 #define REG_A5XX_UNKNOWN_E7C5                                   0x0000e7c5
4735
4736 #define REG_A5XX_HLSQ_HS_CONSTLEN                               0x0000e7c8
4737
4738 #define REG_A5XX_HLSQ_HS_INSTRLEN                               0x0000e7c9
4739
4740 #define REG_A5XX_UNKNOWN_E7CA                                   0x0000e7ca
4741
4742 #define REG_A5XX_HLSQ_DS_CONSTLEN                               0x0000e7cd
4743
4744 #define REG_A5XX_HLSQ_DS_INSTRLEN                               0x0000e7ce
4745
4746 #define REG_A5XX_UNKNOWN_E7CF                                   0x0000e7cf
4747
4748 #define REG_A5XX_HLSQ_GS_CONSTLEN                               0x0000e7d2
4749
4750 #define REG_A5XX_HLSQ_GS_INSTRLEN                               0x0000e7d3
4751
4752 #define REG_A5XX_UNKNOWN_E7D4                                   0x0000e7d4
4753
4754 #define REG_A5XX_HLSQ_FS_CONSTLEN                               0x0000e7d7
4755
4756 #define REG_A5XX_HLSQ_FS_INSTRLEN                               0x0000e7d8
4757
4758 #define REG_A5XX_UNKNOWN_E7D9                                   0x0000e7d9
4759
4760 #define REG_A5XX_HLSQ_CS_CONSTLEN                               0x0000e7dc
4761
4762 #define REG_A5XX_HLSQ_CS_INSTRLEN                               0x0000e7dd
4763
4764 #define REG_A5XX_RB_2D_BLIT_CNTL                                0x00002100
4765
4766 #define REG_A5XX_RB_2D_SRC_SOLID_DW0                            0x00002101
4767
4768 #define REG_A5XX_RB_2D_SRC_SOLID_DW1                            0x00002102
4769
4770 #define REG_A5XX_RB_2D_SRC_SOLID_DW2                            0x00002103
4771
4772 #define REG_A5XX_RB_2D_SRC_SOLID_DW3                            0x00002104
4773
4774 #define REG_A5XX_RB_2D_SRC_INFO                                 0x00002107
4775 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK                  0x000000ff
4776 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT                 0
4777 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4778 {
4779         return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
4780 }
4781 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK                     0x00000300
4782 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT                    8
4783 static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
4784 {
4785         return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
4786 }
4787 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK                    0x00000c00
4788 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT                   10
4789 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4790 {
4791         return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
4792 }
4793 #define A5XX_RB_2D_SRC_INFO_FLAGS                               0x00001000
4794
4795 #define REG_A5XX_RB_2D_SRC_LO                                   0x00002108
4796
4797 #define REG_A5XX_RB_2D_SRC_HI                                   0x00002109
4798
4799 #define REG_A5XX_RB_2D_SRC_SIZE                                 0x0000210a
4800 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK                         0x0000ffff
4801 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT                        0
4802 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
4803 {
4804         return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
4805 }
4806 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK                   0xffff0000
4807 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT                  16
4808 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
4809 {
4810         return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
4811 }
4812
4813 #define REG_A5XX_RB_2D_DST_INFO                                 0x00002110
4814 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK                  0x000000ff
4815 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT                 0
4816 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4817 {
4818         return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
4819 }
4820 #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK                     0x00000300
4821 #define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT                    8
4822 static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
4823 {
4824         return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
4825 }
4826 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK                    0x00000c00
4827 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT                   10
4828 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4829 {
4830         return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
4831 }
4832 #define A5XX_RB_2D_DST_INFO_FLAGS                               0x00001000
4833
4834 #define REG_A5XX_RB_2D_DST_LO                                   0x00002111
4835
4836 #define REG_A5XX_RB_2D_DST_HI                                   0x00002112
4837
4838 #define REG_A5XX_RB_2D_DST_SIZE                                 0x00002113
4839 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK                         0x0000ffff
4840 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT                        0
4841 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
4842 {
4843         return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
4844 }
4845 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK                   0xffff0000
4846 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT                  16
4847 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
4848 {
4849         return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
4850 }
4851
4852 #define REG_A5XX_RB_2D_SRC_FLAGS_LO                             0x00002140
4853
4854 #define REG_A5XX_RB_2D_SRC_FLAGS_HI                             0x00002141
4855
4856 #define REG_A5XX_RB_2D_DST_FLAGS_LO                             0x00002143
4857
4858 #define REG_A5XX_RB_2D_DST_FLAGS_HI                             0x00002144
4859
4860 #define REG_A5XX_GRAS_2D_BLIT_CNTL                              0x00002180
4861
4862 #define REG_A5XX_GRAS_2D_SRC_INFO                               0x00002181
4863 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK                0x000000ff
4864 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT               0
4865 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4866 {
4867         return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
4868 }
4869 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK                   0x00000300
4870 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT                  8
4871 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
4872 {
4873         return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
4874 }
4875 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK                  0x00000c00
4876 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT                 10
4877 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4878 {
4879         return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
4880 }
4881 #define A5XX_GRAS_2D_SRC_INFO_FLAGS                             0x00001000
4882
4883 #define REG_A5XX_GRAS_2D_DST_INFO                               0x00002182
4884 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK                0x000000ff
4885 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT               0
4886 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4887 {
4888         return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
4889 }
4890 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK                   0x00000300
4891 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT                  8
4892 static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
4893 {
4894         return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
4895 }
4896 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK                  0x00000c00
4897 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT                 10
4898 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4899 {
4900         return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
4901 }
4902 #define A5XX_GRAS_2D_DST_INFO_FLAGS                             0x00001000
4903
4904 #define REG_A5XX_UNKNOWN_2100                                   0x00002100
4905
4906 #define REG_A5XX_UNKNOWN_2180                                   0x00002180
4907
4908 #define REG_A5XX_UNKNOWN_2184                                   0x00002184
4909
4910 #define REG_A5XX_TEX_SAMP_0                                     0x00000000
4911 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR                   0x00000001
4912 #define A5XX_TEX_SAMP_0_XY_MAG__MASK                            0x00000006
4913 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT                           1
4914 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
4915 {
4916         return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
4917 }
4918 #define A5XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000018
4919 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT                           3
4920 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
4921 {
4922         return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
4923 }
4924 #define A5XX_TEX_SAMP_0_WRAP_S__MASK                            0x000000e0
4925 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT                           5
4926 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
4927 {
4928         return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
4929 }
4930 #define A5XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000700
4931 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT                           8
4932 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
4933 {
4934         return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
4935 }
4936 #define A5XX_TEX_SAMP_0_WRAP_R__MASK                            0x00003800
4937 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT                           11
4938 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
4939 {
4940         return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
4941 }
4942 #define A5XX_TEX_SAMP_0_ANISO__MASK                             0x0001c000
4943 #define A5XX_TEX_SAMP_0_ANISO__SHIFT                            14
4944 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
4945 {
4946         return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
4947 }
4948 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK                          0xfff80000
4949 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT                         19
4950 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
4951 {
4952         return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
4953 }
4954
4955 #define REG_A5XX_TEX_SAMP_1                                     0x00000001
4956 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK                      0x0000000e
4957 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT                     1
4958 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4959 {
4960         return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4961 }
4962 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF                  0x00000010
4963 #define A5XX_TEX_SAMP_1_UNNORM_COORDS                           0x00000020
4964 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR                    0x00000040
4965 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK                           0x000fff00
4966 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT                          8
4967 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
4968 {
4969         return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
4970 }
4971 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK                           0xfff00000
4972 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT                          20
4973 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
4974 {
4975         return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
4976 }
4977
4978 #define REG_A5XX_TEX_SAMP_2                                     0x00000002
4979 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK                     0xfffffff0
4980 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT                    4
4981 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
4982 {
4983         return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
4984 }
4985
4986 #define REG_A5XX_TEX_SAMP_3                                     0x00000003
4987
4988 #define REG_A5XX_TEX_CONST_0                                    0x00000000
4989 #define A5XX_TEX_CONST_0_TILE_MODE__MASK                        0x00000003
4990 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT                       0
4991 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
4992 {
4993         return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
4994 }
4995 #define A5XX_TEX_CONST_0_SRGB                                   0x00000004
4996 #define A5XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
4997 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
4998 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
4999 {
5000         return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
5001 }
5002 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
5003 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
5004 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
5005 {
5006         return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
5007 }
5008 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
5009 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
5010 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
5011 {
5012         return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
5013 }
5014 #define A5XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
5015 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
5016 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
5017 {
5018         return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
5019 }
5020 #define A5XX_TEX_CONST_0_MIPLVLS__MASK                          0x000f0000
5021 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT                         16
5022 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5023 {
5024         return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
5025 }
5026 #define A5XX_TEX_CONST_0_SAMPLES__MASK                          0x00300000
5027 #define A5XX_TEX_CONST_0_SAMPLES__SHIFT                         20
5028 static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5029 {
5030         return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK;
5031 }
5032 #define A5XX_TEX_CONST_0_FMT__MASK                              0x3fc00000
5033 #define A5XX_TEX_CONST_0_FMT__SHIFT                             22
5034 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
5035 {
5036         return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
5037 }
5038 #define A5XX_TEX_CONST_0_SWAP__MASK                             0xc0000000
5039 #define A5XX_TEX_CONST_0_SWAP__SHIFT                            30
5040 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5041 {
5042         return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
5043 }
5044
5045 #define REG_A5XX_TEX_CONST_1                                    0x00000001
5046 #define A5XX_TEX_CONST_1_WIDTH__MASK                            0x00007fff
5047 #define A5XX_TEX_CONST_1_WIDTH__SHIFT                           0
5048 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
5049 {
5050         return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
5051 }
5052 #define A5XX_TEX_CONST_1_HEIGHT__MASK                           0x3fff8000
5053 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT                          15
5054 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
5055 {
5056         return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
5057 }
5058
5059 #define REG_A5XX_TEX_CONST_2                                    0x00000002
5060 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK                        0x0000000f
5061 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT                       0
5062 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
5063 {
5064         return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
5065 }
5066 #define A5XX_TEX_CONST_2_PITCH__MASK                            0x1fffff80
5067 #define A5XX_TEX_CONST_2_PITCH__SHIFT                           7
5068 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
5069 {
5070         return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
5071 }
5072 #define A5XX_TEX_CONST_2_TYPE__MASK                             0x60000000
5073 #define A5XX_TEX_CONST_2_TYPE__SHIFT                            29
5074 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
5075 {
5076         return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5077 }
5078
5079 #define REG_A5XX_TEX_CONST_3                                    0x00000003
5080 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK                      0x00003fff
5081 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT                     0
5082 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5083 {
5084         return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5085 }
5086 #define A5XX_TEX_CONST_3_FLAG                                   0x10000000
5087
5088 #define REG_A5XX_TEX_CONST_4                                    0x00000004
5089 #define A5XX_TEX_CONST_4_BASE_LO__MASK                          0xffffffe0
5090 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT                         5
5091 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
5092 {
5093         return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
5094 }
5095
5096 #define REG_A5XX_TEX_CONST_5                                    0x00000005
5097 #define A5XX_TEX_CONST_5_BASE_HI__MASK                          0x0001ffff
5098 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT                         0
5099 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
5100 {
5101         return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
5102 }
5103 #define A5XX_TEX_CONST_5_DEPTH__MASK                            0x3ffe0000
5104 #define A5XX_TEX_CONST_5_DEPTH__SHIFT                           17
5105 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
5106 {
5107         return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
5108 }
5109
5110 #define REG_A5XX_TEX_CONST_6                                    0x00000006
5111
5112 #define REG_A5XX_TEX_CONST_7                                    0x00000007
5113
5114 #define REG_A5XX_TEX_CONST_8                                    0x00000008
5115
5116 #define REG_A5XX_TEX_CONST_9                                    0x00000009
5117
5118 #define REG_A5XX_TEX_CONST_10                                   0x0000000a
5119
5120 #define REG_A5XX_TEX_CONST_11                                   0x0000000b
5121
5122 #define REG_A5XX_SSBO_0_0                                       0x00000000
5123 #define A5XX_SSBO_0_0_BASE_LO__MASK                             0xffffffe0
5124 #define A5XX_SSBO_0_0_BASE_LO__SHIFT                            5
5125 static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
5126 {
5127         return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
5128 }
5129
5130 #define REG_A5XX_SSBO_0_1                                       0x00000001
5131 #define A5XX_SSBO_0_1_PITCH__MASK                               0x003fffff
5132 #define A5XX_SSBO_0_1_PITCH__SHIFT                              0
5133 static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
5134 {
5135         return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
5136 }
5137
5138 #define REG_A5XX_SSBO_0_2                                       0x00000002
5139 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK                         0x03fff000
5140 #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT                        12
5141 static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
5142 {
5143         return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
5144 }
5145
5146 #define REG_A5XX_SSBO_0_3                                       0x00000003
5147 #define A5XX_SSBO_0_3_CPP__MASK                                 0x0000003f
5148 #define A5XX_SSBO_0_3_CPP__SHIFT                                0
5149 static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
5150 {
5151         return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
5152 }
5153
5154 #define REG_A5XX_SSBO_1_0                                       0x00000000
5155 #define A5XX_SSBO_1_0_FMT__MASK                                 0x0000ff00
5156 #define A5XX_SSBO_1_0_FMT__SHIFT                                8
5157 static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
5158 {
5159         return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
5160 }
5161 #define A5XX_SSBO_1_0_WIDTH__MASK                               0xffff0000
5162 #define A5XX_SSBO_1_0_WIDTH__SHIFT                              16
5163 static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
5164 {
5165         return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
5166 }
5167
5168 #define REG_A5XX_SSBO_1_1                                       0x00000001
5169 #define A5XX_SSBO_1_1_HEIGHT__MASK                              0x0000ffff
5170 #define A5XX_SSBO_1_1_HEIGHT__SHIFT                             0
5171 static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
5172 {
5173         return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
5174 }
5175 #define A5XX_SSBO_1_1_DEPTH__MASK                               0xffff0000
5176 #define A5XX_SSBO_1_1_DEPTH__SHIFT                              16
5177 static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
5178 {
5179         return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
5180 }
5181
5182 #define REG_A5XX_SSBO_2_0                                       0x00000000
5183 #define A5XX_SSBO_2_0_BASE_LO__MASK                             0xffffffff
5184 #define A5XX_SSBO_2_0_BASE_LO__SHIFT                            0
5185 static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
5186 {
5187         return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
5188 }
5189
5190 #define REG_A5XX_SSBO_2_1                                       0x00000001
5191 #define A5XX_SSBO_2_1_BASE_HI__MASK                             0xffffffff
5192 #define A5XX_SSBO_2_1_BASE_HI__SHIFT                            0
5193 static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
5194 {
5195         return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
5196 }
5197
5198
5199 #endif /* A5XX_XML */