drivers/gpu/drm/msm/adreno/adreno_device.c

   1 /*
   2  * Copyright (C) 2013-2014 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "adreno_gpu.h"
  21
  22 #define ANY_ID 0xff
  23
  24 bool hang_debug = false;
  25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  26 module_param_named(hang_debug, hang_debug, bool, 0600);
  27
  28 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
  29 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
  30
  31 static const struct adreno_info gpulist[] = {
  32         {
  33                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  34                 .revn  = 305,
  35                 .name  = "A305",
  36                 .pm4fw = "/*(DEBLOBBED)*/",
  37                 .pfpfw = "/*(DEBLOBBED)*/",
  38                 .gmem  = SZ_256K,
  39                 .init  = a3xx_gpu_init,
  40         }, {
  41                 .rev   = ADRENO_REV(3, 0, 6, 0),
  42                 .revn  = 307,        /* because a305c is revn==306 */
  43                 .name  = "A306",
  44                 .pm4fw = "/*(DEBLOBBED)*/",
  45                 .pfpfw = "/*(DEBLOBBED)*/",
  46                 .gmem  = SZ_128K,
  47                 .init  = a3xx_gpu_init,
  48         }, {
  49                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  50                 .revn  = 320,
  51                 .name  = "A320",
  52                 .pm4fw = "/*(DEBLOBBED)*/",
  53                 .pfpfw = "/*(DEBLOBBED)*/",
  54                 .gmem  = SZ_512K,
  55                 .init  = a3xx_gpu_init,
  56         }, {
  57                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  58                 .revn  = 330,
  59                 .name  = "A330",
  60                 .pm4fw = "/*(DEBLOBBED)*/",
  61                 .pfpfw = "/*(DEBLOBBED)*/",
  62                 .gmem  = SZ_1M,
  63                 .init  = a3xx_gpu_init,
  64         }, {
  65                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
  66                 .revn  = 420,
  67                 .name  = "A420",
  68                 .pm4fw = "/*(DEBLOBBED)*/",
  69                 .pfpfw = "/*(DEBLOBBED)*/",
  70                 .gmem  = (SZ_1M + SZ_512K),
  71                 .init  = a4xx_gpu_init,
  72         }, {
  73                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
  74                 .revn  = 430,
  75                 .name  = "A430",
  76                 .pm4fw = "/*(DEBLOBBED)*/",
  77                 .pfpfw = "/*(DEBLOBBED)*/",
  78                 .gmem  = (SZ_1M + SZ_512K),
  79                 .init  = a4xx_gpu_init,
  80         },
  81 };
  82
  83 /*(DEBLOBBED)*/
  84
  85 static inline bool _rev_match(uint8_t entry, uint8_t id)
  86 {
  87         return (entry == ANY_ID) || (entry == id);
  88 }
  89
  90 const struct adreno_info *adreno_info(struct adreno_rev rev)
  91 {
  92         int i;
  93
  94         /* identify gpu: */
  95         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
  96                 const struct adreno_info *info = &gpulist[i];
  97                 if (_rev_match(info->rev.core, rev.core) &&
  98                                 _rev_match(info->rev.major, rev.major) &&
  99                                 _rev_match(info->rev.minor, rev.minor) &&
 100                                 _rev_match(info->rev.patchid, rev.patchid))
 101                         return info;
 102         }
 103
 104         return NULL;
 105 }
 106
 107 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 108 {
 109         struct msm_drm_private *priv = dev->dev_private;
 110         struct platform_device *pdev = priv->gpu_pdev;
 111         struct adreno_platform_config *config;
 112         struct adreno_rev rev;
 113         const struct adreno_info *info;
 114         struct msm_gpu *gpu = NULL;
 115
 116         if (!pdev) {
 117                 dev_err(dev->dev, "no adreno device\n");
 118                 return NULL;
 119         }
 120
 121         config = pdev->dev.platform_data;
 122         rev = config->rev;
 123         info = adreno_info(config->rev);
 124
 125         if (!info) {
 126                 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 127                                 rev.core, rev.major, rev.minor, rev.patchid);
 128                 return NULL;
 129         }
 130
 131         DBG("Found GPU: %u.%u.%u.%u",  rev.core, rev.major,
 132                         rev.minor, rev.patchid);
 133
 134         gpu = info->init(dev);
 135         if (IS_ERR(gpu)) {
 136                 dev_warn(dev->dev, "failed to load adreno gpu\n");
 137                 gpu = NULL;
 138                 /* not fatal */
 139         }
 140
 141         if (gpu) {
 142                 int ret;
 143                 mutex_lock(&dev->struct_mutex);
 144                 gpu->funcs->pm_resume(gpu);
 145                 mutex_unlock(&dev->struct_mutex);
 146                 ret = gpu->funcs->hw_init(gpu);
 147                 if (ret) {
 148                         dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
 149                         gpu->funcs->destroy(gpu);
 150                         gpu = NULL;
 151                 } else {
 152                         /* give inactive pm a chance to kick in: */
 153                         msm_gpu_retire(gpu);
 154                 }
 155         }
 156
 157         return gpu;
 158 }
 159
 160 static void set_gpu_pdev(struct drm_device *dev,
 161                 struct platform_device *pdev)
 162 {
 163         struct msm_drm_private *priv = dev->dev_private;
 164         priv->gpu_pdev = pdev;
 165 }
 166
 167 static int adreno_bind(struct device *dev, struct device *master, void *data)
 168 {
 169         static struct adreno_platform_config config = {};
 170         struct device_node *child, *node = dev->of_node;
 171         u32 val;
 172         int ret;
 173
 174         ret = of_property_read_u32(node, "qcom,chipid", &val);
 175         if (ret) {
 176                 dev_err(dev, "could not find chipid: %d\n", ret);
 177                 return ret;
 178         }
 179
 180         config.rev = ADRENO_REV((val >> 24) & 0xff,
 181                         (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
 182
 183         /* find clock rates: */
 184         config.fast_rate = 0;
 185         config.slow_rate = ~0;
 186         for_each_child_of_node(node, child) {
 187                 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
 188                         struct device_node *pwrlvl;
 189                         for_each_child_of_node(child, pwrlvl) {
 190                                 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
 191                                 if (ret) {
 192                                         dev_err(dev, "could not find gpu-freq: %d\n", ret);
 193                                         return ret;
 194                                 }
 195                                 config.fast_rate = max(config.fast_rate, val);
 196                                 config.slow_rate = min(config.slow_rate, val);
 197                         }
 198                 }
 199         }
 200
 201         if (!config.fast_rate) {
 202                 dev_err(dev, "could not find clk rates\n");
 203                 return -ENXIO;
 204         }
 205
 206         dev->platform_data = &config;
 207         set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
 208         return 0;
 209 }
 210
 211 static void adreno_unbind(struct device *dev, struct device *master,
 212                 void *data)
 213 {
 214         set_gpu_pdev(dev_get_drvdata(master), NULL);
 215 }
 216
 217 static const struct component_ops a3xx_ops = {
 218                 .bind   = adreno_bind,
 219                 .unbind = adreno_unbind,
 220 };
 221
 222 static int adreno_probe(struct platform_device *pdev)
 223 {
 224         return component_add(&pdev->dev, &a3xx_ops);
 225 }
 226
 227 static int adreno_remove(struct platform_device *pdev)
 228 {
 229         component_del(&pdev->dev, &a3xx_ops);
 230         return 0;
 231 }
 232
 233 static const struct of_device_id dt_match[] = {
 234         { .compatible = "qcom,adreno-3xx" },
 235         /* for backwards compat w/ downstream kgsl DT files: */
 236         { .compatible = "qcom,kgsl-3d0" },
 237         {}
 238 };
 239
 240 static struct platform_driver adreno_driver = {
 241         .probe = adreno_probe,
 242         .remove = adreno_remove,
 243         .driver = {
 244                 .name = "adreno",
 245                 .of_match_table = dt_match,
 246         },
 247 };
 248
 249 void __init adreno_register(void)
 250 {
 251         platform_driver_register(&adreno_driver);
 252 }
 253
 254 void __exit adreno_unregister(void)
 255 {
 256         platform_driver_unregister(&adreno_driver);
 257 }