drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

   1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include "dpu_kms.h"
  14 #include "dpu_hw_catalog.h"
  15 #include "dpu_hwio.h"
  16 #include "dpu_hw_lm.h"
  17 #include "dpu_hw_mdss.h"
  18 #include "dpu_dbg.h"
  19 #include "dpu_kms.h"
  20
  21 #define LM_OP_MODE                        0x00
  22 #define LM_OUT_SIZE                       0x04
  23 #define LM_BORDER_COLOR_0                 0x08
  24 #define LM_BORDER_COLOR_1                 0x010
  25
  26 /* These register are offset to mixer base + stage base */
  27 #define LM_BLEND0_OP                     0x00
  28 #define LM_BLEND0_CONST_ALPHA            0x04
  29 #define LM_FG_COLOR_FILL_COLOR_0         0x08
  30 #define LM_FG_COLOR_FILL_COLOR_1         0x0C
  31 #define LM_FG_COLOR_FILL_SIZE            0x10
  32 #define LM_FG_COLOR_FILL_XY              0x14
  33
  34 #define LM_BLEND0_FG_ALPHA               0x04
  35 #define LM_BLEND0_BG_ALPHA               0x08
  36
  37 #define LM_MISR_CTRL                    0x310
  38 #define LM_MISR_SIGNATURE               0x314
  39
  40 static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
  41                 struct dpu_mdss_cfg *m,
  42                 void __iomem *addr,
  43                 struct dpu_hw_blk_reg_map *b)
  44 {
  45         int i;
  46
  47         for (i = 0; i < m->mixer_count; i++) {
  48                 if (mixer == m->mixer[i].id) {
  49                         b->base_off = addr;
  50                         b->blk_off = m->mixer[i].base;
  51                         b->length = m->mixer[i].len;
  52                         b->hwversion = m->hwversion;
  53                         b->log_mask = DPU_DBG_MASK_LM;
  54                         return &m->mixer[i];
  55                 }
  56         }
  57
  58         return ERR_PTR(-ENOMEM);
  59 }
  60
  61 /**
  62  * _stage_offset(): returns the relative offset of the blend registers
  63  * for the stage to be setup
  64  * @c:     mixer ctx contains the mixer to be programmed
  65  * @stage: stage index to setup
  66  */
  67 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage)
  68 {
  69         const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk;
  70         int rc;
  71
  72         if (stage == DPU_STAGE_BASE)
  73                 rc = -EINVAL;
  74         else if (stage <= sblk->maxblendstages)
  75                 rc = sblk->blendstage_base[stage - DPU_STAGE_0];
  76         else
  77                 rc = -EINVAL;
  78
  79         return rc;
  80 }
  81
  82 static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx,
  83                 struct dpu_hw_mixer_cfg *mixer)
  84 {
  85         struct dpu_hw_blk_reg_map *c = &ctx->hw;
  86         u32 outsize;
  87         u32 op_mode;
  88
  89         op_mode = DPU_REG_READ(c, LM_OP_MODE);
  90
  91         outsize = mixer->out_height << 16 | mixer->out_width;
  92         DPU_REG_WRITE(c, LM_OUT_SIZE, outsize);
  93
  94         /* SPLIT_LEFT_RIGHT */
  95         if (mixer->right_mixer)
  96                 op_mode |= BIT(31);
  97         else
  98                 op_mode &= ~BIT(31);
  99         DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
 100 }
 101
 102 static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
 103                 struct dpu_mdss_color *color,
 104                 u8 border_en)
 105 {
 106         struct dpu_hw_blk_reg_map *c = &ctx->hw;
 107
 108         if (border_en) {
 109                 DPU_REG_WRITE(c, LM_BORDER_COLOR_0,
 110                         (color->color_0 & 0xFFF) |
 111                         ((color->color_1 & 0xFFF) << 0x10));
 112                 DPU_REG_WRITE(c, LM_BORDER_COLOR_1,
 113                         (color->color_2 & 0xFFF) |
 114                         ((color->color_3 & 0xFFF) << 0x10));
 115         }
 116 }
 117
 118 static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx,
 119         u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
 120 {
 121         struct dpu_hw_blk_reg_map *c = &ctx->hw;
 122         int stage_off;
 123         u32 const_alpha;
 124
 125         if (stage == DPU_STAGE_BASE)
 126                 return;
 127
 128         stage_off = _stage_offset(ctx, stage);
 129         if (WARN_ON(stage_off < 0))
 130                 return;
 131
 132         const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
 133         DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
 134         DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
 135 }
 136
 137 static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
 138         u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
 139 {
 140         struct dpu_hw_blk_reg_map *c = &ctx->hw;
 141         int stage_off;
 142
 143         if (stage == DPU_STAGE_BASE)
 144                 return;
 145
 146         stage_off = _stage_offset(ctx, stage);
 147         if (WARN_ON(stage_off < 0))
 148                 return;
 149
 150         DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
 151         DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
 152         DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
 153 }
 154
 155 static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
 156         uint32_t mixer_op_mode)
 157 {
 158         struct dpu_hw_blk_reg_map *c = &ctx->hw;
 159         int op_mode;
 160
 161         /* read the existing op_mode configuration */
 162         op_mode = DPU_REG_READ(c, LM_OP_MODE);
 163
 164         op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode;
 165
 166         DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
 167 }
 168
 169 static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer,
 170                         void *cfg)
 171 {
 172 }
 173
 174 static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx,
 175                                 bool enable, u32 frame_count)
 176 {
 177         struct dpu_hw_blk_reg_map *c = &ctx->hw;
 178         u32 config = 0;
 179
 180         DPU_REG_WRITE(c, LM_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
 181         /* clear misr data */
 182         wmb();
 183
 184         if (enable)
 185                 config = (frame_count & MISR_FRAME_COUNT_MASK) |
 186                         MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
 187
 188         DPU_REG_WRITE(c, LM_MISR_CTRL, config);
 189 }
 190
 191 static u32 dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx)
 192 {
 193         struct dpu_hw_blk_reg_map *c = &ctx->hw;
 194
 195         return DPU_REG_READ(c, LM_MISR_SIGNATURE);
 196 }
 197
 198 static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
 199                 struct dpu_hw_lm_ops *ops,
 200                 unsigned long features)
 201 {
 202         ops->setup_mixer_out = dpu_hw_lm_setup_out;
 203         if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion))
 204                 ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845;
 205         else
 206                 ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
 207         ops->setup_alpha_out = dpu_hw_lm_setup_color3;
 208         ops->setup_border_color = dpu_hw_lm_setup_border_color;
 209         ops->setup_gc = dpu_hw_lm_gc;
 210         ops->setup_misr = dpu_hw_lm_setup_misr;
 211         ops->collect_misr = dpu_hw_lm_collect_misr;
 212 };
 213
 214 static struct dpu_hw_blk_ops dpu_hw_ops = {
 215         .start = NULL,
 216         .stop = NULL,
 217 };
 218
 219 struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
 220                 void __iomem *addr,
 221                 struct dpu_mdss_cfg *m)
 222 {
 223         struct dpu_hw_mixer *c;
 224         struct dpu_lm_cfg *cfg;
 225         int rc;
 226
 227         c = kzalloc(sizeof(*c), GFP_KERNEL);
 228         if (!c)
 229                 return ERR_PTR(-ENOMEM);
 230
 231         cfg = _lm_offset(idx, m, addr, &c->hw);
 232         if (IS_ERR_OR_NULL(cfg)) {
 233                 kfree(c);
 234                 return ERR_PTR(-EINVAL);
 235         }
 236
 237         /* Assign ops */
 238         c->idx = idx;
 239         c->cap = cfg;
 240         _setup_mixer_ops(m, &c->ops, c->cap->features);
 241
 242         rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops);
 243         if (rc) {
 244                 DPU_ERROR("failed to init hw blk %d\n", rc);
 245                 goto blk_init_error;
 246         }
 247
 248         return c;
 249
 250 blk_init_error:
 251         kzfree(c);
 252
 253         return ERR_PTR(rc);
 254 }
 255
 256 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
 257 {
 258         if (lm)
 259                 dpu_hw_blk_destroy(&lm->base);
 260         kfree(lm);
 261 }