1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #ifndef _DPU_HW_SSPP_H
14 #define _DPU_HW_SSPP_H
16 #include "dpu_hw_catalog.h"
17 #include "dpu_hw_mdss.h"
18 #include "dpu_hw_util.h"
19 #include "dpu_hw_blk.h"
20 #include "dpu_formats.h"
27 #define DPU_SSPP_FLIP_LR BIT(0)
28 #define DPU_SSPP_FLIP_UD BIT(1)
29 #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2)
30 #define DPU_SSPP_ROT_90 BIT(3)
31 #define DPU_SSPP_SOLID_FILL BIT(4)
34 * Define all scaler feature bits in catalog
36 #define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \
37 (1UL << DPU_SSPP_SCALER_QSEED2) | \
38 (1UL << DPU_SSPP_SCALER_QSEED3))
53 * DPU_SSPP_RECT_SOLO - multirect disabled
54 * DPU_SSPP_RECT_0 - rect0 of a multirect pipe
55 * DPU_SSPP_RECT_1 - rect1 of a multirect pipe
57 * Note: HW supports multirect with either RECT0 or
58 * RECT1. Considering no benefit of such configs over
59 * SOLO mode and to keep the plane management simple,
60 * we dont support single rect multirect configs.
62 enum dpu_sspp_multirect_index {
63 DPU_SSPP_RECT_SOLO = 0,
68 enum dpu_sspp_multirect_mode {
69 DPU_SSPP_MULTIRECT_NONE = 0,
70 DPU_SSPP_MULTIRECT_PARALLEL,
71 DPU_SSPP_MULTIRECT_TIME_MX,
81 DPU_SCALE_FILTER_NEAREST = 0,
83 DPU_SCALE_FILTER_PCMN,
88 enum dpu_hw_filter_alpa {
89 DPU_SCALE_ALPHA_PIXEL_REP,
93 enum dpu_hw_filter_yuv {
100 struct dpu_hw_sharp_cfg {
107 struct dpu_hw_pixel_ext {
108 /* scaling factors are enabled for this input layer */
109 uint8_t enable_pxl_ext;
111 int init_phase_x[DPU_MAX_PLANES];
112 int phase_step_x[DPU_MAX_PLANES];
113 int init_phase_y[DPU_MAX_PLANES];
114 int phase_step_y[DPU_MAX_PLANES];
117 * Number of pixels extension in left, right, top and bottom direction
118 * for all color components. This pixel value for each color component
119 * should be sum of fetch + repeat pixels.
121 int num_ext_pxls_left[DPU_MAX_PLANES];
122 int num_ext_pxls_right[DPU_MAX_PLANES];
123 int num_ext_pxls_top[DPU_MAX_PLANES];
124 int num_ext_pxls_btm[DPU_MAX_PLANES];
127 * Number of pixels needs to be overfetched in left, right, top and
128 * bottom directions from source image for scaling.
130 int left_ftch[DPU_MAX_PLANES];
131 int right_ftch[DPU_MAX_PLANES];
132 int top_ftch[DPU_MAX_PLANES];
133 int btm_ftch[DPU_MAX_PLANES];
136 * Number of pixels needs to be repeated in left, right, top and
137 * bottom directions for scaling.
139 int left_rpt[DPU_MAX_PLANES];
140 int right_rpt[DPU_MAX_PLANES];
141 int top_rpt[DPU_MAX_PLANES];
142 int btm_rpt[DPU_MAX_PLANES];
144 uint32_t roi_w[DPU_MAX_PLANES];
145 uint32_t roi_h[DPU_MAX_PLANES];
148 * Filter type to be used for scaling in horizontal and vertical
151 enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
152 enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
157 * struct dpu_hw_pipe_cfg : Pipe description
158 * @layout: format layout information for programming buffer to hardware
159 * @src_rect: src ROI, caller takes into account the different operations
160 * such as decimation, flip etc to program this field
161 * @dest_rect: destination ROI.
162 * @index: index of the rectangle of SSPP
163 * @mode: parallel or time multiplex multirect mode
165 struct dpu_hw_pipe_cfg {
166 struct dpu_hw_fmt_layout layout;
167 struct drm_rect src_rect;
168 struct drm_rect dst_rect;
169 enum dpu_sspp_multirect_index index;
170 enum dpu_sspp_multirect_mode mode;
174 * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
175 * @danger_lut: LUT for generate danger level based on fill level
176 * @safe_lut: LUT for generate safe level based on fill level
177 * @creq_lut: LUT for generate creq level based on fill level
178 * @creq_vblank: creq value generated to vbif during vertical blanking
179 * @danger_vblank: danger value generated during vertical blanking
180 * @vblank_en: enable creq_vblank and danger_vblank during vblank
181 * @danger_safe_en: enable danger safe generation
183 struct dpu_hw_pipe_qos_cfg {
194 * enum CDP preload ahead address size
197 DPU_SSPP_CDP_PRELOAD_AHEAD_32,
198 DPU_SSPP_CDP_PRELOAD_AHEAD_64
202 * struct dpu_hw_pipe_cdp_cfg : CDP configuration
203 * @enable: true to enable CDP
204 * @ubwc_meta_enable: true to enable ubwc metadata preload
205 * @tile_amortize_enable: true to enable amortization control for tile format
206 * @preload_ahead: number of request to preload ahead
207 * DPU_SSPP_CDP_PRELOAD_AHEAD_32,
208 * DPU_SSPP_CDP_PRELOAD_AHEAD_64
210 struct dpu_hw_pipe_cdp_cfg {
212 bool ubwc_meta_enable;
213 bool tile_amortize_enable;
218 * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
219 * @size: size to prefill in bytes, or zero to disable
220 * @time: time to prefill in usec, or zero to disable
222 struct dpu_hw_pipe_ts_cfg {
228 * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
229 * Caller must call the init function to get the pipe context for each pipe
230 * Assumption is these functions will be called after clocks are enabled
232 struct dpu_hw_sspp_ops {
234 * setup_format - setup pixel format cropping rectangle, flip
235 * @ctx: Pointer to pipe context
236 * @cfg: Pointer to pipe config structure
237 * @flags: Extra flags for format config
238 * @index: rectangle index in multirect
240 void (*setup_format)(struct dpu_hw_pipe *ctx,
241 const struct dpu_format *fmt, u32 flags,
242 enum dpu_sspp_multirect_index index);
245 * setup_rects - setup pipe ROI rectangles
246 * @ctx: Pointer to pipe context
247 * @cfg: Pointer to pipe config structure
248 * @index: rectangle index in multirect
250 void (*setup_rects)(struct dpu_hw_pipe *ctx,
251 struct dpu_hw_pipe_cfg *cfg,
252 enum dpu_sspp_multirect_index index);
255 * setup_pe - setup pipe pixel extension
256 * @ctx: Pointer to pipe context
257 * @pe_ext: Pointer to pixel ext settings
259 void (*setup_pe)(struct dpu_hw_pipe *ctx,
260 struct dpu_hw_pixel_ext *pe_ext);
263 * setup_sourceaddress - setup pipe source addresses
264 * @ctx: Pointer to pipe context
265 * @cfg: Pointer to pipe config structure
266 * @index: rectangle index in multirect
268 void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
269 struct dpu_hw_pipe_cfg *cfg,
270 enum dpu_sspp_multirect_index index);
273 * setup_csc - setup color space coversion
274 * @ctx: Pointer to pipe context
275 * @data: Pointer to config structure
277 void (*setup_csc)(struct dpu_hw_pipe *ctx, struct dpu_csc_cfg *data);
280 * setup_solidfill - enable/disable colorfill
281 * @ctx: Pointer to pipe context
282 * @const_color: Fill color value
284 * @index: rectangle index in multirect
286 void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
287 enum dpu_sspp_multirect_index index);
290 * setup_multirect - setup multirect configuration
291 * @ctx: Pointer to pipe context
292 * @index: rectangle index in multirect
293 * @mode: parallel fetch / time multiplex multirect mode
296 void (*setup_multirect)(struct dpu_hw_pipe *ctx,
297 enum dpu_sspp_multirect_index index,
298 enum dpu_sspp_multirect_mode mode);
301 * setup_sharpening - setup sharpening
302 * @ctx: Pointer to pipe context
303 * @cfg: Pointer to config structure
305 void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
306 struct dpu_hw_sharp_cfg *cfg);
309 * setup_danger_safe_lut - setup danger safe LUTs
310 * @ctx: Pointer to pipe context
311 * @cfg: Pointer to pipe QoS configuration
314 void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
315 struct dpu_hw_pipe_qos_cfg *cfg);
318 * setup_creq_lut - setup CREQ LUT
319 * @ctx: Pointer to pipe context
320 * @cfg: Pointer to pipe QoS configuration
323 void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
324 struct dpu_hw_pipe_qos_cfg *cfg);
327 * setup_qos_ctrl - setup QoS control
328 * @ctx: Pointer to pipe context
329 * @cfg: Pointer to pipe QoS configuration
332 void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
333 struct dpu_hw_pipe_qos_cfg *cfg);
336 * setup_histogram - setup histograms
337 * @ctx: Pointer to pipe context
338 * @cfg: Pointer to histogram configuration
340 void (*setup_histogram)(struct dpu_hw_pipe *ctx,
344 * setup_scaler - setup scaler
345 * @ctx: Pointer to pipe context
346 * @pipe_cfg: Pointer to pipe configuration
347 * @pe_cfg: Pointer to pixel extension configuration
348 * @scaler_cfg: Pointer to scaler configuration
350 void (*setup_scaler)(struct dpu_hw_pipe *ctx,
351 struct dpu_hw_pipe_cfg *pipe_cfg,
352 struct dpu_hw_pixel_ext *pe_cfg,
356 * get_scaler_ver - get scaler h/w version
357 * @ctx: Pointer to pipe context
359 u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
362 * setup_cdp - setup client driven prefetch
363 * @ctx: Pointer to pipe context
364 * @cfg: Pointer to cdp configuration
366 void (*setup_cdp)(struct dpu_hw_pipe *ctx,
367 struct dpu_hw_pipe_cdp_cfg *cfg);
371 * struct dpu_hw_pipe - pipe description
372 * @base: hardware block base structure
373 * @hw: block hardware details
374 * @catalog: back pointer to catalog
375 * @mdp: pointer to associated mdp portion of the catalog
377 * @cap: pointer to layer_cfg
378 * @ops: pointer to operations possible for this pipe
381 struct dpu_hw_blk base;
382 struct dpu_hw_blk_reg_map hw;
383 struct dpu_mdss_cfg *catalog;
384 struct dpu_mdp_cfg *mdp;
388 const struct dpu_sspp_cfg *cap;
391 struct dpu_hw_sspp_ops ops;
395 * dpu_hw_pipe - convert base object dpu_hw_base to container
396 * @hw: Pointer to base hardware block
397 * return: Pointer to hardware block container
399 static inline struct dpu_hw_pipe *to_dpu_hw_pipe(struct dpu_hw_blk *hw)
401 return container_of(hw, struct dpu_hw_pipe, base);
405 * dpu_hw_sspp_init - initializes the sspp hw driver object.
406 * Should be called once before accessing every pipe.
407 * @idx: Pipe index for which driver object is required
408 * @addr: Mapped register io address of MDP
409 * @catalog : Pointer to mdss catalog data
410 * @is_virtual_pipe: is this pipe virtual pipe
412 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
413 void __iomem *addr, struct dpu_mdss_cfg *catalog,
414 bool is_virtual_pipe);
417 * dpu_hw_sspp_destroy(): Destroys SSPP driver context
418 * should be called during Hw pipe cleanup.
419 * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
421 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
423 #endif /*_DPU_HW_SSPP_H */