drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

   1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
  13
  14 #include "msm_drv.h"
  15 #include "dpu_kms.h"
  16 #include "dpu_hw_mdss.h"
  17 #include "dpu_hw_util.h"
  18
  19 /* using a file static variables for debugfs access */
  20 static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE;
  21
  22 /* DPU_SCALER_QSEED3 */
  23 #define QSEED3_HW_VERSION                  0x00
  24 #define QSEED3_OP_MODE                     0x04
  25 #define QSEED3_RGB2Y_COEFF                 0x08
  26 #define QSEED3_PHASE_INIT                  0x0C
  27 #define QSEED3_PHASE_STEP_Y_H              0x10
  28 #define QSEED3_PHASE_STEP_Y_V              0x14
  29 #define QSEED3_PHASE_STEP_UV_H             0x18
  30 #define QSEED3_PHASE_STEP_UV_V             0x1C
  31 #define QSEED3_PRELOAD                     0x20
  32 #define QSEED3_DE_SHARPEN                  0x24
  33 #define QSEED3_DE_SHARPEN_CTL              0x28
  34 #define QSEED3_DE_SHAPE_CTL                0x2C
  35 #define QSEED3_DE_THRESHOLD                0x30
  36 #define QSEED3_DE_ADJUST_DATA_0            0x34
  37 #define QSEED3_DE_ADJUST_DATA_1            0x38
  38 #define QSEED3_DE_ADJUST_DATA_2            0x3C
  39 #define QSEED3_SRC_SIZE_Y_RGB_A            0x40
  40 #define QSEED3_SRC_SIZE_UV                 0x44
  41 #define QSEED3_DST_SIZE                    0x48
  42 #define QSEED3_COEF_LUT_CTRL               0x4C
  43 #define QSEED3_COEF_LUT_SWAP_BIT           0
  44 #define QSEED3_COEF_LUT_DIR_BIT            1
  45 #define QSEED3_COEF_LUT_Y_CIR_BIT          2
  46 #define QSEED3_COEF_LUT_UV_CIR_BIT         3
  47 #define QSEED3_COEF_LUT_Y_SEP_BIT          4
  48 #define QSEED3_COEF_LUT_UV_SEP_BIT         5
  49 #define QSEED3_BUFFER_CTRL                 0x50
  50 #define QSEED3_CLK_CTRL0                   0x54
  51 #define QSEED3_CLK_CTRL1                   0x58
  52 #define QSEED3_CLK_STATUS                  0x5C
  53 #define QSEED3_MISR_CTRL                   0x70
  54 #define QSEED3_MISR_SIGNATURE_0            0x74
  55 #define QSEED3_MISR_SIGNATURE_1            0x78
  56 #define QSEED3_PHASE_INIT_Y_H              0x90
  57 #define QSEED3_PHASE_INIT_Y_V              0x94
  58 #define QSEED3_PHASE_INIT_UV_H             0x98
  59 #define QSEED3_PHASE_INIT_UV_V             0x9C
  60 #define QSEED3_COEF_LUT                    0x100
  61 #define QSEED3_FILTERS                     5
  62 #define QSEED3_LUT_REGIONS                 4
  63 #define QSEED3_CIRCULAR_LUTS               9
  64 #define QSEED3_SEPARABLE_LUTS              10
  65 #define QSEED3_LUT_SIZE                    60
  66 #define QSEED3_ENABLE                      2
  67 #define QSEED3_DIR_LUT_SIZE                (200 * sizeof(u32))
  68 #define QSEED3_CIR_LUT_SIZE \
  69         (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
  70 #define QSEED3_SEP_LUT_SIZE \
  71         (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
  72
  73 void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
  74                 u32 reg_off,
  75                 u32 val,
  76                 const char *name)
  77 {
  78         /* don't need to mutex protect this */
  79         if (c->log_mask & dpu_hw_util_log_mask)
  80                 DPU_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n",
  81                                 name, c->blk_off + reg_off, val);
  82         writel_relaxed(val, c->base_off + c->blk_off + reg_off);
  83 }
  84
  85 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off)
  86 {
  87         return readl_relaxed(c->base_off + c->blk_off + reg_off);
  88 }
  89
  90 u32 *dpu_hw_util_get_log_mask_ptr(void)
  91 {
  92         return &dpu_hw_util_log_mask;
  93 }
  94
  95 static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c,
  96                 struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset)
  97 {
  98         int i, j, filter;
  99         int config_lut = 0x0;
 100         unsigned long lut_flags;
 101         u32 lut_addr, lut_offset, lut_len;
 102         u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
 103         static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
 104                 {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
 105                 {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
 106                 {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
 107                 {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
 108                 {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
 109         };
 110
 111         lut_flags = (unsigned long) scaler3_cfg->lut_flag;
 112         if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
 113                 (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
 114                 lut[0] = scaler3_cfg->dir_lut;
 115                 config_lut = 1;
 116         }
 117         if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
 118                 (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
 119                 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
 120                 lut[1] = scaler3_cfg->cir_lut +
 121                         scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
 122                 config_lut = 1;
 123         }
 124         if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
 125                 (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
 126                 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
 127                 lut[2] = scaler3_cfg->cir_lut +
 128                         scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
 129                 config_lut = 1;
 130         }
 131         if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
 132                 (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
 133                 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
 134                 lut[3] = scaler3_cfg->sep_lut +
 135                         scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
 136                 config_lut = 1;
 137         }
 138         if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
 139                 (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
 140                 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
 141                 lut[4] = scaler3_cfg->sep_lut +
 142                         scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
 143                 config_lut = 1;
 144         }
 145
 146         if (config_lut) {
 147                 for (filter = 0; filter < QSEED3_FILTERS; filter++) {
 148                         if (!lut[filter])
 149                                 continue;
 150                         lut_offset = 0;
 151                         for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
 152                                 lut_addr = QSEED3_COEF_LUT + offset
 153                                         + off_tbl[filter][i][1];
 154                                 lut_len = off_tbl[filter][i][0] << 2;
 155                                 for (j = 0; j < lut_len; j++) {
 156                                         DPU_REG_WRITE(c,
 157                                                 lut_addr,
 158                                                 (lut[filter])[lut_offset++]);
 159                                         lut_addr += 4;
 160                                 }
 161                         }
 162                 }
 163         }
 164
 165         if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
 166                 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));
 167
 168 }
 169
 170 static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c,
 171                 struct dpu_hw_scaler3_de_cfg *de_cfg, u32 offset)
 172 {
 173         u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
 174         u32 adjust_a, adjust_b, adjust_c;
 175
 176         if (!de_cfg->enable)
 177                 return;
 178
 179         sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
 180                 ((de_cfg->sharpen_level2 & 0x1FF) << 16);
 181
 182         sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
 183                 ((de_cfg->prec_shift & 0x7) << 13) |
 184                 ((de_cfg->clip & 0x7) << 16);
 185
 186         shape_ctl = (de_cfg->thr_quiet & 0xFF) |
 187                 ((de_cfg->thr_dieout & 0x3FF) << 16);
 188
 189         de_thr = (de_cfg->thr_low & 0x3FF) |
 190                 ((de_cfg->thr_high & 0x3FF) << 16);
 191
 192         adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
 193                 ((de_cfg->adjust_a[1] & 0x3FF) << 10) |
 194                 ((de_cfg->adjust_a[2] & 0x3FF) << 20);
 195
 196         adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
 197                 ((de_cfg->adjust_b[1] & 0x3FF) << 10) |
 198                 ((de_cfg->adjust_b[2] & 0x3FF) << 20);
 199
 200         adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
 201                 ((de_cfg->adjust_c[1] & 0x3FF) << 10) |
 202                 ((de_cfg->adjust_c[2] & 0x3FF) << 20);
 203
 204         DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl);
 205         DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl);
 206         DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl);
 207         DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr);
 208         DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a);
 209         DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b);
 210         DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c);
 211
 212 }
 213
 214 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
 215                 struct dpu_hw_scaler3_cfg *scaler3_cfg,
 216                 u32 scaler_offset, u32 scaler_version,
 217                 const struct dpu_format *format)
 218 {
 219         u32 op_mode = 0;
 220         u32 phase_init, preload, src_y_rgb, src_uv, dst;
 221
 222         if (!scaler3_cfg->enable)
 223                 goto end;
 224
 225         op_mode |= BIT(0);
 226         op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
 227
 228         if (format && DPU_FORMAT_IS_YUV(format)) {
 229                 op_mode |= BIT(12);
 230                 op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
 231         }
 232
 233         op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
 234         op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
 235
 236         preload =
 237                 ((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
 238                 ((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
 239                 ((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
 240                 ((scaler3_cfg->preload_y[1] & 0x7F) << 24);
 241
 242         src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
 243                 ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
 244
 245         src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
 246                 ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
 247
 248         dst = (scaler3_cfg->dst_width & 0x1FFFF) |
 249                 ((scaler3_cfg->dst_height & 0x1FFFF) << 16);
 250
 251         if (scaler3_cfg->de.enable) {
 252                 _dpu_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset);
 253                 op_mode |= BIT(8);
 254         }
 255
 256         if (scaler3_cfg->lut_flag)
 257                 _dpu_hw_setup_scaler3_lut(c, scaler3_cfg,
 258                                                                 scaler_offset);
 259
 260         if (scaler_version == 0x1002) {
 261                 phase_init =
 262                         ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
 263                         ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
 264                         ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
 265                         ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
 266                 DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init);
 267         } else {
 268                 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset,
 269                         scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
 270                 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset,
 271                         scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
 272                 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset,
 273                         scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
 274                 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset,
 275                         scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
 276         }
 277
 278         DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset,
 279                 scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
 280
 281         DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset,
 282                 scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
 283
 284         DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset,
 285                 scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
 286
 287         DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset,
 288                 scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
 289
 290         DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload);
 291
 292         DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb);
 293
 294         DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv);
 295
 296         DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
 297
 298 end:
 299         if (format && !DPU_FORMAT_IS_DX(format))
 300                 op_mode |= BIT(14);
 301
 302         if (format && format->alpha_enable) {
 303                 op_mode |= BIT(10);
 304                 if (scaler_version == 0x1002)
 305                         op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
 306                 else
 307                         op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
 308         }
 309
 310         DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);
 311 }
 312
 313 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
 314                         u32 scaler_offset)
 315 {
 316         return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);
 317 }
 318
 319 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
 320                 u32 csc_reg_off,
 321                 struct dpu_csc_cfg *data, bool csc10)
 322 {
 323         static const u32 matrix_shift = 7;
 324         u32 clamp_shift = csc10 ? 16 : 8;
 325         u32 val;
 326
 327         /* matrix coeff - convert S15.16 to S4.9 */
 328         val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) |
 329                 (((data->csc_mv[1] >> matrix_shift) & 0x1FFF) << 16);
 330         DPU_REG_WRITE(c, csc_reg_off, val);
 331         val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) |
 332                 (((data->csc_mv[3] >> matrix_shift) & 0x1FFF) << 16);
 333         DPU_REG_WRITE(c, csc_reg_off + 0x4, val);
 334         val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) |
 335                 (((data->csc_mv[5] >> matrix_shift) & 0x1FFF) << 16);
 336         DPU_REG_WRITE(c, csc_reg_off + 0x8, val);
 337         val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) |
 338                 (((data->csc_mv[7] >> matrix_shift) & 0x1FFF) << 16);
 339         DPU_REG_WRITE(c, csc_reg_off + 0xc, val);
 340         val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF;
 341         DPU_REG_WRITE(c, csc_reg_off + 0x10, val);
 342
 343         /* Pre clamp */
 344         val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1];
 345         DPU_REG_WRITE(c, csc_reg_off + 0x14, val);
 346         val = (data->csc_pre_lv[2] << clamp_shift) | data->csc_pre_lv[3];
 347         DPU_REG_WRITE(c, csc_reg_off + 0x18, val);
 348         val = (data->csc_pre_lv[4] << clamp_shift) | data->csc_pre_lv[5];
 349         DPU_REG_WRITE(c, csc_reg_off + 0x1c, val);
 350
 351         /* Post clamp */
 352         val = (data->csc_post_lv[0] << clamp_shift) | data->csc_post_lv[1];
 353         DPU_REG_WRITE(c, csc_reg_off + 0x20, val);
 354         val = (data->csc_post_lv[2] << clamp_shift) | data->csc_post_lv[3];
 355         DPU_REG_WRITE(c, csc_reg_off + 0x24, val);
 356         val = (data->csc_post_lv[4] << clamp_shift) | data->csc_post_lv[5];
 357         DPU_REG_WRITE(c, csc_reg_off + 0x28, val);
 358
 359         /* Pre-Bias */
 360         DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]);
 361         DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]);
 362         DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]);
 363
 364         /* Post-Bias */
 365         DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]);
 366         DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
 367         DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
 368 }