drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

   1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #ifndef _DPU_HWIO_H
  14 #define _DPU_HWIO_H
  15
  16 #include "dpu_hw_util.h"
  17
  18 /**
  19  * MDP TOP block Register and bit fields and defines
  20  */
  21 #define DISP_INTF_SEL                   0x004
  22 #define INTR_EN                         0x010
  23 #define INTR_STATUS                     0x014
  24 #define INTR_CLEAR                      0x018
  25 #define INTR2_EN                        0x008
  26 #define INTR2_STATUS                    0x00c
  27 #define INTR2_CLEAR                     0x02c
  28 #define HIST_INTR_EN                    0x01c
  29 #define HIST_INTR_STATUS                0x020
  30 #define HIST_INTR_CLEAR                 0x024
  31 #define INTF_INTR_EN                    0x1C0
  32 #define INTF_INTR_STATUS                0x1C4
  33 #define INTF_INTR_CLEAR                 0x1C8
  34 #define SPLIT_DISPLAY_EN                0x2F4
  35 #define SPLIT_DISPLAY_UPPER_PIPE_CTRL   0x2F8
  36 #define DSPP_IGC_COLOR0_RAM_LUTN        0x300
  37 #define DSPP_IGC_COLOR1_RAM_LUTN        0x304
  38 #define DSPP_IGC_COLOR2_RAM_LUTN        0x308
  39 #define HW_EVENTS_CTL                   0x37C
  40 #define CLK_CTRL3                       0x3A8
  41 #define CLK_STATUS3                     0x3AC
  42 #define CLK_CTRL4                       0x3B0
  43 #define CLK_STATUS4                     0x3B4
  44 #define CLK_CTRL5                       0x3B8
  45 #define CLK_STATUS5                     0x3BC
  46 #define CLK_CTRL7                       0x3D0
  47 #define CLK_STATUS7                     0x3D4
  48 #define SPLIT_DISPLAY_LOWER_PIPE_CTRL   0x3F0
  49 #define SPLIT_DISPLAY_TE_LINE_INTERVAL  0x3F4
  50 #define INTF_SW_RESET_MASK              0x3FC
  51 #define HDMI_DP_CORE_SELECT             0x408
  52 #define MDP_OUT_CTL_0                   0x410
  53 #define MDP_VSYNC_SEL                   0x414
  54 #define DCE_SEL                         0x450
  55
  56 #endif /*_DPU_HWIO_H */