2 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/sort.h>
20 #include <drm/drm_mode.h>
21 #include <drm/drm_crtc.h>
22 #include <drm/drm_crtc_helper.h>
23 #include <drm/drm_flip_work.h>
27 #define CURSOR_WIDTH 64
28 #define CURSOR_HEIGHT 64
35 spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */
37 /* if there is a pending flip, these will be non-null: */
38 struct drm_pending_vblank_event *event;
40 /* Bits have been flushed at the last commit,
41 * used to decide if a vsync has happened since last commit.
45 #define PENDING_CURSOR 0x1
46 #define PENDING_FLIP 0x2
49 /* for unref'ing cursor bo's after scanout completes: */
50 struct drm_flip_work unref_cursor_work;
52 struct mdp_irq vblank;
54 struct mdp_irq pp_done;
56 struct completion pp_completion;
58 bool lm_cursor_enabled;
61 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
64 /* current cursor being scanned out: */
65 struct drm_gem_object *scanout_bo;
67 uint32_t width, height;
71 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
73 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc);
75 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
77 struct msm_drm_private *priv = crtc->dev->dev_private;
78 return to_mdp5_kms(to_mdp_kms(priv->kms));
81 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
83 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
85 atomic_or(pending, &mdp5_crtc->pending);
86 mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
89 static void request_pp_done_pending(struct drm_crtc *crtc)
91 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
92 reinit_completion(&mdp5_crtc->pp_completion);
95 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
97 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
98 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
99 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
100 bool start = !mdp5_cstate->defer_start;
102 mdp5_cstate->defer_start = false;
104 DBG("%s: flush=%08x", crtc->name, flush_mask);
106 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
110 * flush updates, to make sure hw is updated to new scanout fb,
111 * so that we can safely queue unref to current fb (ie. next
112 * vblank we know hw is done w/ previous scanout_fb).
114 static u32 crtc_flush_all(struct drm_crtc *crtc)
116 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
117 struct mdp5_hw_mixer *mixer, *r_mixer;
118 struct drm_plane *plane;
119 uint32_t flush_mask = 0;
121 /* this should not happen: */
122 if (WARN_ON(!mdp5_cstate->ctl))
125 drm_atomic_crtc_for_each_plane(plane, crtc) {
126 if (!plane->state->visible)
128 flush_mask |= mdp5_plane_get_flush(plane);
131 mixer = mdp5_cstate->pipeline.mixer;
132 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
134 r_mixer = mdp5_cstate->pipeline.r_mixer;
136 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
138 return crtc_flush(crtc, flush_mask);
141 /* if file!=NULL, this is preclose potential cancel-flip path */
142 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
144 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
145 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
146 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
147 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
148 struct drm_device *dev = crtc->dev;
149 struct drm_pending_vblank_event *event;
152 spin_lock_irqsave(&dev->event_lock, flags);
153 event = mdp5_crtc->event;
155 mdp5_crtc->event = NULL;
156 DBG("%s: send event: %p", crtc->name, event);
157 drm_crtc_send_vblank_event(crtc, event);
159 spin_unlock_irqrestore(&dev->event_lock, flags);
161 if (ctl && !crtc->state->enable) {
162 /* set STAGE_UNUSED for all layers */
163 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
164 /* XXX: What to do here? */
165 /* mdp5_crtc->ctl = NULL; */
169 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
171 struct mdp5_crtc *mdp5_crtc =
172 container_of(work, struct mdp5_crtc, unref_cursor_work);
173 struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
174 struct msm_kms *kms = &mdp5_kms->base.base;
176 msm_gem_put_iova(val, kms->aspace);
177 drm_gem_object_put_unlocked(val);
180 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
182 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
184 drm_crtc_cleanup(crtc);
185 drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
190 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)
193 case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA;
194 case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA;
195 case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA;
196 case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA;
197 case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA;
198 case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA;
199 case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA;
206 * left/right pipe offsets for the stage array used in blend_setup()
212 * blend_setup() - blend all the planes of a CRTC
214 * If no base layer is available, border will be enabled as the base layer.
215 * Otherwise all layers will be blended based on their stage calculated
216 * in mdp5_crtc_atomic_check.
218 static void blend_setup(struct drm_crtc *crtc)
220 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
221 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
222 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
223 struct mdp5_kms *mdp5_kms = get_kms(crtc);
224 struct drm_plane *plane;
225 const struct mdp5_cfg_hw *hw_cfg;
226 struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
227 const struct mdp_format *format;
228 struct mdp5_hw_mixer *mixer = pipeline->mixer;
229 uint32_t lm = mixer->lm;
230 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
231 uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
232 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
233 uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
235 enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
236 enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
237 int i, plane_cnt = 0;
238 bool bg_alpha_enabled = false;
239 u32 mixer_op_mode = 0;
241 #define blender(stage) ((stage) - STAGE0)
243 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
245 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
247 /* ctl could be released already when we are shutting down: */
248 /* XXX: Can this happen now? */
252 /* Collect all plane information */
253 drm_atomic_crtc_for_each_plane(plane, crtc) {
254 enum mdp5_pipe right_pipe;
256 if (!plane->state->visible)
259 pstate = to_mdp5_plane_state(plane->state);
260 pstates[pstate->stage] = pstate;
261 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
263 * if we have a right mixer, stage the same pipe as we
264 * have on the left mixer
267 r_stage[pstate->stage][PIPE_LEFT] =
268 mdp5_plane_pipe(plane);
270 * if we have a right pipe (i.e, the plane comprises of 2
271 * hwpipes, then stage the right pipe on the right side of both
274 right_pipe = mdp5_plane_right_pipe(plane);
276 stage[pstate->stage][PIPE_RIGHT] = right_pipe;
277 r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
283 if (!pstates[STAGE_BASE]) {
284 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
285 DBG("Border Color is enabled");
286 } else if (plane_cnt) {
287 format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
289 if (format->alpha_enable)
290 bg_alpha_enabled = true;
293 /* The reset for blending */
294 for (i = STAGE0; i <= STAGE_MAX; i++) {
298 format = to_mdp_format(
299 msm_framebuffer_format(pstates[i]->base.fb));
300 plane = pstates[i]->base.plane;
301 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
302 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
303 fg_alpha = pstates[i]->alpha;
304 bg_alpha = 0xFF - pstates[i]->alpha;
306 if (!format->alpha_enable && bg_alpha_enabled)
309 mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
311 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
313 if (format->alpha_enable && pstates[i]->premultiplied) {
314 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
315 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
316 if (fg_alpha != 0xff) {
319 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
320 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
322 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
324 } else if (format->alpha_enable) {
325 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
326 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
327 if (fg_alpha != 0xff) {
330 MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
331 MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
332 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
333 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
335 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
339 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
340 blender(i)), blend_op);
341 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
342 blender(i)), fg_alpha);
343 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
344 blender(i)), bg_alpha);
346 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
347 blender(i)), blend_op);
348 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
349 blender(i)), fg_alpha);
350 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
351 blender(i)), bg_alpha);
355 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
356 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
357 val | mixer_op_mode);
359 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
360 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
361 val | mixer_op_mode);
364 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
367 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
370 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
372 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
373 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
374 struct mdp5_kms *mdp5_kms = get_kms(crtc);
375 struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
376 struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
377 uint32_t lm = mixer->lm;
378 u32 mixer_width, val;
380 struct drm_display_mode *mode;
382 if (WARN_ON(!crtc->state))
385 mode = &crtc->state->adjusted_mode;
387 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
388 crtc->name, mode->base.id, mode->name,
389 mode->vrefresh, mode->clock,
390 mode->hdisplay, mode->hsync_start,
391 mode->hsync_end, mode->htotal,
392 mode->vdisplay, mode->vsync_start,
393 mode->vsync_end, mode->vtotal,
394 mode->type, mode->flags);
396 mixer_width = mode->hdisplay;
400 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
401 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
402 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
403 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
405 /* Assign mixer to LEFT side in source split mode */
406 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
407 val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
408 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
411 u32 r_lm = r_mixer->lm;
413 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
414 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
415 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
417 /* Assign mixer to RIGHT side in source split mode */
418 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
419 val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
420 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
423 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
426 static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
427 struct drm_crtc_state *old_state)
429 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
430 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
431 struct mdp5_kms *mdp5_kms = get_kms(crtc);
432 struct device *dev = &mdp5_kms->pdev->dev;
435 DBG("%s", crtc->name);
437 if (WARN_ON(!mdp5_crtc->enabled))
440 /* Disable/save vblank irq handling before power is disabled */
441 drm_crtc_vblank_off(crtc);
443 if (mdp5_cstate->cmd_mode)
444 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
446 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
447 pm_runtime_put_sync(dev);
449 if (crtc->state->event && !crtc->state->active) {
450 WARN_ON(mdp5_crtc->event);
451 spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);
452 drm_crtc_send_vblank_event(crtc, crtc->state->event);
453 crtc->state->event = NULL;
454 spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);
457 mdp5_crtc->enabled = false;
460 static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
461 struct drm_crtc_state *old_state)
463 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
464 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
465 struct mdp5_kms *mdp5_kms = get_kms(crtc);
466 struct device *dev = &mdp5_kms->pdev->dev;
468 DBG("%s", crtc->name);
470 if (WARN_ON(mdp5_crtc->enabled))
473 pm_runtime_get_sync(dev);
475 if (mdp5_crtc->lm_cursor_enabled) {
477 * Restore LM cursor state, as it might have been lost
480 if (mdp5_crtc->cursor.iova) {
483 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
484 mdp5_crtc_restore_cursor(crtc);
485 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
487 mdp5_ctl_set_cursor(mdp5_cstate->ctl,
488 &mdp5_cstate->pipeline, 0, true);
490 mdp5_ctl_set_cursor(mdp5_cstate->ctl,
491 &mdp5_cstate->pipeline, 0, false);
495 /* Restore vblank irq handling after power is enabled */
496 drm_crtc_vblank_on(crtc);
498 mdp5_crtc_mode_set_nofb(crtc);
500 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
502 if (mdp5_cstate->cmd_mode)
503 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
505 mdp5_crtc->enabled = true;
508 int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
509 struct drm_crtc_state *new_crtc_state,
510 bool need_right_mixer)
512 struct mdp5_crtc_state *mdp5_cstate =
513 to_mdp5_crtc_state(new_crtc_state);
514 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
515 struct mdp5_interface *intf;
516 bool new_mixer = false;
518 new_mixer = !pipeline->mixer;
520 if ((need_right_mixer && !pipeline->r_mixer) ||
521 (!need_right_mixer && pipeline->r_mixer))
525 struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
526 struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer;
530 caps = MDP_LM_CAP_DISPLAY;
531 if (need_right_mixer)
532 caps |= MDP_LM_CAP_PAIR;
534 ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps,
535 &pipeline->mixer, need_right_mixer ?
536 &pipeline->r_mixer : NULL);
540 ret = mdp5_mixer_release(new_crtc_state->state, old_mixer);
545 ret = mdp5_mixer_release(new_crtc_state->state, old_r_mixer);
549 if (!need_right_mixer)
550 pipeline->r_mixer = NULL;
555 * these should have been already set up in the encoder's atomic
556 * check (called by drm_atomic_helper_check_modeset)
558 intf = pipeline->intf;
560 mdp5_cstate->err_irqmask = intf2err(intf->num);
561 mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
563 if ((intf->type == INTF_DSI) &&
564 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
565 mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
566 mdp5_cstate->cmd_mode = true;
568 mdp5_cstate->pp_done_irqmask = 0;
569 mdp5_cstate->cmd_mode = false;
576 struct drm_plane *plane;
577 struct mdp5_plane_state *state;
580 static int pstate_cmp(const void *a, const void *b)
582 struct plane_state *pa = (struct plane_state *)a;
583 struct plane_state *pb = (struct plane_state *)b;
584 return pa->state->zpos - pb->state->zpos;
587 /* is there a helper for this? */
588 static bool is_fullscreen(struct drm_crtc_state *cstate,
589 struct drm_plane_state *pstate)
591 return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
592 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
593 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
596 static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc,
597 struct drm_crtc_state *new_crtc_state,
598 struct drm_plane_state *bpstate)
600 struct mdp5_crtc_state *mdp5_cstate =
601 to_mdp5_crtc_state(new_crtc_state);
604 * if we're in source split mode, it's mandatory to have
605 * border out on the base stage
607 if (mdp5_cstate->pipeline.r_mixer)
610 /* if the bottom-most layer is not fullscreen, we need to use
611 * it for solid-color:
613 if (!is_fullscreen(new_crtc_state, bpstate))
619 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
620 struct drm_crtc_state *state)
622 struct mdp5_kms *mdp5_kms = get_kms(crtc);
623 struct drm_plane *plane;
624 struct drm_device *dev = crtc->dev;
625 struct plane_state pstates[STAGE_MAX + 1];
626 const struct mdp5_cfg_hw *hw_cfg;
627 const struct drm_plane_state *pstate;
628 const struct drm_display_mode *mode = &state->adjusted_mode;
629 bool cursor_plane = false;
630 bool need_right_mixer = false;
633 enum mdp_mixer_stage_id start;
635 DBG("%s: check", crtc->name);
637 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
638 if (!pstate->visible)
641 pstates[cnt].plane = plane;
642 pstates[cnt].state = to_mdp5_plane_state(pstate);
645 * if any plane on this crtc uses 2 hwpipes, then we need
646 * the crtc to have a right hwmixer.
648 if (pstates[cnt].state->r_hwpipe)
649 need_right_mixer = true;
652 if (plane->type == DRM_PLANE_TYPE_CURSOR)
656 /* bail out early if there aren't any planes */
660 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
663 * we need a right hwmixer if the mode's width is greater than a single
666 if (mode->hdisplay > hw_cfg->lm.max_width)
667 need_right_mixer = true;
669 ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer);
671 dev_err(dev->dev, "couldn't assign mixers %d\n", ret);
675 /* assign a stage based on sorted zpos property */
676 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
678 /* trigger a warning if cursor isn't the highest zorder */
679 WARN_ON(cursor_plane &&
680 (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
682 start = get_start_stage(crtc, state, &pstates[0].state->base);
684 /* verify that there are not too many planes attached to crtc
685 * and that we don't have conflicting mixer stages:
687 if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
688 dev_err(dev->dev, "too many planes! cnt=%d, start stage=%d\n",
693 for (i = 0; i < cnt; i++) {
694 if (cursor_plane && (i == (cnt - 1)))
695 pstates[i].state->stage = hw_cfg->lm.nb_stages;
697 pstates[i].state->stage = start + i;
698 DBG("%s: assign pipe %s on stage=%d", crtc->name,
699 pstates[i].plane->name,
700 pstates[i].state->stage);
706 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
707 struct drm_crtc_state *old_crtc_state)
709 DBG("%s: begin", crtc->name);
712 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
713 struct drm_crtc_state *old_crtc_state)
715 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
716 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
717 struct drm_device *dev = crtc->dev;
720 DBG("%s: event: %p", crtc->name, crtc->state->event);
722 WARN_ON(mdp5_crtc->event);
724 spin_lock_irqsave(&dev->event_lock, flags);
725 mdp5_crtc->event = crtc->state->event;
726 crtc->state->event = NULL;
727 spin_unlock_irqrestore(&dev->event_lock, flags);
730 * If no CTL has been allocated in mdp5_crtc_atomic_check(),
731 * it means we are trying to flush a CRTC whose state is disabled:
732 * nothing else needs to be done.
734 /* XXX: Can this happen now ? */
735 if (unlikely(!mdp5_cstate->ctl))
740 /* PP_DONE irq is only used by command mode for now.
741 * It is better to request pending before FLUSH and START trigger
742 * to make sure no pp_done irq missed.
743 * This is safe because no pp_done will happen before SW trigger
746 if (mdp5_cstate->cmd_mode)
747 request_pp_done_pending(crtc);
749 mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
751 /* XXX are we leaking out state here? */
752 mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
753 mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
754 mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
756 request_pending(crtc, PENDING_FLIP);
759 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
761 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
762 uint32_t xres = crtc->mode.hdisplay;
763 uint32_t yres = crtc->mode.vdisplay;
766 * Cursor Region Of Interest (ROI) is a plane read from cursor
767 * buffer to render. The ROI region is determined by the visibility of
768 * the cursor point. In the default Cursor image the cursor point will
769 * be at the top left of the cursor image.
772 * If the cursor point reaches the right (xres - x < cursor.width) or
773 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
774 * width and ROI height need to be evaluated to crop the cursor image
776 * (xres-x) will be new cursor width when x > (xres - cursor.width)
777 * (yres-y) will be new cursor height when y > (yres - cursor.height)
780 * We get negative x and/or y coordinates.
781 * (cursor.width - abs(x)) will be new cursor width when x < 0
782 * (cursor.height - abs(y)) will be new cursor width when y < 0
784 if (mdp5_crtc->cursor.x >= 0)
785 *roi_w = min(mdp5_crtc->cursor.width, xres -
786 mdp5_crtc->cursor.x);
788 *roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x);
789 if (mdp5_crtc->cursor.y >= 0)
790 *roi_h = min(mdp5_crtc->cursor.height, yres -
791 mdp5_crtc->cursor.y);
793 *roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y);
796 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
798 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
799 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
800 struct mdp5_kms *mdp5_kms = get_kms(crtc);
801 const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
802 uint32_t blendcfg, stride;
803 uint32_t x, y, src_x, src_y, width, height;
804 uint32_t roi_w, roi_h;
807 assert_spin_locked(&mdp5_crtc->cursor.lock);
809 lm = mdp5_cstate->pipeline.mixer->lm;
811 x = mdp5_crtc->cursor.x;
812 y = mdp5_crtc->cursor.y;
813 width = mdp5_crtc->cursor.width;
814 height = mdp5_crtc->cursor.height;
816 stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0);
818 get_roi(crtc, &roi_w, &roi_h);
820 /* If cusror buffer overlaps due to rotation on the
821 * upper or left screen border the pixel offset inside
822 * the cursor buffer of the ROI is the positive overlap
825 if (mdp5_crtc->cursor.x < 0) {
826 src_x = abs(mdp5_crtc->cursor.x);
831 if (mdp5_crtc->cursor.y < 0) {
832 src_y = abs(mdp5_crtc->cursor.y);
837 DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d",
838 crtc->name, x, y, roi_w, roi_h, src_x, src_y);
840 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
841 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
842 MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
843 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
844 MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
845 MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
846 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
847 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
848 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
849 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
850 MDP5_LM_CURSOR_START_XY_Y_START(y) |
851 MDP5_LM_CURSOR_START_XY_X_START(x));
852 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
853 MDP5_LM_CURSOR_XY_SRC_Y(src_y) |
854 MDP5_LM_CURSOR_XY_SRC_X(src_x));
855 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
856 mdp5_crtc->cursor.iova);
858 blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
859 blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
860 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
863 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
864 struct drm_file *file, uint32_t handle,
865 uint32_t width, uint32_t height)
867 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
868 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
869 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
870 struct drm_device *dev = crtc->dev;
871 struct mdp5_kms *mdp5_kms = get_kms(crtc);
872 struct platform_device *pdev = mdp5_kms->pdev;
873 struct msm_kms *kms = &mdp5_kms->base.base;
874 struct drm_gem_object *cursor_bo, *old_bo = NULL;
875 struct mdp5_ctl *ctl;
877 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
878 bool cursor_enable = true;
881 if (!mdp5_crtc->lm_cursor_enabled) {
883 "cursor_set is deprecated with cursor planes\n");
887 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
888 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
892 ctl = mdp5_cstate->ctl;
896 /* don't support LM cursors when we we have source split enabled */
897 if (mdp5_cstate->pipeline.r_mixer)
902 cursor_enable = false;
903 mdp5_crtc->cursor.iova = 0;
904 pm_runtime_get_sync(&pdev->dev);
908 cursor_bo = drm_gem_object_lookup(file, handle);
912 ret = msm_gem_get_iova(cursor_bo, kms->aspace,
913 &mdp5_crtc->cursor.iova);
915 drm_gem_object_put(cursor_bo);
919 pm_runtime_get_sync(&pdev->dev);
921 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
922 old_bo = mdp5_crtc->cursor.scanout_bo;
924 mdp5_crtc->cursor.scanout_bo = cursor_bo;
925 mdp5_crtc->cursor.width = width;
926 mdp5_crtc->cursor.height = height;
928 mdp5_crtc_restore_cursor(crtc);
930 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
933 ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
935 dev_err(dev->dev, "failed to %sable cursor: %d\n",
936 cursor_enable ? "en" : "dis", ret);
940 crtc_flush(crtc, flush_mask);
943 pm_runtime_put_sync(&pdev->dev);
945 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
946 /* enable vblank to complete cursor work: */
947 request_pending(crtc, PENDING_CURSOR);
952 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
954 struct mdp5_kms *mdp5_kms = get_kms(crtc);
955 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
956 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
957 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
958 struct drm_device *dev = crtc->dev;
963 if (!mdp5_crtc->lm_cursor_enabled) {
965 "cursor_move is deprecated with cursor planes\n");
969 /* don't support LM cursors when we we have source split enabled */
970 if (mdp5_cstate->pipeline.r_mixer)
973 /* In case the CRTC is disabled, just drop the cursor update */
974 if (unlikely(!crtc->state->enable))
977 /* accept negative x/y coordinates up to maximum cursor overlap */
978 mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width);
979 mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height);
981 get_roi(crtc, &roi_w, &roi_h);
983 pm_runtime_get_sync(&mdp5_kms->pdev->dev);
985 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
986 mdp5_crtc_restore_cursor(crtc);
987 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
989 crtc_flush(crtc, flush_mask);
991 pm_runtime_put_sync(&mdp5_kms->pdev->dev);
997 mdp5_crtc_atomic_print_state(struct drm_printer *p,
998 const struct drm_crtc_state *state)
1000 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1001 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
1002 struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
1004 if (WARN_ON(!pipeline))
1007 if (mdp5_cstate->ctl)
1008 drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl));
1010 drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ?
1011 pipeline->mixer->name : "(null)");
1013 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
1014 drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ?
1015 pipeline->r_mixer->name : "(null)");
1017 drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
1020 static void mdp5_crtc_reset(struct drm_crtc *crtc)
1022 struct mdp5_crtc_state *mdp5_cstate;
1025 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1026 kfree(to_mdp5_crtc_state(crtc->state));
1029 mdp5_cstate = kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
1032 mdp5_cstate->base.crtc = crtc;
1033 crtc->state = &mdp5_cstate->base;
1037 static struct drm_crtc_state *
1038 mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
1040 struct mdp5_crtc_state *mdp5_cstate;
1042 if (WARN_ON(!crtc->state))
1045 mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
1046 sizeof(*mdp5_cstate), GFP_KERNEL);
1050 __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
1052 return &mdp5_cstate->base;
1055 static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)
1057 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1059 __drm_atomic_helper_crtc_destroy_state(state);
1064 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
1065 .set_config = drm_atomic_helper_set_config,
1066 .destroy = mdp5_crtc_destroy,
1067 .page_flip = drm_atomic_helper_page_flip,
1068 .reset = mdp5_crtc_reset,
1069 .atomic_duplicate_state = mdp5_crtc_duplicate_state,
1070 .atomic_destroy_state = mdp5_crtc_destroy_state,
1071 .cursor_set = mdp5_crtc_cursor_set,
1072 .cursor_move = mdp5_crtc_cursor_move,
1073 .atomic_print_state = mdp5_crtc_atomic_print_state,
1076 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
1077 .mode_set_nofb = mdp5_crtc_mode_set_nofb,
1078 .atomic_check = mdp5_crtc_atomic_check,
1079 .atomic_begin = mdp5_crtc_atomic_begin,
1080 .atomic_flush = mdp5_crtc_atomic_flush,
1081 .atomic_enable = mdp5_crtc_atomic_enable,
1082 .atomic_disable = mdp5_crtc_atomic_disable,
1085 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
1087 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
1088 struct drm_crtc *crtc = &mdp5_crtc->base;
1089 struct msm_drm_private *priv = crtc->dev->dev_private;
1092 mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
1094 pending = atomic_xchg(&mdp5_crtc->pending, 0);
1096 if (pending & PENDING_FLIP) {
1097 complete_flip(crtc, NULL);
1100 if (pending & PENDING_CURSOR)
1101 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
1104 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
1106 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
1108 DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
1111 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
1113 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
1116 complete(&mdp5_crtc->pp_completion);
1119 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
1121 struct drm_device *dev = crtc->dev;
1122 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1123 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1126 ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1127 msecs_to_jiffies(50));
1129 dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
1130 mdp5_cstate->pipeline.mixer->lm);
1133 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
1135 struct drm_device *dev = crtc->dev;
1136 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1137 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1138 struct mdp5_ctl *ctl = mdp5_cstate->ctl;
1141 /* Should not call this function if crtc is disabled. */
1145 ret = drm_crtc_vblank_get(crtc);
1149 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
1150 ((mdp5_ctl_get_commit_status(ctl) &
1151 mdp5_crtc->flushed_mask) == 0),
1152 msecs_to_jiffies(50));
1154 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
1156 mdp5_crtc->flushed_mask = 0;
1158 drm_crtc_vblank_put(crtc);
1161 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
1163 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1164 return mdp5_crtc->vblank.irqmask;
1167 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
1169 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1170 struct mdp5_kms *mdp5_kms = get_kms(crtc);
1172 /* should this be done elsewhere ? */
1173 mdp_irq_update(&mdp5_kms->base);
1175 mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
1178 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
1180 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1182 return mdp5_cstate->ctl;
1185 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
1187 struct mdp5_crtc_state *mdp5_cstate;
1190 return ERR_PTR(-EINVAL);
1192 mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1194 return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
1195 ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
1198 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
1200 struct mdp5_crtc_state *mdp5_cstate;
1203 return ERR_PTR(-EINVAL);
1205 mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1207 return &mdp5_cstate->pipeline;
1210 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
1212 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1214 if (mdp5_cstate->cmd_mode)
1215 mdp5_crtc_wait_for_pp_done(crtc);
1217 mdp5_crtc_wait_for_flush_done(crtc);
1220 /* initialize crtc */
1221 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
1222 struct drm_plane *plane,
1223 struct drm_plane *cursor_plane, int id)
1225 struct drm_crtc *crtc = NULL;
1226 struct mdp5_crtc *mdp5_crtc;
1228 mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
1230 return ERR_PTR(-ENOMEM);
1232 crtc = &mdp5_crtc->base;
1236 spin_lock_init(&mdp5_crtc->lm_lock);
1237 spin_lock_init(&mdp5_crtc->cursor.lock);
1238 init_completion(&mdp5_crtc->pp_completion);
1240 mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
1241 mdp5_crtc->err.irq = mdp5_crtc_err_irq;
1242 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
1244 mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true;
1246 drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,
1247 &mdp5_crtc_funcs, NULL);
1249 drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
1250 "unref cursor", unref_cursor_worker);
1252 drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);