drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

   1 /*
   2  * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <drm/drm_print.h>
  20 #include "mdp5_kms.h"
  21
  22 struct mdp5_plane {
  23         struct drm_plane base;
  24
  25         uint32_t nformats;
  26         uint32_t formats[32];
  27 };
  28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
  29
  30 static int mdp5_plane_mode_set(struct drm_plane *plane,
  31                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  32                 struct drm_rect *src, struct drm_rect *dest);
  33
  34 static struct mdp5_kms *get_kms(struct drm_plane *plane)
  35 {
  36         struct msm_drm_private *priv = plane->dev->dev_private;
  37         return to_mdp5_kms(to_mdp_kms(priv->kms));
  38 }
  39
  40 static bool plane_enabled(struct drm_plane_state *state)
  41 {
  42         return state->visible;
  43 }
  44
  45 static void mdp5_plane_destroy(struct drm_plane *plane)
  46 {
  47         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
  48
  49         drm_plane_helper_disable(plane, NULL);
  50         drm_plane_cleanup(plane);
  51
  52         kfree(mdp5_plane);
  53 }
  54
  55 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
  56                 struct drm_plane *plane)
  57 {
  58         drm_plane_create_rotation_property(plane,
  59                                            DRM_MODE_ROTATE_0,
  60                                            DRM_MODE_ROTATE_0 |
  61                                            DRM_MODE_ROTATE_180 |
  62                                            DRM_MODE_REFLECT_X |
  63                                            DRM_MODE_REFLECT_Y);
  64 }
  65
  66 /* helper to install properties which are common to planes and crtcs */
  67 static void mdp5_plane_install_properties(struct drm_plane *plane,
  68                 struct drm_mode_object *obj)
  69 {
  70         struct drm_device *dev = plane->dev;
  71         struct msm_drm_private *dev_priv = dev->dev_private;
  72         struct drm_property *prop;
  73
  74 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
  75                 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
  76                 if (!prop) { \
  77                         prop = drm_property_##fnc(dev, 0, #name, \
  78                                 ##__VA_ARGS__); \
  79                         if (!prop) { \
  80                                 dev_warn(dev->dev, \
  81                                         "Create property %s failed\n", \
  82                                         #name); \
  83                                 return; \
  84                         } \
  85                         dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
  86                 } \
  87                 drm_object_attach_property(&plane->base, prop, init_val); \
  88         } while (0)
  89
  90 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
  91                 INSTALL_PROPERTY(name, NAME, init_val, \
  92                                 create_range, min, max)
  93
  94 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
  95                 INSTALL_PROPERTY(name, NAME, init_val, \
  96                                 create_enum, name##_prop_enum_list, \
  97                                 ARRAY_SIZE(name##_prop_enum_list))
  98
  99         INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
 100
 101         mdp5_plane_install_rotation_property(dev, plane);
 102
 103 #undef INSTALL_RANGE_PROPERTY
 104 #undef INSTALL_ENUM_PROPERTY
 105 #undef INSTALL_PROPERTY
 106 }
 107
 108 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
 109                 struct drm_plane_state *state, struct drm_property *property,
 110                 uint64_t val)
 111 {
 112         struct drm_device *dev = plane->dev;
 113         struct mdp5_plane_state *pstate;
 114         struct msm_drm_private *dev_priv = dev->dev_private;
 115         int ret = 0;
 116
 117         pstate = to_mdp5_plane_state(state);
 118
 119 #define SET_PROPERTY(name, NAME, type) do { \
 120                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 121                         pstate->name = (type)val; \
 122                         DBG("Set property %s %d", #name, (type)val); \
 123                         goto done; \
 124                 } \
 125         } while (0)
 126
 127         SET_PROPERTY(zpos, ZPOS, uint8_t);
 128
 129         dev_err(dev->dev, "Invalid property\n");
 130         ret = -EINVAL;
 131 done:
 132         return ret;
 133 #undef SET_PROPERTY
 134 }
 135
 136 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
 137                 const struct drm_plane_state *state,
 138                 struct drm_property *property, uint64_t *val)
 139 {
 140         struct drm_device *dev = plane->dev;
 141         struct mdp5_plane_state *pstate;
 142         struct msm_drm_private *dev_priv = dev->dev_private;
 143         int ret = 0;
 144
 145         pstate = to_mdp5_plane_state(state);
 146
 147 #define GET_PROPERTY(name, NAME, type) do { \
 148                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 149                         *val = pstate->name; \
 150                         DBG("Get property %s %lld", #name, *val); \
 151                         goto done; \
 152                 } \
 153         } while (0)
 154
 155         GET_PROPERTY(zpos, ZPOS, uint8_t);
 156
 157         dev_err(dev->dev, "Invalid property\n");
 158         ret = -EINVAL;
 159 done:
 160         return ret;
 161 #undef SET_PROPERTY
 162 }
 163
 164 static void
 165 mdp5_plane_atomic_print_state(struct drm_printer *p,
 166                 const struct drm_plane_state *state)
 167 {
 168         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 169         struct mdp5_kms *mdp5_kms = get_kms(state->plane);
 170
 171         drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
 172                         pstate->hwpipe->name : "(null)");
 173         if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
 174                 drm_printf(p, "\tright-hwpipe=%s\n",
 175                            pstate->r_hwpipe ? pstate->r_hwpipe->name :
 176                                               "(null)");
 177         drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
 178         drm_printf(p, "\tzpos=%u\n", pstate->zpos);
 179         drm_printf(p, "\talpha=%u\n", pstate->alpha);
 180         drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
 181 }
 182
 183 static void mdp5_plane_reset(struct drm_plane *plane)
 184 {
 185         struct mdp5_plane_state *mdp5_state;
 186
 187         if (plane->state && plane->state->fb)
 188                 drm_framebuffer_unreference(plane->state->fb);
 189
 190         kfree(to_mdp5_plane_state(plane->state));
 191         plane->state = NULL;
 192         mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
 193         if (!mdp5_state)
 194                 return;
 195
 196         /* assign default blend parameters */
 197         mdp5_state->alpha = 255;
 198         mdp5_state->premultiplied = 0;
 199
 200         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 201                 mdp5_state->zpos = STAGE_BASE;
 202         else
 203                 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
 204
 205         mdp5_state->base.plane = plane;
 206
 207         plane->state = &mdp5_state->base;
 208 }
 209
 210 static struct drm_plane_state *
 211 mdp5_plane_duplicate_state(struct drm_plane *plane)
 212 {
 213         struct mdp5_plane_state *mdp5_state;
 214
 215         if (WARN_ON(!plane->state))
 216                 return NULL;
 217
 218         mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 219                         sizeof(*mdp5_state), GFP_KERNEL);
 220         if (!mdp5_state)
 221                 return NULL;
 222
 223         __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
 224
 225         return &mdp5_state->base;
 226 }
 227
 228 static void mdp5_plane_destroy_state(struct drm_plane *plane,
 229                 struct drm_plane_state *state)
 230 {
 231         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 232
 233         if (state->fb)
 234                 drm_framebuffer_unreference(state->fb);
 235
 236         kfree(pstate);
 237 }
 238
 239 static const struct drm_plane_funcs mdp5_plane_funcs = {
 240                 .update_plane = drm_atomic_helper_update_plane,
 241                 .disable_plane = drm_atomic_helper_disable_plane,
 242                 .destroy = mdp5_plane_destroy,
 243                 .atomic_set_property = mdp5_plane_atomic_set_property,
 244                 .atomic_get_property = mdp5_plane_atomic_get_property,
 245                 .reset = mdp5_plane_reset,
 246                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 247                 .atomic_destroy_state = mdp5_plane_destroy_state,
 248                 .atomic_print_state = mdp5_plane_atomic_print_state,
 249 };
 250
 251 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
 252                                   struct drm_plane_state *old_state)
 253 {
 254         struct mdp5_kms *mdp5_kms = get_kms(plane);
 255         struct msm_kms *kms = &mdp5_kms->base.base;
 256         struct drm_framebuffer *fb = old_state->fb;
 257
 258         if (!fb)
 259                 return;
 260
 261         DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
 262         msm_framebuffer_cleanup(fb, kms->aspace);
 263 }
 264
 265 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
 266                                               struct drm_plane_state *state)
 267 {
 268         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 269         struct drm_plane *plane = state->plane;
 270         struct drm_plane_state *old_state = plane->state;
 271         struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
 272         bool new_hwpipe = false;
 273         bool need_right_hwpipe = false;
 274         uint32_t max_width, max_height;
 275         bool out_of_bounds = false;
 276         uint32_t caps = 0;
 277         int min_scale, max_scale;
 278         int ret;
 279
 280         DBG("%s: check (%d -> %d)", plane->name,
 281                         plane_enabled(old_state), plane_enabled(state));
 282
 283         max_width = config->hw->lm.max_width << 16;
 284         max_height = config->hw->lm.max_height << 16;
 285
 286         /* Make sure source dimensions are within bounds. */
 287         if (state->src_h > max_height)
 288                 out_of_bounds = true;
 289
 290         if (state->src_w > max_width) {
 291                 /* If source split is supported, we can go up to 2x
 292                  * the max LM width, but we'd need to stage another
 293                  * hwpipe to the right LM. So, the drm_plane would
 294                  * consist of 2 hwpipes.
 295                  */
 296                 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
 297                     (state->src_w <= 2 * max_width))
 298                         need_right_hwpipe = true;
 299                 else
 300                         out_of_bounds = true;
 301         }
 302
 303         if (out_of_bounds) {
 304                 struct drm_rect src = drm_plane_state_src(state);
 305                 DBG("Invalid source size "DRM_RECT_FP_FMT,
 306                                 DRM_RECT_FP_ARG(&src));
 307                 return -ERANGE;
 308         }
 309
 310         min_scale = FRAC_16_16(1, 8);
 311         max_scale = FRAC_16_16(8, 1);
 312
 313         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 314                                                   min_scale, max_scale,
 315                                                   true, true);
 316         if (ret)
 317                 return ret;
 318
 319         if (plane_enabled(state)) {
 320                 unsigned int rotation;
 321                 const struct mdp_format *format;
 322                 struct mdp5_kms *mdp5_kms = get_kms(plane);
 323                 uint32_t blkcfg = 0;
 324
 325                 format = to_mdp_format(msm_framebuffer_format(state->fb));
 326                 if (MDP_FORMAT_IS_YUV(format))
 327                         caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 328
 329                 if (((state->src_w >> 16) != state->crtc_w) ||
 330                                 ((state->src_h >> 16) != state->crtc_h))
 331                         caps |= MDP_PIPE_CAP_SCALE;
 332
 333                 rotation = drm_rotation_simplify(state->rotation,
 334                                                  DRM_MODE_ROTATE_0 |
 335                                                  DRM_MODE_REFLECT_X |
 336                                                  DRM_MODE_REFLECT_Y);
 337
 338                 if (rotation & DRM_MODE_REFLECT_X)
 339                         caps |= MDP_PIPE_CAP_HFLIP;
 340
 341                 if (rotation & DRM_MODE_REFLECT_Y)
 342                         caps |= MDP_PIPE_CAP_VFLIP;
 343
 344                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 345                         caps |= MDP_PIPE_CAP_CURSOR;
 346
 347                 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
 348                 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
 349                         new_hwpipe = true;
 350
 351                 /*
 352                  * (re)allocte hw pipe if we're either requesting for 2 hw pipes
 353                  * or we're switching from 2 hw pipes to 1 hw pipe because the
 354                  * new src_w can be supported by 1 hw pipe itself.
 355                  */
 356                 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
 357                     (!need_right_hwpipe && mdp5_state->r_hwpipe))
 358                         new_hwpipe = true;
 359
 360                 if (mdp5_kms->smp) {
 361                         const struct mdp_format *format =
 362                                 to_mdp_format(msm_framebuffer_format(state->fb));
 363
 364                         blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
 365                                         state->src_w >> 16, false);
 366
 367                         if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
 368                                 new_hwpipe = true;
 369                 }
 370
 371                 /* (re)assign hwpipe if needed, otherwise keep old one: */
 372                 if (new_hwpipe) {
 373                         /* TODO maybe we want to re-assign hwpipe sometimes
 374                          * in cases when we no-longer need some caps to make
 375                          * it available for other planes?
 376                          */
 377                         struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
 378                         struct mdp5_hw_pipe *old_right_hwpipe =
 379                                                           mdp5_state->r_hwpipe;
 380                         struct mdp5_hw_pipe *new_hwpipe = NULL;
 381                         struct mdp5_hw_pipe *new_right_hwpipe = NULL;
 382
 383                         ret = mdp5_pipe_assign(state->state, plane, caps,
 384                                                blkcfg, &new_hwpipe,
 385                                                need_right_hwpipe ?
 386                                                &new_right_hwpipe : NULL);
 387                         if (ret) {
 388                                 DBG("%s: failed to assign hwpipe(s)!",
 389                                     plane->name);
 390                                 return ret;
 391                         }
 392
 393                         mdp5_state->hwpipe = new_hwpipe;
 394                         if (need_right_hwpipe)
 395                                 mdp5_state->r_hwpipe = new_right_hwpipe;
 396                         else
 397                                 /*
 398                                  * set it to NULL so that the driver knows we
 399                                  * don't have a right hwpipe when committing a
 400                                  * new state
 401                                  */
 402                                 mdp5_state->r_hwpipe = NULL;
 403
 404
 405                         ret = mdp5_pipe_release(state->state, old_hwpipe);
 406                         if (ret)
 407                                 return ret;
 408
 409                         ret = mdp5_pipe_release(state->state, old_right_hwpipe);
 410                         if (ret)
 411                                 return ret;
 412
 413                 }
 414         } else {
 415                 ret = mdp5_pipe_release(state->state, mdp5_state->hwpipe);
 416                 if (ret)
 417                         return ret;
 418
 419                 ret = mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
 420                 if (ret)
 421                         return ret;
 422
 423                 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
 424         }
 425
 426         return 0;
 427 }
 428
 429 static int mdp5_plane_atomic_check(struct drm_plane *plane,
 430                                    struct drm_plane_state *state)
 431 {
 432         struct drm_crtc *crtc;
 433         struct drm_crtc_state *crtc_state;
 434
 435         crtc = state->crtc ? state->crtc : plane->state->crtc;
 436         if (!crtc)
 437                 return 0;
 438
 439         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 440         if (WARN_ON(!crtc_state))
 441                 return -EINVAL;
 442
 443         return mdp5_plane_atomic_check_with_state(crtc_state, state);
 444 }
 445
 446 static void mdp5_plane_atomic_update(struct drm_plane *plane,
 447                                      struct drm_plane_state *old_state)
 448 {
 449         struct drm_plane_state *state = plane->state;
 450
 451         DBG("%s: update", plane->name);
 452
 453         if (plane_enabled(state)) {
 454                 int ret;
 455
 456                 ret = mdp5_plane_mode_set(plane,
 457                                 state->crtc, state->fb,
 458                                 &state->src, &state->dst);
 459                 /* atomic_check should have ensured that this doesn't fail */
 460                 WARN_ON(ret < 0);
 461         }
 462 }
 463
 464 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
 465                                          struct drm_plane_state *state)
 466 {
 467         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 468         struct drm_crtc_state *crtc_state;
 469         int min_scale, max_scale;
 470         int ret;
 471
 472         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 473                                                         state->crtc);
 474         if (WARN_ON(!crtc_state))
 475                 return -EINVAL;
 476
 477         if (!crtc_state->active)
 478                 return -EINVAL;
 479
 480         mdp5_state = to_mdp5_plane_state(state);
 481
 482         /* don't use fast path if we don't have a hwpipe allocated yet */
 483         if (!mdp5_state->hwpipe)
 484                 return -EINVAL;
 485
 486         /* only allow changing of position(crtc x/y or src x/y) in fast path */
 487         if (plane->state->crtc != state->crtc ||
 488             plane->state->src_w != state->src_w ||
 489             plane->state->src_h != state->src_h ||
 490             plane->state->crtc_w != state->crtc_w ||
 491             plane->state->crtc_h != state->crtc_h ||
 492             !plane->state->fb ||
 493             plane->state->fb != state->fb)
 494                 return -EINVAL;
 495
 496         min_scale = FRAC_16_16(1, 8);
 497         max_scale = FRAC_16_16(8, 1);
 498
 499         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 500                                                   min_scale, max_scale,
 501                                                   true, true);
 502         if (ret)
 503                 return ret;
 504
 505         /*
 506          * if the visibility of the plane changes (i.e, if the cursor is
 507          * clipped out completely, we can't take the async path because
 508          * we need to stage/unstage the plane from the Layer Mixer(s). We
 509          * also assign/unassign the hwpipe(s) tied to the plane. We avoid
 510          * taking the fast path for both these reasons.
 511          */
 512         if (state->visible != plane->state->visible)
 513                 return -EINVAL;
 514
 515         return 0;
 516 }
 517
 518 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
 519                                            struct drm_plane_state *new_state)
 520 {
 521         struct drm_framebuffer *old_fb = plane->state->fb;
 522
 523         plane->state->src_x = new_state->src_x;
 524         plane->state->src_y = new_state->src_y;
 525         plane->state->crtc_x = new_state->crtc_x;
 526         plane->state->crtc_y = new_state->crtc_y;
 527
 528         if (plane_enabled(new_state)) {
 529                 struct mdp5_ctl *ctl;
 530                 struct mdp5_pipeline *pipeline =
 531                                         mdp5_crtc_get_pipeline(new_state->crtc);
 532                 int ret;
 533
 534                 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
 535                                 &new_state->src, &new_state->dst);
 536                 WARN_ON(ret < 0);
 537
 538                 ctl = mdp5_crtc_get_ctl(new_state->crtc);
 539
 540                 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
 541         }
 542
 543         *to_mdp5_plane_state(plane->state) =
 544                 *to_mdp5_plane_state(new_state);
 545
 546         new_state->fb = old_fb;
 547 }
 548
 549 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
 550                 .prepare_fb = msm_atomic_prepare_fb,
 551                 .cleanup_fb = mdp5_plane_cleanup_fb,
 552                 .atomic_check = mdp5_plane_atomic_check,
 553                 .atomic_update = mdp5_plane_atomic_update,
 554                 .atomic_async_check = mdp5_plane_atomic_async_check,
 555                 .atomic_async_update = mdp5_plane_atomic_async_update,
 556 };
 557
 558 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
 559                                enum mdp5_pipe pipe,
 560                                struct drm_framebuffer *fb)
 561 {
 562         struct msm_kms *kms = &mdp5_kms->base.base;
 563
 564         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
 565                         MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 566                         MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 567
 568         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
 569                         MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 570                         MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 571
 572         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
 573                         msm_framebuffer_iova(fb, kms->aspace, 0));
 574         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
 575                         msm_framebuffer_iova(fb, kms->aspace, 1));
 576         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
 577                         msm_framebuffer_iova(fb, kms->aspace, 2));
 578         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
 579                         msm_framebuffer_iova(fb, kms->aspace, 3));
 580 }
 581
 582 /* Note: mdp5_plane->pipe_lock must be locked */
 583 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
 584 {
 585         uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
 586                          ~MDP5_PIPE_OP_MODE_CSC_1_EN;
 587
 588         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
 589 }
 590
 591 /* Note: mdp5_plane->pipe_lock must be locked */
 592 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 593                 struct csc_cfg *csc)
 594 {
 595         uint32_t  i, mode = 0; /* RGB, no CSC */
 596         uint32_t *matrix;
 597
 598         if (unlikely(!csc))
 599                 return;
 600
 601         if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
 602                 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
 603         if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
 604                 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
 605         mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
 606         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
 607
 608         matrix = csc->matrix;
 609         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
 610                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
 611                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
 612         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
 613                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
 614                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
 615         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
 616                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
 617                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
 618         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
 619                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
 620                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
 621         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
 622                         MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
 623
 624         for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
 625                 uint32_t *pre_clamp = csc->pre_clamp;
 626                 uint32_t *post_clamp = csc->post_clamp;
 627
 628                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
 629                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
 630                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
 631
 632                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
 633                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
 634                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
 635
 636                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
 637                         MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
 638
 639                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
 640                         MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
 641         }
 642 }
 643
 644 #define PHASE_STEP_SHIFT        21
 645 #define DOWN_SCALE_RATIO_MAX    32      /* 2^(26-21) */
 646
 647 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
 648 {
 649         uint32_t unit;
 650
 651         if (src == 0 || dst == 0)
 652                 return -EINVAL;
 653
 654         /*
 655          * PHASE_STEP_X/Y is coded on 26 bits (25:0),
 656          * where 2^21 represents the unity "1" in fixed-point hardware design.
 657          * This leaves 5 bits for the integer part (downscale case):
 658          *      -> maximum downscale ratio = 0b1_1111 = 31
 659          */
 660         if (src > (dst * DOWN_SCALE_RATIO_MAX))
 661                 return -EOVERFLOW;
 662
 663         unit = 1 << PHASE_STEP_SHIFT;
 664         *out_phase = mult_frac(unit, src, dst);
 665
 666         return 0;
 667 }
 668
 669 static int calc_scalex_steps(struct drm_plane *plane,
 670                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 671                 uint32_t phasex_steps[COMP_MAX])
 672 {
 673         struct mdp5_kms *mdp5_kms = get_kms(plane);
 674         struct device *dev = mdp5_kms->dev->dev;
 675         uint32_t phasex_step;
 676         unsigned int hsub;
 677         int ret;
 678
 679         ret = calc_phase_step(src, dest, &phasex_step);
 680         if (ret) {
 681                 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
 682                 return ret;
 683         }
 684
 685         hsub = drm_format_horz_chroma_subsampling(pixel_format);
 686
 687         phasex_steps[COMP_0]   = phasex_step;
 688         phasex_steps[COMP_3]   = phasex_step;
 689         phasex_steps[COMP_1_2] = phasex_step / hsub;
 690
 691         return 0;
 692 }
 693
 694 static int calc_scaley_steps(struct drm_plane *plane,
 695                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 696                 uint32_t phasey_steps[COMP_MAX])
 697 {
 698         struct mdp5_kms *mdp5_kms = get_kms(plane);
 699         struct device *dev = mdp5_kms->dev->dev;
 700         uint32_t phasey_step;
 701         unsigned int vsub;
 702         int ret;
 703
 704         ret = calc_phase_step(src, dest, &phasey_step);
 705         if (ret) {
 706                 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
 707                 return ret;
 708         }
 709
 710         vsub = drm_format_vert_chroma_subsampling(pixel_format);
 711
 712         phasey_steps[COMP_0]   = phasey_step;
 713         phasey_steps[COMP_3]   = phasey_step;
 714         phasey_steps[COMP_1_2] = phasey_step / vsub;
 715
 716         return 0;
 717 }
 718
 719 static uint32_t get_scale_config(const struct mdp_format *format,
 720                 uint32_t src, uint32_t dst, bool horz)
 721 {
 722         bool scaling = format->is_yuv ? true : (src != dst);
 723         uint32_t sub, pix_fmt = format->base.pixel_format;
 724         uint32_t ya_filter, uv_filter;
 725         bool yuv = format->is_yuv;
 726
 727         if (!scaling)
 728                 return 0;
 729
 730         if (yuv) {
 731                 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
 732                              drm_format_vert_chroma_subsampling(pix_fmt);
 733                 uv_filter = ((src / sub) <= dst) ?
 734                                    SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 735         }
 736         ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 737
 738         if (horz)
 739                 return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
 740                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
 741                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
 742                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
 743         else
 744                 return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
 745                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
 746                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
 747                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
 748 }
 749
 750 static void calc_pixel_ext(const struct mdp_format *format,
 751                 uint32_t src, uint32_t dst, uint32_t phase_step[2],
 752                 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
 753                 bool horz)
 754 {
 755         bool scaling = format->is_yuv ? true : (src != dst);
 756         int i;
 757
 758         /*
 759          * Note:
 760          * We assume here that:
 761          *     1. PCMN filter is used for downscale
 762          *     2. bilinear filter is used for upscale
 763          *     3. we are in a single pipe configuration
 764          */
 765
 766         for (i = 0; i < COMP_MAX; i++) {
 767                 pix_ext_edge1[i] = 0;
 768                 pix_ext_edge2[i] = scaling ? 1 : 0;
 769         }
 770 }
 771
 772 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 773         const struct mdp_format *format,
 774         uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
 775         uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
 776 {
 777         uint32_t pix_fmt = format->base.pixel_format;
 778         uint32_t lr, tb, req;
 779         int i;
 780
 781         for (i = 0; i < COMP_MAX; i++) {
 782                 uint32_t roi_w = src_w;
 783                 uint32_t roi_h = src_h;
 784
 785                 if (format->is_yuv && i == COMP_1_2) {
 786                         roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
 787                         roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
 788                 }
 789
 790                 lr  = (pe_left[i] >= 0) ?
 791                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
 792                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
 793
 794                 lr |= (pe_right[i] >= 0) ?
 795                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
 796                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
 797
 798                 tb  = (pe_top[i] >= 0) ?
 799                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
 800                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
 801
 802                 tb |= (pe_bottom[i] >= 0) ?
 803                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
 804                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
 805
 806                 req  = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
 807                                 pe_left[i] + pe_right[i]);
 808
 809                 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
 810                                 pe_top[i] + pe_bottom[i]);
 811
 812                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
 813                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
 814                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
 815
 816                 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 817                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
 818                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
 819                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
 820                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
 821                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
 822
 823                 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 824                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
 825                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
 826                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
 827                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
 828                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
 829         }
 830 }
 831
 832 struct pixel_ext {
 833         int left[COMP_MAX];
 834         int right[COMP_MAX];
 835         int top[COMP_MAX];
 836         int bottom[COMP_MAX];
 837 };
 838
 839 struct phase_step {
 840         u32 x[COMP_MAX];
 841         u32 y[COMP_MAX];
 842 };
 843
 844 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
 845                                  struct mdp5_hw_pipe *hwpipe,
 846                                  struct drm_framebuffer *fb,
 847                                  struct phase_step *step,
 848                                  struct pixel_ext *pe,
 849                                  u32 scale_config, u32 hdecm, u32 vdecm,
 850                                  bool hflip, bool vflip,
 851                                  int crtc_x, int crtc_y,
 852                                  unsigned int crtc_w, unsigned int crtc_h,
 853                                  u32 src_img_w, u32 src_img_h,
 854                                  u32 src_x, u32 src_y,
 855                                  u32 src_w, u32 src_h)
 856 {
 857         enum mdp5_pipe pipe = hwpipe->pipe;
 858         bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
 859         const struct mdp_format *format =
 860                         to_mdp_format(msm_framebuffer_format(fb));
 861
 862         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
 863                         MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
 864                         MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
 865
 866         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
 867                         MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
 868                         MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
 869
 870         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
 871                         MDP5_PIPE_SRC_XY_X(src_x) |
 872                         MDP5_PIPE_SRC_XY_Y(src_y));
 873
 874         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
 875                         MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
 876                         MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
 877
 878         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
 879                         MDP5_PIPE_OUT_XY_X(crtc_x) |
 880                         MDP5_PIPE_OUT_XY_Y(crtc_y));
 881
 882         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
 883                         MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 884                         MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 885                         MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 886                         MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 887                         COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 888                         MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 889                         MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 890                         COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
 891                         MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
 892                         MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
 893
 894         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
 895                         MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 896                         MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 897                         MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 898                         MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 899
 900         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
 901                         (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
 902                         (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
 903                         COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
 904                         MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
 905
 906         /* not using secure mode: */
 907         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
 908
 909         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
 910                 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
 911                                 src_w, pe->left, pe->right,
 912                                 src_h, pe->top, pe->bottom);
 913
 914         if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
 915                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
 916                                 step->x[COMP_0]);
 917                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
 918                                 step->y[COMP_0]);
 919                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
 920                                 step->x[COMP_1_2]);
 921                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
 922                                 step->y[COMP_1_2]);
 923                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
 924                                 MDP5_PIPE_DECIMATION_VERT(vdecm) |
 925                                 MDP5_PIPE_DECIMATION_HORZ(hdecm));
 926                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
 927                            scale_config);
 928         }
 929
 930         if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
 931                 if (MDP_FORMAT_IS_YUV(format))
 932                         csc_enable(mdp5_kms, pipe,
 933                                         mdp_get_default_csc_cfg(CSC_YUV2RGB));
 934                 else
 935                         csc_disable(mdp5_kms, pipe);
 936         }
 937
 938         set_scanout_locked(mdp5_kms, pipe, fb);
 939 }
 940
 941 static int mdp5_plane_mode_set(struct drm_plane *plane,
 942                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 943                 struct drm_rect *src, struct drm_rect *dest)
 944 {
 945         struct drm_plane_state *pstate = plane->state;
 946         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
 947         struct mdp5_kms *mdp5_kms = get_kms(plane);
 948         enum mdp5_pipe pipe = hwpipe->pipe;
 949         struct mdp5_hw_pipe *right_hwpipe;
 950         const struct mdp_format *format;
 951         uint32_t nplanes, config = 0;
 952         struct phase_step step = { { 0 } };
 953         struct pixel_ext pe = { { 0 } };
 954         uint32_t hdecm = 0, vdecm = 0;
 955         uint32_t pix_format;
 956         unsigned int rotation;
 957         bool vflip, hflip;
 958         int crtc_x, crtc_y;
 959         unsigned int crtc_w, crtc_h;
 960         uint32_t src_x, src_y;
 961         uint32_t src_w, src_h;
 962         uint32_t src_img_w, src_img_h;
 963         int ret;
 964
 965         nplanes = fb->format->num_planes;
 966
 967         /* bad formats should already be rejected: */
 968         if (WARN_ON(nplanes > pipe2nclients(pipe)))
 969                 return -EINVAL;
 970
 971         format = to_mdp_format(msm_framebuffer_format(fb));
 972         pix_format = format->base.pixel_format;
 973
 974         src_x = src->x1;
 975         src_y = src->y1;
 976         src_w = drm_rect_width(src);
 977         src_h = drm_rect_height(src);
 978
 979         crtc_x = dest->x1;
 980         crtc_y = dest->y1;
 981         crtc_w = drm_rect_width(dest);
 982         crtc_h = drm_rect_height(dest);
 983
 984         /* src values are in Q16 fixed point, convert to integer: */
 985         src_x = src_x >> 16;
 986         src_y = src_y >> 16;
 987         src_w = src_w >> 16;
 988         src_h = src_h >> 16;
 989
 990         src_img_w = min(fb->width, src_w);
 991         src_img_h = min(fb->height, src_h);
 992
 993         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
 994                         fb->base.id, src_x, src_y, src_w, src_h,
 995                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 996
 997         right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
 998         if (right_hwpipe) {
 999                 /*
1000                  * if the plane comprises of 2 hw pipes, assume that the width
1001                  * is split equally across them. The only parameters that varies
1002                  * between the 2 pipes are src_x and crtc_x
1003                  */
1004                 crtc_w /= 2;
1005                 src_w /= 2;
1006                 src_img_w /= 2;
1007         }
1008
1009         ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
1010         if (ret)
1011                 return ret;
1012
1013         ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
1014         if (ret)
1015                 return ret;
1016
1017         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
1018                 calc_pixel_ext(format, src_w, crtc_w, step.x,
1019                                pe.left, pe.right, true);
1020                 calc_pixel_ext(format, src_h, crtc_h, step.y,
1021                                pe.top, pe.bottom, false);
1022         }
1023
1024         /* TODO calc hdecm, vdecm */
1025
1026         /* SCALE is used to both scale and up-sample chroma components */
1027         config |= get_scale_config(format, src_w, crtc_w, true);
1028         config |= get_scale_config(format, src_h, crtc_h, false);
1029         DBG("scale config = %x", config);
1030
1031         rotation = drm_rotation_simplify(pstate->rotation,
1032                                          DRM_MODE_ROTATE_0 |
1033                                          DRM_MODE_REFLECT_X |
1034                                          DRM_MODE_REFLECT_Y);
1035         hflip = !!(rotation & DRM_MODE_REFLECT_X);
1036         vflip = !!(rotation & DRM_MODE_REFLECT_Y);
1037
1038         mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
1039                              config, hdecm, vdecm, hflip, vflip,
1040                              crtc_x, crtc_y, crtc_w, crtc_h,
1041                              src_img_w, src_img_h,
1042                              src_x, src_y, src_w, src_h);
1043         if (right_hwpipe)
1044                 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
1045                                      config, hdecm, vdecm, hflip, vflip,
1046                                      crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
1047                                      src_img_w, src_img_h,
1048                                      src_x + src_w, src_y, src_w, src_h);
1049
1050         return ret;
1051 }
1052
1053 /*
1054  * Use this func and the one below only after the atomic state has been
1055  * successfully swapped
1056  */
1057 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1058 {
1059         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1060
1061         if (WARN_ON(!pstate->hwpipe))
1062                 return SSPP_NONE;
1063
1064         return pstate->hwpipe->pipe;
1065 }
1066
1067 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1068 {
1069         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1070
1071         if (!pstate->r_hwpipe)
1072                 return SSPP_NONE;
1073
1074         return pstate->r_hwpipe->pipe;
1075 }
1076
1077 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1078 {
1079         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1080         u32 mask;
1081
1082         if (WARN_ON(!pstate->hwpipe))
1083                 return 0;
1084
1085         mask = pstate->hwpipe->flush_mask;
1086
1087         if (pstate->r_hwpipe)
1088                 mask |= pstate->r_hwpipe->flush_mask;
1089
1090         return mask;
1091 }
1092
1093 /* initialize plane */
1094 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1095                                   enum drm_plane_type type)
1096 {
1097         struct drm_plane *plane = NULL;
1098         struct mdp5_plane *mdp5_plane;
1099         int ret;
1100
1101         mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1102         if (!mdp5_plane) {
1103                 ret = -ENOMEM;
1104                 goto fail;
1105         }
1106
1107         plane = &mdp5_plane->base;
1108
1109         mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1110                 ARRAY_SIZE(mdp5_plane->formats), false);
1111
1112         ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1113                         mdp5_plane->formats, mdp5_plane->nformats,
1114                         NULL, type, NULL);
1115         if (ret)
1116                 goto fail;
1117
1118         drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1119
1120         mdp5_plane_install_properties(plane, &plane->base);
1121
1122         return plane;
1123
1124 fail:
1125         if (plane)
1126                 mdp5_plane_destroy(plane);
1127
1128         return ERR_PTR(ret);
1129 }