2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <video/mipi_display.h>
37 #define DSI_RESET_TOGGLE_DELAY_MS 20
39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
48 * makes all other registers 4-byte shifted down.
50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
51 * older, we read the DSI_VERSION register without any shift(offset
52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
53 * the case of DSI6G, this has to be zero (the offset points to a
54 * scratch register which we never touch)
57 ver = msm_readl(base + REG_DSI_VERSION);
59 /* older dsi host, there is no register shift */
60 ver = FIELD(ver, DSI_VERSION_MAJOR);
61 if (ver <= MSM_DSI_VER_MAJOR_V2) {
71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
72 * registers are shifted down, read DSI_VERSION again with
75 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
76 ver = FIELD(ver, DSI_VERSION_MAJOR);
77 if (ver == MSM_DSI_VER_MAJOR_6G) {
80 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
88 #define DSI_ERR_STATE_ACK 0x0000
89 #define DSI_ERR_STATE_TIMEOUT 0x0001
90 #define DSI_ERR_STATE_DLN0_PHY 0x0002
91 #define DSI_ERR_STATE_FIFO 0x0004
92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
96 #define DSI_CLK_CTRL_ENABLE_CLKS \
97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
102 struct msm_dsi_host {
103 struct mipi_dsi_host base;
105 struct platform_device *pdev;
106 struct drm_device *dev;
110 void __iomem *ctrl_base;
111 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
113 struct clk *bus_clks[DSI_BUS_CLK_MAX];
115 struct clk *byte_clk;
117 struct clk *pixel_clk;
118 struct clk *byte_clk_src;
119 struct clk *pixel_clk_src;
120 struct clk *byte_intf_clk;
126 /* DSI v2 specific clocks */
128 struct clk *esc_clk_src;
129 struct clk *dsi_clk_src;
133 struct gpio_desc *disp_en_gpio;
134 struct gpio_desc *te_gpio;
136 const struct msm_dsi_cfg_handler *cfg_hnd;
138 struct completion dma_comp;
139 struct completion video_comp;
140 struct mutex dev_mutex;
141 struct mutex cmd_mutex;
142 spinlock_t intr_lock; /* Protect interrupt ctrl register */
145 struct work_struct err_work;
146 struct work_struct hpd_work;
147 struct workqueue_struct *workqueue;
149 /* DSI 6G TX buffer*/
150 struct drm_gem_object *tx_gem_obj;
152 /* DSI v2 TX buffer */
154 dma_addr_t tx_buf_paddr;
162 struct drm_display_mode *mode;
164 /* connected device info */
165 struct device_node *device_node;
166 unsigned int channel;
168 enum mipi_dsi_pixel_format format;
169 unsigned long mode_flags;
171 /* lane data parsed via DT */
175 u32 dma_cmd_ctrl_restore;
183 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
186 case MIPI_DSI_FMT_RGB565: return 16;
187 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
188 case MIPI_DSI_FMT_RGB666:
189 case MIPI_DSI_FMT_RGB888:
194 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
196 return msm_readl(msm_host->ctrl_base + reg);
198 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
200 msm_writel(data, msm_host->ctrl_base + reg);
203 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
204 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
206 static const struct msm_dsi_cfg_handler *dsi_get_config(
207 struct msm_dsi_host *msm_host)
209 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
210 struct device *dev = &msm_host->pdev->dev;
211 struct regulator *gdsc_reg;
214 u32 major = 0, minor = 0;
216 gdsc_reg = regulator_get(dev, "gdsc");
217 if (IS_ERR(gdsc_reg)) {
218 pr_err("%s: cannot get gdsc\n", __func__);
222 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
223 if (IS_ERR(ahb_clk)) {
224 pr_err("%s: cannot get interface clock\n", __func__);
228 pm_runtime_get_sync(dev);
230 ret = regulator_enable(gdsc_reg);
232 pr_err("%s: unable to enable gdsc\n", __func__);
236 ret = clk_prepare_enable(ahb_clk);
238 pr_err("%s: unable to enable ahb_clk\n", __func__);
242 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
244 pr_err("%s: Invalid version\n", __func__);
248 cfg_hnd = msm_dsi_cfg_get(major, minor);
250 DBG("%s: Version %x:%x\n", __func__, major, minor);
253 clk_disable_unprepare(ahb_clk);
255 regulator_disable(gdsc_reg);
256 pm_runtime_put_sync(dev);
258 regulator_put(gdsc_reg);
263 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
265 return container_of(host, struct msm_dsi_host, base);
268 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
270 struct regulator_bulk_data *s = msm_host->supplies;
271 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
272 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
276 for (i = num - 1; i >= 0; i--)
277 if (regs[i].disable_load >= 0)
278 regulator_set_load(s[i].consumer,
279 regs[i].disable_load);
281 regulator_bulk_disable(num, s);
284 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
286 struct regulator_bulk_data *s = msm_host->supplies;
287 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
288 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
292 for (i = 0; i < num; i++) {
293 if (regs[i].enable_load >= 0) {
294 ret = regulator_set_load(s[i].consumer,
295 regs[i].enable_load);
297 pr_err("regulator %d set op mode failed, %d\n",
304 ret = regulator_bulk_enable(num, s);
306 pr_err("regulator enable failed, %d\n", ret);
313 for (i--; i >= 0; i--)
314 regulator_set_load(s[i].consumer, regs[i].disable_load);
318 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
320 struct regulator_bulk_data *s = msm_host->supplies;
321 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
322 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
325 for (i = 0; i < num; i++)
326 s[i].supply = regs[i].name;
328 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
330 pr_err("%s: failed to init regulator, ret=%d\n",
338 int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
340 struct platform_device *pdev = msm_host->pdev;
343 msm_host->src_clk = msm_clk_get(pdev, "src");
345 if (IS_ERR(msm_host->src_clk)) {
346 ret = PTR_ERR(msm_host->src_clk);
347 pr_err("%s: can't find src clock. ret=%d\n",
349 msm_host->src_clk = NULL;
353 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
354 if (!msm_host->esc_clk_src) {
356 pr_err("%s: can't get esc clock parent. ret=%d\n",
361 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
362 if (!msm_host->dsi_clk_src) {
364 pr_err("%s: can't get src clock parent. ret=%d\n",
371 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
373 struct platform_device *pdev = msm_host->pdev;
376 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
377 if (IS_ERR(msm_host->byte_intf_clk)) {
378 ret = PTR_ERR(msm_host->byte_intf_clk);
379 pr_err("%s: can't find byte_intf clock. ret=%d\n",
386 static int dsi_clk_init(struct msm_dsi_host *msm_host)
388 struct platform_device *pdev = msm_host->pdev;
389 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
390 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
394 for (i = 0; i < cfg->num_bus_clks; i++) {
395 msm_host->bus_clks[i] = msm_clk_get(pdev,
396 cfg->bus_clk_names[i]);
397 if (IS_ERR(msm_host->bus_clks[i])) {
398 ret = PTR_ERR(msm_host->bus_clks[i]);
399 pr_err("%s: Unable to get %s clock, ret = %d\n",
400 __func__, cfg->bus_clk_names[i], ret);
405 /* get link and source clocks */
406 msm_host->byte_clk = msm_clk_get(pdev, "byte");
407 if (IS_ERR(msm_host->byte_clk)) {
408 ret = PTR_ERR(msm_host->byte_clk);
409 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
411 msm_host->byte_clk = NULL;
415 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
416 if (IS_ERR(msm_host->pixel_clk)) {
417 ret = PTR_ERR(msm_host->pixel_clk);
418 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
420 msm_host->pixel_clk = NULL;
424 msm_host->esc_clk = msm_clk_get(pdev, "core");
425 if (IS_ERR(msm_host->esc_clk)) {
426 ret = PTR_ERR(msm_host->esc_clk);
427 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
429 msm_host->esc_clk = NULL;
433 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
434 if (IS_ERR(msm_host->byte_clk_src)) {
435 ret = PTR_ERR(msm_host->byte_clk_src);
436 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
440 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
441 if (IS_ERR(msm_host->pixel_clk_src)) {
442 ret = PTR_ERR(msm_host->pixel_clk_src);
443 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
447 if (cfg_hnd->ops->clk_init_ver)
448 ret = cfg_hnd->ops->clk_init_ver(msm_host);
453 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
455 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
458 DBG("id=%d", msm_host->id);
460 for (i = 0; i < cfg->num_bus_clks; i++) {
461 ret = clk_prepare_enable(msm_host->bus_clks[i]);
463 pr_err("%s: failed to enable bus clock %d ret %d\n",
472 clk_disable_unprepare(msm_host->bus_clks[i]);
477 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
479 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
484 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
485 clk_disable_unprepare(msm_host->bus_clks[i]);
488 int msm_dsi_runtime_suspend(struct device *dev)
490 struct platform_device *pdev = to_platform_device(dev);
491 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
492 struct mipi_dsi_host *host = msm_dsi->host;
493 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
495 if (!msm_host->cfg_hnd)
498 dsi_bus_clk_disable(msm_host);
503 int msm_dsi_runtime_resume(struct device *dev)
505 struct platform_device *pdev = to_platform_device(dev);
506 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
507 struct mipi_dsi_host *host = msm_dsi->host;
508 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
510 if (!msm_host->cfg_hnd)
513 return dsi_bus_clk_enable(msm_host);
516 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
520 DBG("Set clk rates: pclk=%d, byteclk=%d",
521 msm_host->mode->clock, msm_host->byte_clk_rate);
523 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
525 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
529 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
531 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
535 if (msm_host->byte_intf_clk) {
536 ret = clk_set_rate(msm_host->byte_intf_clk,
537 msm_host->byte_clk_rate / 2);
539 pr_err("%s: Failed to set rate byte intf clk, %d\n",
545 ret = clk_prepare_enable(msm_host->esc_clk);
547 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
551 ret = clk_prepare_enable(msm_host->byte_clk);
553 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
557 ret = clk_prepare_enable(msm_host->pixel_clk);
559 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
563 if (msm_host->byte_intf_clk) {
564 ret = clk_prepare_enable(msm_host->byte_intf_clk);
566 pr_err("%s: Failed to enable byte intf clk\n",
568 goto byte_intf_clk_err;
575 clk_disable_unprepare(msm_host->pixel_clk);
577 clk_disable_unprepare(msm_host->byte_clk);
579 clk_disable_unprepare(msm_host->esc_clk);
584 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
588 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
589 msm_host->mode->clock, msm_host->byte_clk_rate,
590 msm_host->esc_clk_rate, msm_host->src_clk_rate);
592 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
594 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
598 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
600 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
604 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
606 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
610 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
612 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
616 ret = clk_prepare_enable(msm_host->byte_clk);
618 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
622 ret = clk_prepare_enable(msm_host->esc_clk);
624 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
628 ret = clk_prepare_enable(msm_host->src_clk);
630 pr_err("%s: Failed to enable dsi src clk\n", __func__);
634 ret = clk_prepare_enable(msm_host->pixel_clk);
636 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
643 clk_disable_unprepare(msm_host->src_clk);
645 clk_disable_unprepare(msm_host->esc_clk);
647 clk_disable_unprepare(msm_host->byte_clk);
652 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
654 clk_disable_unprepare(msm_host->esc_clk);
655 clk_disable_unprepare(msm_host->pixel_clk);
656 if (msm_host->byte_intf_clk)
657 clk_disable_unprepare(msm_host->byte_intf_clk);
658 clk_disable_unprepare(msm_host->byte_clk);
661 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
663 clk_disable_unprepare(msm_host->pixel_clk);
664 clk_disable_unprepare(msm_host->src_clk);
665 clk_disable_unprepare(msm_host->esc_clk);
666 clk_disable_unprepare(msm_host->byte_clk);
669 static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
671 struct drm_display_mode *mode = msm_host->mode;
674 pclk_rate = mode->clock * 1000;
677 * For dual DSI mode, the current DRM mode has the complete width of the
678 * panel. Since, the complete panel is driven by two DSI controllers,
679 * the clock rates have to be split between the two dsi controllers.
680 * Adjust the byte and pixel clock rates for each dsi host accordingly.
688 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi)
690 u8 lanes = msm_host->lanes;
691 u32 bpp = dsi_get_bpp(msm_host->format);
692 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi);
693 u64 pclk_bpp = (u64)pclk_rate * bpp;
696 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
700 do_div(pclk_bpp, (8 * lanes));
702 msm_host->pixel_clk_rate = pclk_rate;
703 msm_host->byte_clk_rate = pclk_bpp;
705 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
706 msm_host->byte_clk_rate);
710 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi)
712 if (!msm_host->mode) {
713 pr_err("%s: mode not set\n", __func__);
717 dsi_calc_pclk(msm_host, is_dual_dsi);
718 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
722 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
724 u32 bpp = dsi_get_bpp(msm_host->format);
726 unsigned int esc_mhz, esc_div;
727 unsigned long byte_mhz;
729 dsi_calc_pclk(msm_host, is_dual_dsi);
731 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp;
733 msm_host->src_clk_rate = pclk_bpp;
736 * esc clock is byte clock followed by a 4 bit divider,
737 * we need to find an escape clock frequency within the
738 * mipi DSI spec range within the maximum divider limit
739 * We iterate here between an escape clock frequencey
740 * between 20 Mhz to 5 Mhz and pick up the first one
741 * that can be supported by our divider
744 byte_mhz = msm_host->byte_clk_rate / 1000000;
746 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
747 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
750 * TODO: Ideally, we shouldn't know what sort of divider
751 * is available in mmss_cc, we're just assuming that
752 * it'll always be a 4 bit divider. Need to come up with
755 if (esc_div >= 1 && esc_div <= 16)
762 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
764 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
765 msm_host->src_clk_rate);
770 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
775 spin_lock_irqsave(&msm_host->intr_lock, flags);
776 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
783 DBG("intr=%x enable=%d", intr, enable);
785 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
786 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
789 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
791 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
793 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
794 return NON_BURST_SYNCH_PULSE;
796 return NON_BURST_SYNCH_EVENT;
799 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
800 const enum mipi_dsi_pixel_format mipi_fmt)
803 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
804 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
805 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
806 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
807 default: return VID_DST_FORMAT_RGB888;
811 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
812 const enum mipi_dsi_pixel_format mipi_fmt)
815 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
816 case MIPI_DSI_FMT_RGB666_PACKED:
817 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
818 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
819 default: return CMD_DST_FORMAT_RGB888;
823 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
824 struct msm_dsi_phy_shared_timings *phy_shared_timings)
826 u32 flags = msm_host->mode_flags;
827 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
828 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
832 dsi_write(msm_host, REG_DSI_CTRL, 0);
836 if (flags & MIPI_DSI_MODE_VIDEO) {
837 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
838 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
839 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
840 data |= DSI_VID_CFG0_HFP_POWER_STOP;
841 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
842 data |= DSI_VID_CFG0_HBP_POWER_STOP;
843 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
844 data |= DSI_VID_CFG0_HSA_POWER_STOP;
845 /* Always set low power stop mode for BLLP
846 * to let command engine send packets
848 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
849 DSI_VID_CFG0_BLLP_POWER_STOP;
850 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
851 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
852 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
853 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
855 /* Do not swap RGB colors */
856 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
857 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
859 /* Do not swap RGB colors */
860 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
861 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
862 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
864 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
865 DSI_CMD_CFG1_WR_MEM_CONTINUE(
866 MIPI_DCS_WRITE_MEMORY_CONTINUE);
867 /* Always insert DCS command */
868 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
869 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
872 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
873 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
874 DSI_CMD_DMA_CTRL_LOW_POWER);
877 /* Always assume dedicated TE pin */
878 data |= DSI_TRIG_CTRL_TE;
879 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
880 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
881 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
882 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
883 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
884 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
885 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
887 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
888 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
889 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
891 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
892 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
893 phy_shared_timings->clk_pre_inc_by_2)
894 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
895 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
898 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
899 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
900 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
902 /* allow only ack-err-status to generate interrupt */
903 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
905 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
907 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
909 data = DSI_CTRL_CLK_EN;
911 DBG("lane number=%d", msm_host->lanes);
912 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
914 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
915 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
917 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
918 dsi_write(msm_host, REG_DSI_LANE_CTRL,
919 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
921 data |= DSI_CTRL_ENABLE;
923 dsi_write(msm_host, REG_DSI_CTRL, data);
926 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
928 struct drm_display_mode *mode = msm_host->mode;
929 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
930 u32 h_total = mode->htotal;
931 u32 v_total = mode->vtotal;
932 u32 hs_end = mode->hsync_end - mode->hsync_start;
933 u32 vs_end = mode->vsync_end - mode->vsync_start;
934 u32 ha_start = h_total - mode->hsync_start;
935 u32 ha_end = ha_start + mode->hdisplay;
936 u32 va_start = v_total - mode->vsync_start;
937 u32 va_end = va_start + mode->vdisplay;
938 u32 hdisplay = mode->hdisplay;
944 * For dual DSI mode, the current DRM mode has
945 * the complete width of the panel. Since, the complete
946 * panel is driven by two DSI controllers, the horizontal
947 * timings have to be split between the two dsi controllers.
948 * Adjust the DSI host timing values accordingly.
958 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
959 dsi_write(msm_host, REG_DSI_ACTIVE_H,
960 DSI_ACTIVE_H_START(ha_start) |
961 DSI_ACTIVE_H_END(ha_end));
962 dsi_write(msm_host, REG_DSI_ACTIVE_V,
963 DSI_ACTIVE_V_START(va_start) |
964 DSI_ACTIVE_V_END(va_end));
965 dsi_write(msm_host, REG_DSI_TOTAL,
966 DSI_TOTAL_H_TOTAL(h_total - 1) |
967 DSI_TOTAL_V_TOTAL(v_total - 1));
969 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
970 DSI_ACTIVE_HSYNC_START(hs_start) |
971 DSI_ACTIVE_HSYNC_END(hs_end));
972 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
973 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
974 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
975 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
976 } else { /* command mode */
977 /* image data and 1 byte write_memory_start cmd */
978 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
980 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
981 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
982 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
984 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
985 MIPI_DSI_DCS_LONG_WRITE));
987 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
988 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) |
989 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
993 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
995 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
996 wmb(); /* clocks need to be enabled before reset */
998 dsi_write(msm_host, REG_DSI_RESET, 1);
999 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1000 dsi_write(msm_host, REG_DSI_RESET, 0);
1003 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
1004 bool video_mode, bool enable)
1008 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1011 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1012 DSI_CTRL_CMD_MODE_EN);
1013 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1014 DSI_IRQ_MASK_VIDEO_DONE, 0);
1017 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1018 } else { /* command mode */
1019 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1020 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1022 dsi_ctrl |= DSI_CTRL_ENABLE;
1025 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1028 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1032 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1035 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1037 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1039 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1042 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1045 struct device *dev = &msm_host->pdev->dev;
1047 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1049 reinit_completion(&msm_host->video_comp);
1051 ret = wait_for_completion_timeout(&msm_host->video_comp,
1052 msecs_to_jiffies(70));
1055 dev_err(dev, "wait for video done timed out\n");
1057 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1060 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1062 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1065 if (msm_host->power_on && msm_host->enabled) {
1066 dsi_wait4video_done(msm_host);
1067 /* delay 4 ms to skip BLLP */
1068 usleep_range(2000, 4000);
1072 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1074 struct drm_device *dev = msm_host->dev;
1075 struct msm_drm_private *priv = dev->dev_private;
1079 data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
1081 &msm_host->tx_gem_obj, &iova);
1084 msm_host->tx_gem_obj = NULL;
1085 return PTR_ERR(data);
1088 msm_host->tx_size = msm_host->tx_gem_obj->size;
1093 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1095 struct drm_device *dev = msm_host->dev;
1097 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1098 &msm_host->tx_buf_paddr, GFP_KERNEL);
1099 if (!msm_host->tx_buf)
1102 msm_host->tx_size = size;
1107 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1109 struct drm_device *dev = msm_host->dev;
1110 struct msm_drm_private *priv;
1113 * This is possible if we're tearing down before we've had a chance to
1114 * fully initialize. A very real possibility if our probe is deferred,
1115 * in which case we'll hit msm_dsi_host_destroy() without having run
1116 * through the dsi_tx_buf_alloc().
1121 priv = dev->dev_private;
1122 if (msm_host->tx_gem_obj) {
1123 msm_gem_put_iova(msm_host->tx_gem_obj, priv->kms->aspace);
1124 drm_gem_object_put_unlocked(msm_host->tx_gem_obj);
1125 msm_host->tx_gem_obj = NULL;
1128 if (msm_host->tx_buf)
1129 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1130 msm_host->tx_buf_paddr);
1133 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1135 return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1138 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1140 return msm_host->tx_buf;
1143 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1145 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1149 * prepare cmd buffer to be txed
1151 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1152 const struct mipi_dsi_msg *msg)
1154 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1155 struct mipi_dsi_packet packet;
1160 ret = mipi_dsi_create_packet(&packet, msg);
1162 pr_err("%s: create packet failed, %d\n", __func__, ret);
1165 len = (packet.size + 3) & (~0x3);
1167 if (len > msm_host->tx_size) {
1168 pr_err("%s: packet size is too big\n", __func__);
1172 data = cfg_hnd->ops->tx_buf_get(msm_host);
1174 ret = PTR_ERR(data);
1175 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1179 /* MSM specific command format in memory */
1180 data[0] = packet.header[1];
1181 data[1] = packet.header[2];
1182 data[2] = packet.header[0];
1183 data[3] = BIT(7); /* Last packet */
1184 if (mipi_dsi_packet_format_is_long(msg->type))
1186 if (msg->rx_buf && msg->rx_len)
1190 if (packet.payload && packet.payload_length)
1191 memcpy(data + 4, packet.payload, packet.payload_length);
1193 /* Append 0xff to the end */
1194 if (packet.size < len)
1195 memset(data + packet.size, 0xff, len - packet.size);
1197 if (cfg_hnd->ops->tx_buf_put)
1198 cfg_hnd->ops->tx_buf_put(msm_host);
1204 * dsi_short_read1_resp: 1 parameter
1206 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1208 u8 *data = msg->rx_buf;
1209 if (data && (msg->rx_len >= 1)) {
1210 *data = buf[1]; /* strip out dcs type */
1213 pr_err("%s: read data does not match with rx_buf len %zu\n",
1214 __func__, msg->rx_len);
1220 * dsi_short_read2_resp: 2 parameter
1222 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1224 u8 *data = msg->rx_buf;
1225 if (data && (msg->rx_len >= 2)) {
1226 data[0] = buf[1]; /* strip out dcs type */
1230 pr_err("%s: read data does not match with rx_buf len %zu\n",
1231 __func__, msg->rx_len);
1236 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1238 /* strip out 4 byte dcs header */
1239 if (msg->rx_buf && msg->rx_len)
1240 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1245 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1247 struct drm_device *dev = msm_host->dev;
1248 struct msm_drm_private *priv = dev->dev_private;
1253 return msm_gem_get_iova(msm_host->tx_gem_obj,
1254 priv->kms->aspace, dma_base);
1257 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1262 *dma_base = msm_host->tx_buf_paddr;
1266 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1268 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1273 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1275 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1279 reinit_completion(&msm_host->dma_comp);
1281 dsi_wait4video_eng_busy(msm_host);
1283 triggered = msm_dsi_manager_cmd_xfer_trigger(
1284 msm_host->id, dma_base, len);
1286 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1287 msecs_to_jiffies(200));
1299 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1300 u8 *buf, int rx_byte, int pkt_size)
1302 u32 *lp, *temp, data;
1306 int repeated_bytes = 0;
1307 int buf_offset = buf - msm_host->rx_buf;
1311 cnt = (rx_byte + 3) >> 2;
1313 cnt = 4; /* 4 x 32 bits registers only */
1318 read_cnt = pkt_size + 6;
1321 * In case of multiple reads from the panel, after the first read, there
1322 * is possibility that there are some bytes in the payload repeating in
1323 * the RDBK_DATA registers. Since we read all the parameters from the
1324 * panel right from the first byte for every pass. We need to skip the
1325 * repeating bytes and then append the new parameters to the rx buffer.
1327 if (read_cnt > 16) {
1329 /* Any data more than 16 bytes will be shifted out.
1330 * The temp read buffer should already contain these bytes.
1331 * The remaining bytes in read buffer are the repeated bytes.
1333 bytes_shifted = read_cnt - 16;
1334 repeated_bytes = buf_offset - bytes_shifted;
1337 for (i = cnt - 1; i >= 0; i--) {
1338 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1339 *temp++ = ntohl(data); /* to host byte order */
1340 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1343 for (i = repeated_bytes; i < 16; i++)
1349 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1350 const struct mipi_dsi_msg *msg)
1353 int bllp_len = msm_host->mode->hdisplay *
1354 dsi_get_bpp(msm_host->format) / 8;
1356 len = dsi_cmd_dma_add(msm_host, msg);
1358 pr_err("%s: failed to add cmd type = 0x%x\n",
1359 __func__, msg->type);
1363 /* for video mode, do not send cmds more than
1364 * one pixel line, since it only transmit it
1367 /* TODO: if the command is sent in LP mode, the bit rate is only
1368 * half of esc clk rate. In this case, if the video is already
1369 * actively streaming, we need to check more carefully if the
1370 * command can be fit into one BLLP.
1372 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1373 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1378 ret = dsi_cmd_dma_tx(msm_host, len);
1380 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n",
1381 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret);
1383 } else if (ret < len) {
1384 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n",
1385 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len);
1392 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1396 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1398 data1 &= ~DSI_CTRL_ENABLE;
1399 dsi_write(msm_host, REG_DSI_CTRL, data1);
1401 * dsi controller need to be disabled before
1406 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1407 wmb(); /* make sure clocks enabled */
1409 /* dsi controller can only be reset while clocks are running */
1410 dsi_write(msm_host, REG_DSI_RESET, 1);
1411 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1412 dsi_write(msm_host, REG_DSI_RESET, 0);
1413 wmb(); /* controller out of reset */
1414 dsi_write(msm_host, REG_DSI_CTRL, data0);
1415 wmb(); /* make sure dsi controller enabled again */
1418 static void dsi_hpd_worker(struct work_struct *work)
1420 struct msm_dsi_host *msm_host =
1421 container_of(work, struct msm_dsi_host, hpd_work);
1423 drm_helper_hpd_irq_event(msm_host->dev);
1426 static void dsi_err_worker(struct work_struct *work)
1428 struct msm_dsi_host *msm_host =
1429 container_of(work, struct msm_dsi_host, err_work);
1430 u32 status = msm_host->err_work_state;
1432 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1433 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1434 dsi_sw_reset_restore(msm_host);
1436 /* It is safe to clear here because error irq is disabled. */
1437 msm_host->err_work_state = 0;
1439 /* enable dsi error interrupt */
1440 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1443 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1447 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1450 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1451 /* Writing of an extra 0 needed to clear error bits */
1452 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1453 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1457 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1461 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1464 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1465 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1469 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1473 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1475 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1476 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1477 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1478 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1479 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1480 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1481 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1485 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1489 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1491 /* fifo underflow, overflow */
1493 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1494 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1495 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1496 msm_host->err_work_state |=
1497 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1501 static void dsi_status(struct msm_dsi_host *msm_host)
1505 status = dsi_read(msm_host, REG_DSI_STATUS0);
1507 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1508 dsi_write(msm_host, REG_DSI_STATUS0, status);
1509 msm_host->err_work_state |=
1510 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1514 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1518 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1520 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1521 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1522 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1526 static void dsi_error(struct msm_dsi_host *msm_host)
1528 /* disable dsi error interrupt */
1529 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1531 dsi_clk_status(msm_host);
1532 dsi_fifo_status(msm_host);
1533 dsi_ack_err_status(msm_host);
1534 dsi_timeout_status(msm_host);
1535 dsi_status(msm_host);
1536 dsi_dln0_phy_err(msm_host);
1538 queue_work(msm_host->workqueue, &msm_host->err_work);
1541 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1543 struct msm_dsi_host *msm_host = ptr;
1545 unsigned long flags;
1547 if (!msm_host->ctrl_base)
1550 spin_lock_irqsave(&msm_host->intr_lock, flags);
1551 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1552 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1553 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1555 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1557 if (isr & DSI_IRQ_ERROR)
1558 dsi_error(msm_host);
1560 if (isr & DSI_IRQ_VIDEO_DONE)
1561 complete(&msm_host->video_comp);
1563 if (isr & DSI_IRQ_CMD_DMA_DONE)
1564 complete(&msm_host->dma_comp);
1569 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1570 struct device *panel_device)
1572 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1575 if (IS_ERR(msm_host->disp_en_gpio)) {
1576 DBG("cannot get disp-enable-gpios %ld",
1577 PTR_ERR(msm_host->disp_en_gpio));
1578 return PTR_ERR(msm_host->disp_en_gpio);
1581 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1583 if (IS_ERR(msm_host->te_gpio)) {
1584 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1585 return PTR_ERR(msm_host->te_gpio);
1591 static int dsi_host_attach(struct mipi_dsi_host *host,
1592 struct mipi_dsi_device *dsi)
1594 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1597 if (dsi->lanes > msm_host->num_data_lanes)
1600 msm_host->channel = dsi->channel;
1601 msm_host->lanes = dsi->lanes;
1602 msm_host->format = dsi->format;
1603 msm_host->mode_flags = dsi->mode_flags;
1605 msm_dsi_manager_attach_dsi_device(msm_host->id, dsi->mode_flags);
1607 /* Some gpios defined in panel DT need to be controlled by host */
1608 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1612 DBG("id=%d", msm_host->id);
1614 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1619 static int dsi_host_detach(struct mipi_dsi_host *host,
1620 struct mipi_dsi_device *dsi)
1622 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1624 msm_host->device_node = NULL;
1626 DBG("id=%d", msm_host->id);
1628 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1633 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1634 const struct mipi_dsi_msg *msg)
1636 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1639 if (!msg || !msm_host->power_on)
1642 mutex_lock(&msm_host->cmd_mutex);
1643 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1644 mutex_unlock(&msm_host->cmd_mutex);
1649 static struct mipi_dsi_host_ops dsi_host_ops = {
1650 .attach = dsi_host_attach,
1651 .detach = dsi_host_detach,
1652 .transfer = dsi_host_transfer,
1656 * List of supported physical to logical lane mappings.
1657 * For example, the 2nd entry represents the following mapping:
1659 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1661 static const int supported_data_lane_swaps[][4] = {
1672 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1673 struct device_node *ep)
1675 struct device *dev = &msm_host->pdev->dev;
1676 struct property *prop;
1678 int ret, i, len, num_lanes;
1680 prop = of_find_property(ep, "data-lanes", &len);
1683 "failed to find data lane mapping, using default\n");
1684 /* Set the number of date lanes to 4 by default. */
1685 msm_host->num_data_lanes = 4;
1689 num_lanes = len / sizeof(u32);
1691 if (num_lanes < 1 || num_lanes > 4) {
1692 dev_err(dev, "bad number of data lanes\n");
1696 msm_host->num_data_lanes = num_lanes;
1698 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1701 dev_err(dev, "failed to read lane data\n");
1706 * compare DT specified physical-logical lane mappings with the ones
1707 * supported by hardware
1709 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1710 const int *swap = supported_data_lane_swaps[i];
1714 * the data-lanes array we get from DT has a logical->physical
1715 * mapping. The "data lane swap" register field represents
1716 * supported configurations in a physical->logical mapping.
1717 * Translate the DT mapping to what we understand and find a
1718 * configuration that works.
1720 for (j = 0; j < num_lanes; j++) {
1721 if (lane_map[j] < 0 || lane_map[j] > 3)
1722 dev_err(dev, "bad physical lane entry %u\n",
1725 if (swap[lane_map[j]] != j)
1729 if (j == num_lanes) {
1730 msm_host->dlane_swap = i;
1738 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1740 struct device *dev = &msm_host->pdev->dev;
1741 struct device_node *np = dev->of_node;
1742 struct device_node *endpoint, *device_node;
1746 * Get the endpoint of the output port of the DSI host. In our case,
1747 * this is mapped to port number with reg = 1. Don't return an error if
1748 * the remote endpoint isn't defined. It's possible that there is
1749 * nothing connected to the dsi output.
1751 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1753 dev_dbg(dev, "%s: no endpoint\n", __func__);
1757 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1759 dev_err(dev, "%s: invalid lane configuration %d\n",
1764 /* Get panel node from the output port's endpoint data */
1765 device_node = of_graph_get_remote_node(np, 1, 0);
1767 dev_dbg(dev, "%s: no valid device\n", __func__);
1771 msm_host->device_node = device_node;
1773 if (of_property_read_bool(np, "syscon-sfpb")) {
1774 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1776 if (IS_ERR(msm_host->sfpb)) {
1777 dev_err(dev, "%s: failed to get sfpb regmap\n",
1779 ret = PTR_ERR(msm_host->sfpb);
1783 of_node_put(device_node);
1786 of_node_put(endpoint);
1791 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1793 struct platform_device *pdev = msm_host->pdev;
1794 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1795 struct resource *res;
1798 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1802 for (i = 0; i < cfg->num_dsi; i++) {
1803 if (cfg->io_start[i] == res->start)
1810 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1812 struct msm_dsi_host *msm_host = NULL;
1813 struct platform_device *pdev = msm_dsi->pdev;
1816 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1818 pr_err("%s: FAILED: cannot alloc dsi host\n",
1824 msm_host->pdev = pdev;
1825 msm_dsi->host = &msm_host->base;
1827 ret = dsi_host_parse_dt(msm_host);
1829 pr_err("%s: failed to parse dt\n", __func__);
1833 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1834 if (IS_ERR(msm_host->ctrl_base)) {
1835 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1836 ret = PTR_ERR(msm_host->ctrl_base);
1840 pm_runtime_enable(&pdev->dev);
1842 msm_host->cfg_hnd = dsi_get_config(msm_host);
1843 if (!msm_host->cfg_hnd) {
1845 pr_err("%s: get config failed\n", __func__);
1849 msm_host->id = dsi_host_get_id(msm_host);
1850 if (msm_host->id < 0) {
1852 pr_err("%s: unable to identify DSI host index\n", __func__);
1856 /* fixup base address by io offset */
1857 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1859 ret = dsi_regulator_init(msm_host);
1861 pr_err("%s: regulator init failed\n", __func__);
1865 ret = dsi_clk_init(msm_host);
1867 pr_err("%s: unable to initialize dsi clks\n", __func__);
1871 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1872 if (!msm_host->rx_buf) {
1874 pr_err("%s: alloc rx temp buf failed\n", __func__);
1878 init_completion(&msm_host->dma_comp);
1879 init_completion(&msm_host->video_comp);
1880 mutex_init(&msm_host->dev_mutex);
1881 mutex_init(&msm_host->cmd_mutex);
1882 spin_lock_init(&msm_host->intr_lock);
1884 /* setup workqueue */
1885 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1886 if (!msm_host->workqueue)
1889 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1890 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1892 msm_dsi->id = msm_host->id;
1894 DBG("Dsi Host %d initialized", msm_host->id);
1901 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1903 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1906 dsi_tx_buf_free(msm_host);
1907 if (msm_host->workqueue) {
1908 flush_workqueue(msm_host->workqueue);
1909 destroy_workqueue(msm_host->workqueue);
1910 msm_host->workqueue = NULL;
1913 mutex_destroy(&msm_host->cmd_mutex);
1914 mutex_destroy(&msm_host->dev_mutex);
1916 pm_runtime_disable(&msm_host->pdev->dev);
1919 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1920 struct drm_device *dev)
1922 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1923 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1924 struct platform_device *pdev = msm_host->pdev;
1927 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1928 if (msm_host->irq < 0) {
1929 ret = msm_host->irq;
1930 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1934 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1935 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1936 "dsi_isr", msm_host);
1938 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1939 msm_host->irq, ret);
1943 msm_host->dev = dev;
1944 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
1946 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1953 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1955 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1958 /* Register mipi dsi host */
1959 if (!msm_host->registered) {
1960 host->dev = &msm_host->pdev->dev;
1961 host->ops = &dsi_host_ops;
1962 ret = mipi_dsi_host_register(host);
1966 msm_host->registered = true;
1968 /* If the panel driver has not been probed after host register,
1969 * we should defer the host's probe.
1970 * It makes sure panel is connected when fbcon detects
1971 * connector status and gets the proper display mode to
1972 * create framebuffer.
1973 * Don't try to defer if there is nothing connected to the dsi
1976 if (check_defer && msm_host->device_node) {
1977 if (IS_ERR(of_drm_find_panel(msm_host->device_node)))
1978 if (!of_drm_find_bridge(msm_host->device_node))
1979 return -EPROBE_DEFER;
1986 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1988 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1990 if (msm_host->registered) {
1991 mipi_dsi_host_unregister(host);
1994 msm_host->registered = false;
1998 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1999 const struct mipi_dsi_msg *msg)
2001 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2002 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2004 /* TODO: make sure dsi_cmd_mdp is idle.
2005 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
2006 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
2007 * How to handle the old versions? Wait for mdp cmd done?
2011 * mdss interrupt is generated in mdp core clock domain
2012 * mdp clock need to be enabled to receive dsi interrupt
2014 pm_runtime_get_sync(&msm_host->pdev->dev);
2015 cfg_hnd->ops->link_clk_enable(msm_host);
2017 /* TODO: vote for bus bandwidth */
2019 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2020 dsi_set_tx_power_mode(0, msm_host);
2022 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2023 dsi_write(msm_host, REG_DSI_CTRL,
2024 msm_host->dma_cmd_ctrl_restore |
2025 DSI_CTRL_CMD_MODE_EN |
2027 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2032 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2033 const struct mipi_dsi_msg *msg)
2035 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2036 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2038 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2039 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2041 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2042 dsi_set_tx_power_mode(1, msm_host);
2044 /* TODO: unvote for bus bandwidth */
2046 cfg_hnd->ops->link_clk_disable(msm_host);
2047 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2050 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2051 const struct mipi_dsi_msg *msg)
2053 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2055 return dsi_cmds2buf_tx(msm_host, msg);
2058 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2059 const struct mipi_dsi_msg *msg)
2061 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2062 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2063 int data_byte, rx_byte, dlen, end;
2064 int short_response, diff, pkt_size, ret = 0;
2066 int rlen = msg->rx_len;
2075 data_byte = 10; /* first read */
2076 if (rlen < data_byte)
2079 pkt_size = data_byte;
2080 rx_byte = data_byte + 6; /* 4 header + 2 crc */
2083 buf = msm_host->rx_buf;
2086 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2087 struct mipi_dsi_msg max_pkt_size_msg = {
2088 .channel = msg->channel,
2089 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2094 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2095 rlen, pkt_size, rx_byte);
2097 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2099 pr_err("%s: Set max pkt size failed, %d\n",
2104 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2105 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2106 /* Clear the RDBK_DATA registers */
2107 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2108 DSI_RDBK_DATA_CTRL_CLR);
2109 wmb(); /* make sure the RDBK registers are cleared */
2110 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2111 wmb(); /* release cleared status before transfer */
2114 ret = dsi_cmds2buf_tx(msm_host, msg);
2116 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2118 } else if (ret < msg->tx_len) {
2119 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret);
2124 * once cmd_dma_done interrupt received,
2125 * return data from client is ready and stored
2126 * at RDBK_DATA register already
2127 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2128 * after that dcs header lost during shift into registers
2130 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2138 if (rlen <= data_byte) {
2139 diff = data_byte - rlen;
2147 dlen -= 2; /* 2 crc */
2149 buf += dlen; /* next start position */
2150 data_byte = 14; /* NOT first read */
2151 if (rlen < data_byte)
2154 pkt_size += data_byte;
2155 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2160 * For single Long read, if the requested rlen < 10,
2161 * we need to shift the start position of rx
2162 * data buffer to skip the bytes which are not
2165 if (pkt_size < 10 && !short_response)
2166 buf = msm_host->rx_buf + (10 - rlen);
2168 buf = msm_host->rx_buf;
2172 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2173 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2176 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2177 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2178 ret = dsi_short_read1_resp(buf, msg);
2180 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2181 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2182 ret = dsi_short_read2_resp(buf, msg);
2184 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2185 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2186 ret = dsi_long_read_resp(buf, msg);
2189 pr_warn("%s:Invalid response cmd\n", __func__);
2196 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2199 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2201 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2202 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2203 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2205 /* Make sure trigger happens */
2209 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2210 struct msm_dsi_pll *src_pll)
2212 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2213 struct clk *byte_clk_provider, *pixel_clk_provider;
2216 ret = msm_dsi_pll_get_clk_provider(src_pll,
2217 &byte_clk_provider, &pixel_clk_provider);
2219 pr_info("%s: can't get provider from pll, don't set parent\n",
2224 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2226 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2231 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2233 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2238 if (msm_host->dsi_clk_src) {
2239 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2241 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2247 if (msm_host->esc_clk_src) {
2248 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2250 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2260 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2262 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2265 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2266 /* Make sure fully reset */
2269 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2273 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2274 struct msm_dsi_phy_clk_request *clk_req,
2277 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2278 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2281 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi);
2283 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2287 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2288 clk_req->escclk_rate = msm_host->esc_clk_rate;
2291 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2293 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2295 dsi_op_mode_config(msm_host,
2296 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2298 /* TODO: clock should be turned off for command mode,
2299 * and only turned on before MDP START.
2300 * This part of code should be enabled once mdp driver support it.
2302 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2303 * dsi_link_clk_disable(msm_host);
2304 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2307 msm_host->enabled = true;
2311 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2313 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2315 msm_host->enabled = false;
2316 dsi_op_mode_config(msm_host,
2317 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2319 /* Since we have disabled INTF, the video engine won't stop so that
2320 * the cmd engine will be blocked.
2321 * Reset to disable video engine so that we can send off cmd.
2323 dsi_sw_reset(msm_host);
2328 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2330 enum sfpb_ahb_arb_master_port_en en;
2332 if (!msm_host->sfpb)
2335 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2337 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2338 SFPB_GPREG_MASTER_PORT_EN__MASK,
2339 SFPB_GPREG_MASTER_PORT_EN(en));
2342 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2343 struct msm_dsi_phy_shared_timings *phy_shared_timings,
2346 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2347 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2350 mutex_lock(&msm_host->dev_mutex);
2351 if (msm_host->power_on) {
2352 DBG("dsi host already on");
2356 msm_dsi_sfpb_config(msm_host, true);
2358 ret = dsi_host_regulator_enable(msm_host);
2360 pr_err("%s:Failed to enable vregs.ret=%d\n",
2365 pm_runtime_get_sync(&msm_host->pdev->dev);
2366 ret = cfg_hnd->ops->link_clk_enable(msm_host);
2368 pr_err("%s: failed to enable link clocks. ret=%d\n",
2370 goto fail_disable_reg;
2373 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2375 pr_err("%s: failed to set pinctrl default state, %d\n",
2377 goto fail_disable_clk;
2380 dsi_timing_setup(msm_host, is_dual_dsi);
2381 dsi_sw_reset(msm_host);
2382 dsi_ctrl_config(msm_host, true, phy_shared_timings);
2384 if (msm_host->disp_en_gpio)
2385 gpiod_set_value(msm_host->disp_en_gpio, 1);
2387 msm_host->power_on = true;
2388 mutex_unlock(&msm_host->dev_mutex);
2393 cfg_hnd->ops->link_clk_disable(msm_host);
2394 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2396 dsi_host_regulator_disable(msm_host);
2398 mutex_unlock(&msm_host->dev_mutex);
2402 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2404 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2405 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2407 mutex_lock(&msm_host->dev_mutex);
2408 if (!msm_host->power_on) {
2409 DBG("dsi host already off");
2413 dsi_ctrl_config(msm_host, false, NULL);
2415 if (msm_host->disp_en_gpio)
2416 gpiod_set_value(msm_host->disp_en_gpio, 0);
2418 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2420 cfg_hnd->ops->link_clk_disable(msm_host);
2421 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2423 dsi_host_regulator_disable(msm_host);
2425 msm_dsi_sfpb_config(msm_host, false);
2429 msm_host->power_on = false;
2432 mutex_unlock(&msm_host->dev_mutex);
2436 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2437 struct drm_display_mode *mode)
2439 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2441 if (msm_host->mode) {
2442 drm_mode_destroy(msm_host->dev, msm_host->mode);
2443 msm_host->mode = NULL;
2446 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2447 if (!msm_host->mode) {
2448 pr_err("%s: cannot duplicate mode\n", __func__);
2455 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2456 unsigned long *panel_flags)
2458 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2459 struct drm_panel *panel;
2461 panel = of_drm_find_panel(msm_host->device_node);
2463 *panel_flags = msm_host->mode_flags;
2468 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2470 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2472 return of_drm_find_bridge(msm_host->device_node);