drivers/gpu/drm/msm/dsi/mmss_cc.xml.h

   1 #ifndef MMSS_CC_XML
   2 #define MMSS_CC_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2017-05-17 13:21:27)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2017-05-17 13:21:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2017-05-17 13:21:27)
  14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2017-05-17 13:21:27)
  15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2017-05-17 13:21:27)
  16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  33004 bytes, from 2017-05-17 13:21:27)
  17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2017-05-17 13:21:27)
  18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2017-05-17 13:21:27)
  19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2017-05-17 13:21:27)
  20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  41799 bytes, from 2017-06-16 12:32:42)
  21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2017-05-17 13:21:27)
  22
  23 Copyright (C) 2013-2017 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26
  27 Permission is hereby granted, free of charge, to any person obtaining
  28 a copy of this software and associated documentation files (the
  29 "Software"), to deal in the Software without restriction, including
  30 without limitation the rights to use, copy, modify, merge, publish,
  31 distribute, sublicense, and/or sell copies of the Software, and to
  32 permit persons to whom the Software is furnished to do so, subject to
  33 the following conditions:
  34
  35 The above copyright notice and this permission notice (including the
  36 next paragraph) shall be included in all copies or substantial
  37 portions of the Software.
  38
  39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46 */
  47
  48
  49 enum mmss_cc_clk {
  50         CLK = 0,
  51         PCLK = 1,
  52 };
  53
  54 #define REG_MMSS_CC_AHB                                         0x00000008
  55
  56 static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
  57 {
  58         switch (idx) {
  59                 case CLK: return 0x0000004c;
  60                 case PCLK: return 0x00000130;
  61                 default: return INVALID_IDX(idx);
  62         }
  63 }
  64 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
  65
  66 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
  67 #define MMSS_CC_CLK_CC_CLK_EN                                   0x00000001
  68 #define MMSS_CC_CLK_CC_ROOT_EN                                  0x00000004
  69 #define MMSS_CC_CLK_CC_MND_EN                                   0x00000020
  70 #define MMSS_CC_CLK_CC_MND_MODE__MASK                           0x000000c0
  71 #define MMSS_CC_CLK_CC_MND_MODE__SHIFT                          6
  72 static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
  73 {
  74         return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
  75 }
  76 #define MMSS_CC_CLK_CC_PMXO_SEL__MASK                           0x00000300
  77 #define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT                          8
  78 static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
  79 {
  80         return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
  81 }
  82
  83 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
  84 #define MMSS_CC_CLK_MD_D__MASK                                  0x000000ff
  85 #define MMSS_CC_CLK_MD_D__SHIFT                                 0
  86 static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
  87 {
  88         return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
  89 }
  90 #define MMSS_CC_CLK_MD_M__MASK                                  0x0000ff00
  91 #define MMSS_CC_CLK_MD_M__SHIFT                                 8
  92 static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
  93 {
  94         return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
  95 }
  96
  97 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
  98 #define MMSS_CC_CLK_NS_SRC__MASK                                0x0000000f
  99 #define MMSS_CC_CLK_NS_SRC__SHIFT                               0
 100 static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
 101 {
 102         return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
 103 }
 104 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK                       0x00fff000
 105 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT                      12
 106 static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
 107 {
 108         return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
 109 }
 110 #define MMSS_CC_CLK_NS_VAL__MASK                                0xff000000
 111 #define MMSS_CC_CLK_NS_VAL__SHIFT                               24
 112 static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
 113 {
 114         return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
 115 }
 116
 117 #define REG_MMSS_CC_DSI2_PIXEL_CC                               0x00000094
 118
 119 #define REG_MMSS_CC_DSI2_PIXEL_NS                               0x000000e4
 120
 121 #define REG_MMSS_CC_DSI2_PIXEL_CC2                              0x00000264
 122
 123
 124 #endif /* MMSS_CC_XML */