2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/irqdomain.h>
18 #include <linux/irq.h>
24 * If needed, this can become more specific: something like struct mdp5_mdss,
25 * which contains a 'struct msm_mdss base' member.
28 struct drm_device *dev;
30 void __iomem *mmio, *vbif;
32 struct regulator *vdd;
36 struct clk *vsync_clk;
39 volatile unsigned long enabled_mask;
40 struct irq_domain *domain;
44 static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
46 msm_writel(data, mdss->mmio + reg);
49 static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
51 return msm_readl(mdss->mmio + reg);
54 static irqreturn_t mdss_irq(int irq, void *arg)
56 struct msm_mdss *mdss = arg;
59 intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
61 VERB("intr=%08x", intr);
64 irq_hw_number_t hwirq = fls(intr) - 1;
66 generic_handle_irq(irq_find_mapping(
67 mdss->irqcontroller.domain, hwirq));
68 intr &= ~(1 << hwirq);
75 * interrupt-controller implementation, so sub-blocks (MDP/HDMI/eDP/DSI/etc)
76 * can register to get their irq's delivered
79 #define VALID_IRQS (MDSS_HW_INTR_STATUS_INTR_MDP | \
80 MDSS_HW_INTR_STATUS_INTR_DSI0 | \
81 MDSS_HW_INTR_STATUS_INTR_DSI1 | \
82 MDSS_HW_INTR_STATUS_INTR_HDMI | \
83 MDSS_HW_INTR_STATUS_INTR_EDP)
85 static void mdss_hw_mask_irq(struct irq_data *irqd)
87 struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
89 smp_mb__before_atomic();
90 clear_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);
91 smp_mb__after_atomic();
94 static void mdss_hw_unmask_irq(struct irq_data *irqd)
96 struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
98 smp_mb__before_atomic();
99 set_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);
100 smp_mb__after_atomic();
103 static struct irq_chip mdss_hw_irq_chip = {
105 .irq_mask = mdss_hw_mask_irq,
106 .irq_unmask = mdss_hw_unmask_irq,
109 static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
110 irq_hw_number_t hwirq)
112 struct msm_mdss *mdss = d->host_data;
114 if (!(VALID_IRQS & (1 << hwirq)))
117 irq_set_chip_and_handler(irq, &mdss_hw_irq_chip, handle_level_irq);
118 irq_set_chip_data(irq, mdss);
123 static const struct irq_domain_ops mdss_hw_irqdomain_ops = {
124 .map = mdss_hw_irqdomain_map,
125 .xlate = irq_domain_xlate_onecell,
129 static int mdss_irq_domain_init(struct msm_mdss *mdss)
131 struct device *dev = mdss->dev->dev;
132 struct irq_domain *d;
134 d = irq_domain_add_linear(dev->of_node, 32, &mdss_hw_irqdomain_ops,
137 dev_err(dev, "mdss irq domain add failed\n");
141 mdss->irqcontroller.enabled_mask = 0;
142 mdss->irqcontroller.domain = d;
147 int msm_mdss_enable(struct msm_mdss *mdss)
151 clk_prepare_enable(mdss->ahb_clk);
153 clk_prepare_enable(mdss->axi_clk);
155 clk_prepare_enable(mdss->vsync_clk);
160 int msm_mdss_disable(struct msm_mdss *mdss)
165 clk_disable_unprepare(mdss->vsync_clk);
167 clk_disable_unprepare(mdss->axi_clk);
168 clk_disable_unprepare(mdss->ahb_clk);
173 static int msm_mdss_get_clocks(struct msm_mdss *mdss)
175 struct platform_device *pdev = to_platform_device(mdss->dev->dev);
177 mdss->ahb_clk = msm_clk_get(pdev, "iface");
178 if (IS_ERR(mdss->ahb_clk))
179 mdss->ahb_clk = NULL;
181 mdss->axi_clk = msm_clk_get(pdev, "bus");
182 if (IS_ERR(mdss->axi_clk))
183 mdss->axi_clk = NULL;
185 mdss->vsync_clk = msm_clk_get(pdev, "vsync");
186 if (IS_ERR(mdss->vsync_clk))
187 mdss->vsync_clk = NULL;
192 void msm_mdss_destroy(struct drm_device *dev)
194 struct msm_drm_private *priv = dev->dev_private;
195 struct msm_mdss *mdss = priv->mdss;
200 irq_domain_remove(mdss->irqcontroller.domain);
201 mdss->irqcontroller.domain = NULL;
203 regulator_disable(mdss->vdd);
205 pm_runtime_disable(dev->dev);
208 int msm_mdss_init(struct drm_device *dev)
210 struct platform_device *pdev = to_platform_device(dev->dev);
211 struct msm_drm_private *priv = dev->dev_private;
212 struct msm_mdss *mdss;
217 if (!of_device_is_compatible(dev->dev->of_node, "qcom,mdss"))
220 mdss = devm_kzalloc(dev->dev, sizeof(*mdss), GFP_KERNEL);
228 mdss->mmio = msm_ioremap(pdev, "mdss_phys", "MDSS");
229 if (IS_ERR(mdss->mmio)) {
230 ret = PTR_ERR(mdss->mmio);
234 mdss->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
235 if (IS_ERR(mdss->vbif)) {
236 ret = PTR_ERR(mdss->vbif);
240 ret = msm_mdss_get_clocks(mdss);
242 dev_err(dev->dev, "failed to get clocks: %d\n", ret);
246 /* Regulator to enable GDSCs in downstream kernels */
247 mdss->vdd = devm_regulator_get(dev->dev, "vdd");
248 if (IS_ERR(mdss->vdd)) {
249 ret = PTR_ERR(mdss->vdd);
253 ret = regulator_enable(mdss->vdd);
255 dev_err(dev->dev, "failed to enable regulator vdd: %d\n",
260 ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),
261 mdss_irq, 0, "mdss_isr", mdss);
263 dev_err(dev->dev, "failed to init irq: %d\n", ret);
267 ret = mdss_irq_domain_init(mdss);
269 dev_err(dev->dev, "failed to init sub-block irqs: %d\n", ret);
275 pm_runtime_enable(dev->dev);
279 regulator_disable(mdss->vdd);