drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c

   1 /*
   2  * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <drm/drm_print.h>
  20 #include "mdp5_kms.h"
  21
  22 struct mdp5_plane {
  23         struct drm_plane base;
  24
  25         uint32_t nformats;
  26         uint32_t formats[32];
  27 };
  28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
  29
  30 static int mdp5_plane_mode_set(struct drm_plane *plane,
  31                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  32                 struct drm_rect *src, struct drm_rect *dest);
  33
  34 static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
  35                 struct drm_crtc *crtc,
  36                 struct drm_framebuffer *fb,
  37                 int crtc_x, int crtc_y,
  38                 unsigned int crtc_w, unsigned int crtc_h,
  39                 uint32_t src_x, uint32_t src_y,
  40                 uint32_t src_w, uint32_t src_h,
  41                 struct drm_modeset_acquire_ctx *ctx);
  42
  43 static struct mdp5_kms *get_kms(struct drm_plane *plane)
  44 {
  45         struct msm_drm_private *priv = plane->dev->dev_private;
  46         return to_mdp5_kms(to_mdp_kms(priv->kms));
  47 }
  48
  49 static bool plane_enabled(struct drm_plane_state *state)
  50 {
  51         return state->visible;
  52 }
  53
  54 static void mdp5_plane_destroy(struct drm_plane *plane)
  55 {
  56         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
  57
  58         drm_plane_helper_disable(plane);
  59         drm_plane_cleanup(plane);
  60
  61         kfree(mdp5_plane);
  62 }
  63
  64 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
  65                 struct drm_plane *plane)
  66 {
  67         drm_plane_create_rotation_property(plane,
  68                                            DRM_MODE_ROTATE_0,
  69                                            DRM_MODE_ROTATE_0 |
  70                                            DRM_MODE_ROTATE_180 |
  71                                            DRM_MODE_REFLECT_X |
  72                                            DRM_MODE_REFLECT_Y);
  73 }
  74
  75 /* helper to install properties which are common to planes and crtcs */
  76 static void mdp5_plane_install_properties(struct drm_plane *plane,
  77                 struct drm_mode_object *obj)
  78 {
  79         struct drm_device *dev = plane->dev;
  80         struct msm_drm_private *dev_priv = dev->dev_private;
  81         struct drm_property *prop;
  82
  83 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
  84                 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
  85                 if (!prop) { \
  86                         prop = drm_property_##fnc(dev, 0, #name, \
  87                                 ##__VA_ARGS__); \
  88                         if (!prop) { \
  89                                 dev_warn(dev->dev, \
  90                                         "Create property %s failed\n", \
  91                                         #name); \
  92                                 return; \
  93                         } \
  94                         dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
  95                 } \
  96                 drm_object_attach_property(&plane->base, prop, init_val); \
  97         } while (0)
  98
  99 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
 100                 INSTALL_PROPERTY(name, NAME, init_val, \
 101                                 create_range, min, max)
 102
 103 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
 104                 INSTALL_PROPERTY(name, NAME, init_val, \
 105                                 create_enum, name##_prop_enum_list, \
 106                                 ARRAY_SIZE(name##_prop_enum_list))
 107
 108         INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
 109
 110         mdp5_plane_install_rotation_property(dev, plane);
 111
 112 #undef INSTALL_RANGE_PROPERTY
 113 #undef INSTALL_ENUM_PROPERTY
 114 #undef INSTALL_PROPERTY
 115 }
 116
 117 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
 118                 struct drm_plane_state *state, struct drm_property *property,
 119                 uint64_t val)
 120 {
 121         struct drm_device *dev = plane->dev;
 122         struct mdp5_plane_state *pstate;
 123         struct msm_drm_private *dev_priv = dev->dev_private;
 124         int ret = 0;
 125
 126         pstate = to_mdp5_plane_state(state);
 127
 128 #define SET_PROPERTY(name, NAME, type) do { \
 129                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 130                         pstate->name = (type)val; \
 131                         DBG("Set property %s %d", #name, (type)val); \
 132                         goto done; \
 133                 } \
 134         } while (0)
 135
 136         SET_PROPERTY(zpos, ZPOS, uint8_t);
 137
 138         dev_err(dev->dev, "Invalid property\n");
 139         ret = -EINVAL;
 140 done:
 141         return ret;
 142 #undef SET_PROPERTY
 143 }
 144
 145 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
 146                 const struct drm_plane_state *state,
 147                 struct drm_property *property, uint64_t *val)
 148 {
 149         struct drm_device *dev = plane->dev;
 150         struct mdp5_plane_state *pstate;
 151         struct msm_drm_private *dev_priv = dev->dev_private;
 152         int ret = 0;
 153
 154         pstate = to_mdp5_plane_state(state);
 155
 156 #define GET_PROPERTY(name, NAME, type) do { \
 157                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 158                         *val = pstate->name; \
 159                         DBG("Get property %s %lld", #name, *val); \
 160                         goto done; \
 161                 } \
 162         } while (0)
 163
 164         GET_PROPERTY(zpos, ZPOS, uint8_t);
 165
 166         dev_err(dev->dev, "Invalid property\n");
 167         ret = -EINVAL;
 168 done:
 169         return ret;
 170 #undef SET_PROPERTY
 171 }
 172
 173 static void
 174 mdp5_plane_atomic_print_state(struct drm_printer *p,
 175                 const struct drm_plane_state *state)
 176 {
 177         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 178         struct mdp5_kms *mdp5_kms = get_kms(state->plane);
 179
 180         drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
 181                         pstate->hwpipe->name : "(null)");
 182         if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
 183                 drm_printf(p, "\tright-hwpipe=%s\n",
 184                            pstate->r_hwpipe ? pstate->r_hwpipe->name :
 185                                               "(null)");
 186         drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
 187         drm_printf(p, "\tzpos=%u\n", pstate->zpos);
 188         drm_printf(p, "\talpha=%u\n", pstate->alpha);
 189         drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
 190 }
 191
 192 static void mdp5_plane_reset(struct drm_plane *plane)
 193 {
 194         struct mdp5_plane_state *mdp5_state;
 195
 196         if (plane->state && plane->state->fb)
 197                 drm_framebuffer_unreference(plane->state->fb);
 198
 199         kfree(to_mdp5_plane_state(plane->state));
 200         plane->state = NULL;
 201         mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
 202         if (!mdp5_state)
 203                 return;
 204
 205         /* assign default blend parameters */
 206         mdp5_state->alpha = 255;
 207         mdp5_state->premultiplied = 0;
 208
 209         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 210                 mdp5_state->zpos = STAGE_BASE;
 211         else
 212                 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
 213
 214         mdp5_state->base.plane = plane;
 215
 216         plane->state = &mdp5_state->base;
 217 }
 218
 219 static struct drm_plane_state *
 220 mdp5_plane_duplicate_state(struct drm_plane *plane)
 221 {
 222         struct mdp5_plane_state *mdp5_state;
 223
 224         if (WARN_ON(!plane->state))
 225                 return NULL;
 226
 227         mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 228                         sizeof(*mdp5_state), GFP_KERNEL);
 229         if (!mdp5_state)
 230                 return NULL;
 231
 232         __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
 233
 234         return &mdp5_state->base;
 235 }
 236
 237 static void mdp5_plane_destroy_state(struct drm_plane *plane,
 238                 struct drm_plane_state *state)
 239 {
 240         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 241
 242         if (state->fb)
 243                 drm_framebuffer_unreference(state->fb);
 244
 245         kfree(pstate);
 246 }
 247
 248 static const struct drm_plane_funcs mdp5_plane_funcs = {
 249                 .update_plane = drm_atomic_helper_update_plane,
 250                 .disable_plane = drm_atomic_helper_disable_plane,
 251                 .destroy = mdp5_plane_destroy,
 252                 .atomic_set_property = mdp5_plane_atomic_set_property,
 253                 .atomic_get_property = mdp5_plane_atomic_get_property,
 254                 .reset = mdp5_plane_reset,
 255                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 256                 .atomic_destroy_state = mdp5_plane_destroy_state,
 257                 .atomic_print_state = mdp5_plane_atomic_print_state,
 258 };
 259
 260 static const struct drm_plane_funcs mdp5_cursor_plane_funcs = {
 261                 .update_plane = mdp5_update_cursor_plane_legacy,
 262                 .disable_plane = drm_atomic_helper_disable_plane,
 263                 .destroy = mdp5_plane_destroy,
 264                 .atomic_set_property = mdp5_plane_atomic_set_property,
 265                 .atomic_get_property = mdp5_plane_atomic_get_property,
 266                 .reset = mdp5_plane_reset,
 267                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 268                 .atomic_destroy_state = mdp5_plane_destroy_state,
 269                 .atomic_print_state = mdp5_plane_atomic_print_state,
 270 };
 271
 272 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
 273                                  struct drm_plane_state *new_state)
 274 {
 275         struct mdp5_kms *mdp5_kms = get_kms(plane);
 276         struct msm_kms *kms = &mdp5_kms->base.base;
 277         struct drm_framebuffer *fb = new_state->fb;
 278
 279         if (!new_state->fb)
 280                 return 0;
 281
 282         DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
 283         return msm_framebuffer_prepare(fb, kms->aspace);
 284 }
 285
 286 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
 287                                   struct drm_plane_state *old_state)
 288 {
 289         struct mdp5_kms *mdp5_kms = get_kms(plane);
 290         struct msm_kms *kms = &mdp5_kms->base.base;
 291         struct drm_framebuffer *fb = old_state->fb;
 292
 293         if (!fb)
 294                 return;
 295
 296         DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
 297         msm_framebuffer_cleanup(fb, kms->aspace);
 298 }
 299
 300 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
 301 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
 302                                               struct drm_plane_state *state)
 303 {
 304         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 305         struct drm_plane *plane = state->plane;
 306         struct drm_plane_state *old_state = plane->state;
 307         struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
 308         bool new_hwpipe = false;
 309         bool need_right_hwpipe = false;
 310         uint32_t max_width, max_height;
 311         bool out_of_bounds = false;
 312         uint32_t caps = 0;
 313         struct drm_rect clip;
 314         int min_scale, max_scale;
 315         int ret;
 316
 317         DBG("%s: check (%d -> %d)", plane->name,
 318                         plane_enabled(old_state), plane_enabled(state));
 319
 320         max_width = config->hw->lm.max_width << 16;
 321         max_height = config->hw->lm.max_height << 16;
 322
 323         /* Make sure source dimensions are within bounds. */
 324         if (state->src_h > max_height)
 325                 out_of_bounds = true;
 326
 327         if (state->src_w > max_width) {
 328                 /* If source split is supported, we can go up to 2x
 329                  * the max LM width, but we'd need to stage another
 330                  * hwpipe to the right LM. So, the drm_plane would
 331                  * consist of 2 hwpipes.
 332                  */
 333                 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
 334                     (state->src_w <= 2 * max_width))
 335                         need_right_hwpipe = true;
 336                 else
 337                         out_of_bounds = true;
 338         }
 339
 340         if (out_of_bounds) {
 341                 struct drm_rect src = drm_plane_state_src(state);
 342                 DBG("Invalid source size "DRM_RECT_FP_FMT,
 343                                 DRM_RECT_FP_ARG(&src));
 344                 return -ERANGE;
 345         }
 346
 347         clip.x1 = 0;
 348         clip.y1 = 0;
 349         clip.x2 = crtc_state->adjusted_mode.hdisplay;
 350         clip.y2 = crtc_state->adjusted_mode.vdisplay;
 351         min_scale = FRAC_16_16(1, 8);
 352         max_scale = FRAC_16_16(8, 1);
 353
 354         ret = drm_plane_helper_check_state(state, &clip, min_scale,
 355                                            max_scale, true, true);
 356         if (ret)
 357                 return ret;
 358
 359         if (plane_enabled(state)) {
 360                 unsigned int rotation;
 361                 const struct mdp_format *format;
 362                 struct mdp5_kms *mdp5_kms = get_kms(plane);
 363                 uint32_t blkcfg = 0;
 364
 365                 format = to_mdp_format(msm_framebuffer_format(state->fb));
 366                 if (MDP_FORMAT_IS_YUV(format))
 367                         caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 368
 369                 if (((state->src_w >> 16) != state->crtc_w) ||
 370                                 ((state->src_h >> 16) != state->crtc_h))
 371                         caps |= MDP_PIPE_CAP_SCALE;
 372
 373                 rotation = drm_rotation_simplify(state->rotation,
 374                                                  DRM_MODE_ROTATE_0 |
 375                                                  DRM_MODE_REFLECT_X |
 376                                                  DRM_MODE_REFLECT_Y);
 377
 378                 if (rotation & DRM_MODE_REFLECT_X)
 379                         caps |= MDP_PIPE_CAP_HFLIP;
 380
 381                 if (rotation & DRM_MODE_REFLECT_Y)
 382                         caps |= MDP_PIPE_CAP_VFLIP;
 383
 384                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 385                         caps |= MDP_PIPE_CAP_CURSOR;
 386
 387                 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
 388                 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
 389                         new_hwpipe = true;
 390
 391                 /*
 392                  * (re)allocte hw pipe if we're either requesting for 2 hw pipes
 393                  * or we're switching from 2 hw pipes to 1 hw pipe because the
 394                  * new src_w can be supported by 1 hw pipe itself.
 395                  */
 396                 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
 397                     (!need_right_hwpipe && mdp5_state->r_hwpipe))
 398                         new_hwpipe = true;
 399
 400                 if (mdp5_kms->smp) {
 401                         const struct mdp_format *format =
 402                                 to_mdp_format(msm_framebuffer_format(state->fb));
 403
 404                         blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
 405                                         state->src_w >> 16, false);
 406
 407                         if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
 408                                 new_hwpipe = true;
 409                 }
 410
 411                 /* (re)assign hwpipe if needed, otherwise keep old one: */
 412                 if (new_hwpipe) {
 413                         /* TODO maybe we want to re-assign hwpipe sometimes
 414                          * in cases when we no-longer need some caps to make
 415                          * it available for other planes?
 416                          */
 417                         struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
 418                         struct mdp5_hw_pipe *old_right_hwpipe =
 419                                                           mdp5_state->r_hwpipe;
 420
 421                         mdp5_state->hwpipe = mdp5_pipe_assign(state->state,
 422                                         plane, caps, blkcfg);
 423                         if (IS_ERR(mdp5_state->hwpipe)) {
 424                                 DBG("%s: failed to assign hwpipe!", plane->name);
 425                                 return PTR_ERR(mdp5_state->hwpipe);
 426                         }
 427
 428                         if (need_right_hwpipe) {
 429                                 mdp5_state->r_hwpipe =
 430                                         mdp5_pipe_assign(state->state, plane,
 431                                                          caps, blkcfg);
 432                                 if (IS_ERR(mdp5_state->r_hwpipe)) {
 433                                         DBG("%s: failed to assign right hwpipe",
 434                                             plane->name);
 435                                         return PTR_ERR(mdp5_state->r_hwpipe);
 436                                 }
 437                         } else {
 438                                 /*
 439                                  * set it to NULL so that the driver knows we
 440                                  * don't have a right hwpipe when committing a
 441                                  * new state
 442                                  */
 443                                 mdp5_state->r_hwpipe = NULL;
 444                         }
 445
 446                         mdp5_pipe_release(state->state, old_hwpipe);
 447                         mdp5_pipe_release(state->state, old_right_hwpipe);
 448                 }
 449         } else {
 450                 mdp5_pipe_release(state->state, mdp5_state->hwpipe);
 451                 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
 452                 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int mdp5_plane_atomic_check(struct drm_plane *plane,
 459                                    struct drm_plane_state *state)
 460 {
 461         struct drm_crtc *crtc;
 462         struct drm_crtc_state *crtc_state;
 463
 464         crtc = state->crtc ? state->crtc : plane->state->crtc;
 465         if (!crtc)
 466                 return 0;
 467
 468         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 469         if (WARN_ON(!crtc_state))
 470                 return -EINVAL;
 471
 472         return mdp5_plane_atomic_check_with_state(crtc_state, state);
 473 }
 474
 475 static void mdp5_plane_atomic_update(struct drm_plane *plane,
 476                                      struct drm_plane_state *old_state)
 477 {
 478         struct drm_plane_state *state = plane->state;
 479
 480         DBG("%s: update", plane->name);
 481
 482         if (plane_enabled(state)) {
 483                 int ret;
 484
 485                 ret = mdp5_plane_mode_set(plane,
 486                                 state->crtc, state->fb,
 487                                 &state->src, &state->dst);
 488                 /* atomic_check should have ensured that this doesn't fail */
 489                 WARN_ON(ret < 0);
 490         }
 491 }
 492
 493 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
 494                 .prepare_fb = mdp5_plane_prepare_fb,
 495                 .cleanup_fb = mdp5_plane_cleanup_fb,
 496                 .atomic_check = mdp5_plane_atomic_check,
 497                 .atomic_update = mdp5_plane_atomic_update,
 498 };
 499
 500 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
 501                                enum mdp5_pipe pipe,
 502                                struct drm_framebuffer *fb)
 503 {
 504         struct msm_kms *kms = &mdp5_kms->base.base;
 505
 506         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
 507                         MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 508                         MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 509
 510         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
 511                         MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 512                         MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 513
 514         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
 515                         msm_framebuffer_iova(fb, kms->aspace, 0));
 516         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
 517                         msm_framebuffer_iova(fb, kms->aspace, 1));
 518         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
 519                         msm_framebuffer_iova(fb, kms->aspace, 2));
 520         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
 521                         msm_framebuffer_iova(fb, kms->aspace, 3));
 522 }
 523
 524 /* Note: mdp5_plane->pipe_lock must be locked */
 525 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
 526 {
 527         uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
 528                          ~MDP5_PIPE_OP_MODE_CSC_1_EN;
 529
 530         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
 531 }
 532
 533 /* Note: mdp5_plane->pipe_lock must be locked */
 534 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 535                 struct csc_cfg *csc)
 536 {
 537         uint32_t  i, mode = 0; /* RGB, no CSC */
 538         uint32_t *matrix;
 539
 540         if (unlikely(!csc))
 541                 return;
 542
 543         if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
 544                 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
 545         if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
 546                 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
 547         mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
 548         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
 549
 550         matrix = csc->matrix;
 551         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
 552                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
 553                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
 554         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
 555                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
 556                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
 557         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
 558                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
 559                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
 560         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
 561                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
 562                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
 563         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
 564                         MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
 565
 566         for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
 567                 uint32_t *pre_clamp = csc->pre_clamp;
 568                 uint32_t *post_clamp = csc->post_clamp;
 569
 570                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
 571                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
 572                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
 573
 574                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
 575                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
 576                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
 577
 578                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
 579                         MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
 580
 581                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
 582                         MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
 583         }
 584 }
 585
 586 #define PHASE_STEP_SHIFT        21
 587 #define DOWN_SCALE_RATIO_MAX    32      /* 2^(26-21) */
 588
 589 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
 590 {
 591         uint32_t unit;
 592
 593         if (src == 0 || dst == 0)
 594                 return -EINVAL;
 595
 596         /*
 597          * PHASE_STEP_X/Y is coded on 26 bits (25:0),
 598          * where 2^21 represents the unity "1" in fixed-point hardware design.
 599          * This leaves 5 bits for the integer part (downscale case):
 600          *      -> maximum downscale ratio = 0b1_1111 = 31
 601          */
 602         if (src > (dst * DOWN_SCALE_RATIO_MAX))
 603                 return -EOVERFLOW;
 604
 605         unit = 1 << PHASE_STEP_SHIFT;
 606         *out_phase = mult_frac(unit, src, dst);
 607
 608         return 0;
 609 }
 610
 611 static int calc_scalex_steps(struct drm_plane *plane,
 612                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 613                 uint32_t phasex_steps[COMP_MAX])
 614 {
 615         struct mdp5_kms *mdp5_kms = get_kms(plane);
 616         struct device *dev = mdp5_kms->dev->dev;
 617         uint32_t phasex_step;
 618         unsigned int hsub;
 619         int ret;
 620
 621         ret = calc_phase_step(src, dest, &phasex_step);
 622         if (ret) {
 623                 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
 624                 return ret;
 625         }
 626
 627         hsub = drm_format_horz_chroma_subsampling(pixel_format);
 628
 629         phasex_steps[COMP_0]   = phasex_step;
 630         phasex_steps[COMP_3]   = phasex_step;
 631         phasex_steps[COMP_1_2] = phasex_step / hsub;
 632
 633         return 0;
 634 }
 635
 636 static int calc_scaley_steps(struct drm_plane *plane,
 637                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 638                 uint32_t phasey_steps[COMP_MAX])
 639 {
 640         struct mdp5_kms *mdp5_kms = get_kms(plane);
 641         struct device *dev = mdp5_kms->dev->dev;
 642         uint32_t phasey_step;
 643         unsigned int vsub;
 644         int ret;
 645
 646         ret = calc_phase_step(src, dest, &phasey_step);
 647         if (ret) {
 648                 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
 649                 return ret;
 650         }
 651
 652         vsub = drm_format_vert_chroma_subsampling(pixel_format);
 653
 654         phasey_steps[COMP_0]   = phasey_step;
 655         phasey_steps[COMP_3]   = phasey_step;
 656         phasey_steps[COMP_1_2] = phasey_step / vsub;
 657
 658         return 0;
 659 }
 660
 661 static uint32_t get_scale_config(const struct mdp_format *format,
 662                 uint32_t src, uint32_t dst, bool horz)
 663 {
 664         bool scaling = format->is_yuv ? true : (src != dst);
 665         uint32_t sub, pix_fmt = format->base.pixel_format;
 666         uint32_t ya_filter, uv_filter;
 667         bool yuv = format->is_yuv;
 668
 669         if (!scaling)
 670                 return 0;
 671
 672         if (yuv) {
 673                 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
 674                              drm_format_vert_chroma_subsampling(pix_fmt);
 675                 uv_filter = ((src / sub) <= dst) ?
 676                                    SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 677         }
 678         ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 679
 680         if (horz)
 681                 return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
 682                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
 683                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
 684                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
 685         else
 686                 return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
 687                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
 688                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
 689                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
 690 }
 691
 692 static void calc_pixel_ext(const struct mdp_format *format,
 693                 uint32_t src, uint32_t dst, uint32_t phase_step[2],
 694                 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
 695                 bool horz)
 696 {
 697         bool scaling = format->is_yuv ? true : (src != dst);
 698         int i;
 699
 700         /*
 701          * Note:
 702          * We assume here that:
 703          *     1. PCMN filter is used for downscale
 704          *     2. bilinear filter is used for upscale
 705          *     3. we are in a single pipe configuration
 706          */
 707
 708         for (i = 0; i < COMP_MAX; i++) {
 709                 pix_ext_edge1[i] = 0;
 710                 pix_ext_edge2[i] = scaling ? 1 : 0;
 711         }
 712 }
 713
 714 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 715         const struct mdp_format *format,
 716         uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
 717         uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
 718 {
 719         uint32_t pix_fmt = format->base.pixel_format;
 720         uint32_t lr, tb, req;
 721         int i;
 722
 723         for (i = 0; i < COMP_MAX; i++) {
 724                 uint32_t roi_w = src_w;
 725                 uint32_t roi_h = src_h;
 726
 727                 if (format->is_yuv && i == COMP_1_2) {
 728                         roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
 729                         roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
 730                 }
 731
 732                 lr  = (pe_left[i] >= 0) ?
 733                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
 734                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
 735
 736                 lr |= (pe_right[i] >= 0) ?
 737                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
 738                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
 739
 740                 tb  = (pe_top[i] >= 0) ?
 741                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
 742                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
 743
 744                 tb |= (pe_bottom[i] >= 0) ?
 745                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
 746                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
 747
 748                 req  = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
 749                                 pe_left[i] + pe_right[i]);
 750
 751                 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
 752                                 pe_top[i] + pe_bottom[i]);
 753
 754                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
 755                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
 756                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
 757
 758                 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 759                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
 760                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
 761                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
 762                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
 763                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
 764
 765                 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 766                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
 767                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
 768                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
 769                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
 770                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
 771         }
 772 }
 773
 774 struct pixel_ext {
 775         int left[COMP_MAX];
 776         int right[COMP_MAX];
 777         int top[COMP_MAX];
 778         int bottom[COMP_MAX];
 779 };
 780
 781 struct phase_step {
 782         u32 x[COMP_MAX];
 783         u32 y[COMP_MAX];
 784 };
 785
 786 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
 787                                  struct mdp5_hw_pipe *hwpipe,
 788                                  struct drm_framebuffer *fb,
 789                                  struct phase_step *step,
 790                                  struct pixel_ext *pe,
 791                                  u32 scale_config, u32 hdecm, u32 vdecm,
 792                                  bool hflip, bool vflip,
 793                                  int crtc_x, int crtc_y,
 794                                  unsigned int crtc_w, unsigned int crtc_h,
 795                                  u32 src_img_w, u32 src_img_h,
 796                                  u32 src_x, u32 src_y,
 797                                  u32 src_w, u32 src_h)
 798 {
 799         enum mdp5_pipe pipe = hwpipe->pipe;
 800         bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
 801         const struct mdp_format *format =
 802                         to_mdp_format(msm_framebuffer_format(fb));
 803
 804         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
 805                         MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
 806                         MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
 807
 808         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
 809                         MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
 810                         MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
 811
 812         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
 813                         MDP5_PIPE_SRC_XY_X(src_x) |
 814                         MDP5_PIPE_SRC_XY_Y(src_y));
 815
 816         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
 817                         MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
 818                         MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
 819
 820         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
 821                         MDP5_PIPE_OUT_XY_X(crtc_x) |
 822                         MDP5_PIPE_OUT_XY_Y(crtc_y));
 823
 824         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
 825                         MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 826                         MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 827                         MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 828                         MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 829                         COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 830                         MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 831                         MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 832                         COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
 833                         MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
 834                         MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
 835
 836         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
 837                         MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 838                         MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 839                         MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 840                         MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 841
 842         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
 843                         (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
 844                         (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
 845                         COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
 846                         MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
 847
 848         /* not using secure mode: */
 849         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
 850
 851         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
 852                 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
 853                                 src_w, pe->left, pe->right,
 854                                 src_h, pe->top, pe->bottom);
 855
 856         if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
 857                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
 858                                 step->x[COMP_0]);
 859                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
 860                                 step->y[COMP_0]);
 861                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
 862                                 step->x[COMP_1_2]);
 863                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
 864                                 step->y[COMP_1_2]);
 865                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
 866                                 MDP5_PIPE_DECIMATION_VERT(vdecm) |
 867                                 MDP5_PIPE_DECIMATION_HORZ(hdecm));
 868                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
 869                            scale_config);
 870         }
 871
 872         if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
 873                 if (MDP_FORMAT_IS_YUV(format))
 874                         csc_enable(mdp5_kms, pipe,
 875                                         mdp_get_default_csc_cfg(CSC_YUV2RGB));
 876                 else
 877                         csc_disable(mdp5_kms, pipe);
 878         }
 879
 880         set_scanout_locked(mdp5_kms, pipe, fb);
 881 }
 882
 883 static int mdp5_plane_mode_set(struct drm_plane *plane,
 884                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 885                 struct drm_rect *src, struct drm_rect *dest)
 886 {
 887         struct drm_plane_state *pstate = plane->state;
 888         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
 889         struct mdp5_kms *mdp5_kms = get_kms(plane);
 890         enum mdp5_pipe pipe = hwpipe->pipe;
 891         struct mdp5_hw_pipe *right_hwpipe;
 892         const struct mdp_format *format;
 893         uint32_t nplanes, config = 0;
 894         struct phase_step step = { { 0 } };
 895         struct pixel_ext pe = { { 0 } };
 896         uint32_t hdecm = 0, vdecm = 0;
 897         uint32_t pix_format;
 898         unsigned int rotation;
 899         bool vflip, hflip;
 900         int crtc_x, crtc_y;
 901         unsigned int crtc_w, crtc_h;
 902         uint32_t src_x, src_y;
 903         uint32_t src_w, src_h;
 904         uint32_t src_img_w, src_img_h;
 905         uint32_t src_x_r;
 906         int crtc_x_r;
 907         int ret;
 908
 909         nplanes = fb->format->num_planes;
 910
 911         /* bad formats should already be rejected: */
 912         if (WARN_ON(nplanes > pipe2nclients(pipe)))
 913                 return -EINVAL;
 914
 915         format = to_mdp_format(msm_framebuffer_format(fb));
 916         pix_format = format->base.pixel_format;
 917
 918         src_x = src->x1;
 919         src_y = src->y1;
 920         src_w = drm_rect_width(src);
 921         src_h = drm_rect_height(src);
 922
 923         crtc_x = dest->x1;
 924         crtc_y = dest->y1;
 925         crtc_w = drm_rect_width(dest);
 926         crtc_h = drm_rect_height(dest);
 927
 928         /* src values are in Q16 fixed point, convert to integer: */
 929         src_x = src_x >> 16;
 930         src_y = src_y >> 16;
 931         src_w = src_w >> 16;
 932         src_h = src_h >> 16;
 933
 934         src_img_w = min(fb->width, src_w);
 935         src_img_h = min(fb->height, src_h);
 936
 937         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
 938                         fb->base.id, src_x, src_y, src_w, src_h,
 939                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 940
 941         right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
 942         if (right_hwpipe) {
 943                 /*
 944                  * if the plane comprises of 2 hw pipes, assume that the width
 945                  * is split equally across them. The only parameters that varies
 946                  * between the 2 pipes are src_x and crtc_x
 947                  */
 948                 crtc_w /= 2;
 949                 src_w /= 2;
 950                 src_img_w /= 2;
 951
 952                 crtc_x_r = crtc_x + crtc_w;
 953                 src_x_r = src_x + src_w;
 954         }
 955
 956         ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
 957         if (ret)
 958                 return ret;
 959
 960         ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
 961         if (ret)
 962                 return ret;
 963
 964         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
 965                 calc_pixel_ext(format, src_w, crtc_w, step.x,
 966                                pe.left, pe.right, true);
 967                 calc_pixel_ext(format, src_h, crtc_h, step.y,
 968                                pe.top, pe.bottom, false);
 969         }
 970
 971         /* TODO calc hdecm, vdecm */
 972
 973         /* SCALE is used to both scale and up-sample chroma components */
 974         config |= get_scale_config(format, src_w, crtc_w, true);
 975         config |= get_scale_config(format, src_h, crtc_h, false);
 976         DBG("scale config = %x", config);
 977
 978         rotation = drm_rotation_simplify(pstate->rotation,
 979                                          DRM_MODE_ROTATE_0 |
 980                                          DRM_MODE_REFLECT_X |
 981                                          DRM_MODE_REFLECT_Y);
 982         hflip = !!(rotation & DRM_MODE_REFLECT_X);
 983         vflip = !!(rotation & DRM_MODE_REFLECT_Y);
 984
 985         mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
 986                              config, hdecm, vdecm, hflip, vflip,
 987                              crtc_x, crtc_y, crtc_w, crtc_h,
 988                              src_img_w, src_img_h,
 989                              src_x, src_y, src_w, src_h);
 990         if (right_hwpipe)
 991                 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
 992                                      config, hdecm, vdecm, hflip, vflip,
 993                                      crtc_x_r, crtc_y, crtc_w, crtc_h,
 994                                      src_img_w, src_img_h,
 995                                      src_x_r, src_y, src_w, src_h);
 996
 997         plane->fb = fb;
 998
 999         return ret;
1000 }
1001
1002 static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
1003                         struct drm_crtc *crtc, struct drm_framebuffer *fb,
1004                         int crtc_x, int crtc_y,
1005                         unsigned int crtc_w, unsigned int crtc_h,
1006                         uint32_t src_x, uint32_t src_y,
1007                         uint32_t src_w, uint32_t src_h,
1008                         struct drm_modeset_acquire_ctx *ctx)
1009 {
1010         struct drm_plane_state *plane_state, *new_plane_state;
1011         struct mdp5_plane_state *mdp5_pstate;
1012         struct drm_crtc_state *crtc_state = crtc->state;
1013         int ret;
1014
1015         if (!crtc_state->active || drm_atomic_crtc_needs_modeset(crtc_state))
1016                 goto slow;
1017
1018         plane_state = plane->state;
1019         mdp5_pstate = to_mdp5_plane_state(plane_state);
1020
1021         /* don't use fast path if we don't have a hwpipe allocated yet */
1022         if (!mdp5_pstate->hwpipe)
1023                 goto slow;
1024
1025         /* only allow changing of position(crtc x/y or src x/y) in fast path */
1026         if (plane_state->crtc != crtc ||
1027             plane_state->src_w != src_w ||
1028             plane_state->src_h != src_h ||
1029             plane_state->crtc_w != crtc_w ||
1030             plane_state->crtc_h != crtc_h ||
1031             !plane_state->fb ||
1032             plane_state->fb != fb)
1033                 goto slow;
1034
1035         new_plane_state = mdp5_plane_duplicate_state(plane);
1036         if (!new_plane_state)
1037                 return -ENOMEM;
1038
1039         new_plane_state->src_x = src_x;
1040         new_plane_state->src_y = src_y;
1041         new_plane_state->src_w = src_w;
1042         new_plane_state->src_h = src_h;
1043         new_plane_state->crtc_x = crtc_x;
1044         new_plane_state->crtc_y = crtc_y;
1045         new_plane_state->crtc_w = crtc_w;
1046         new_plane_state->crtc_h = crtc_h;
1047
1048         ret = mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);
1049         if (ret)
1050                 goto slow_free;
1051
1052         if (new_plane_state->visible) {
1053                 struct mdp5_ctl *ctl;
1054                 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(crtc);
1055
1056                 ret = mdp5_plane_mode_set(plane, crtc, fb,
1057                                           &new_plane_state->src,
1058                                           &new_plane_state->dst);
1059                 WARN_ON(ret < 0);
1060
1061                 ctl = mdp5_crtc_get_ctl(crtc);
1062
1063                 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane));
1064         }
1065
1066         *to_mdp5_plane_state(plane_state) =
1067                 *to_mdp5_plane_state(new_plane_state);
1068
1069         mdp5_plane_destroy_state(plane, new_plane_state);
1070
1071         return 0;
1072 slow_free:
1073         mdp5_plane_destroy_state(plane, new_plane_state);
1074 slow:
1075         return drm_atomic_helper_update_plane(plane, crtc, fb,
1076                                               crtc_x, crtc_y, crtc_w, crtc_h,
1077                                               src_x, src_y, src_w, src_h, ctx);
1078 }
1079
1080 /*
1081  * Use this func and the one below only after the atomic state has been
1082  * successfully swapped
1083  */
1084 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1085 {
1086         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1087
1088         if (WARN_ON(!pstate->hwpipe))
1089                 return SSPP_NONE;
1090
1091         return pstate->hwpipe->pipe;
1092 }
1093
1094 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1095 {
1096         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1097
1098         if (!pstate->r_hwpipe)
1099                 return SSPP_NONE;
1100
1101         return pstate->r_hwpipe->pipe;
1102 }
1103
1104 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1105 {
1106         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1107         u32 mask;
1108
1109         if (WARN_ON(!pstate->hwpipe))
1110                 return 0;
1111
1112         mask = pstate->hwpipe->flush_mask;
1113
1114         if (pstate->r_hwpipe)
1115                 mask |= pstate->r_hwpipe->flush_mask;
1116
1117         return mask;
1118 }
1119
1120 /* initialize plane */
1121 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1122                                   enum drm_plane_type type)
1123 {
1124         struct drm_plane *plane = NULL;
1125         struct mdp5_plane *mdp5_plane;
1126         int ret;
1127
1128         mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1129         if (!mdp5_plane) {
1130                 ret = -ENOMEM;
1131                 goto fail;
1132         }
1133
1134         plane = &mdp5_plane->base;
1135
1136         mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1137                 ARRAY_SIZE(mdp5_plane->formats), false);
1138
1139         if (type == DRM_PLANE_TYPE_CURSOR)
1140                 ret = drm_universal_plane_init(dev, plane, 0xff,
1141                                 &mdp5_cursor_plane_funcs,
1142                                 mdp5_plane->formats, mdp5_plane->nformats,
1143                                 NULL, type, NULL);
1144         else
1145                 ret = drm_universal_plane_init(dev, plane, 0xff,
1146                                 &mdp5_plane_funcs,
1147                                 mdp5_plane->formats, mdp5_plane->nformats,
1148                                 NULL, type, NULL);
1149         if (ret)
1150                 goto fail;
1151
1152         drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1153
1154         mdp5_plane_install_properties(plane, &plane->base);
1155
1156         return plane;
1157
1158 fail:
1159         if (plane)
1160                 mdp5_plane_destroy(plane);
1161
1162         return ERR_PTR(ret);
1163 }