2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 * Some code and ideas taken from drivers/video/omap/ driver
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #define DSS_SUBSYS_NAME "DSS"
23 #include <linux/debugfs.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/export.h>
29 #include <linux/err.h>
30 #include <linux/delay.h>
31 #include <linux/seq_file.h>
32 #include <linux/clk.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/gfp.h>
37 #include <linux/sizes.h>
38 #include <linux/mfd/syscon.h>
39 #include <linux/regmap.h>
41 #include <linux/of_device.h>
42 #include <linux/of_graph.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/suspend.h>
45 #include <linux/component.h>
46 #include <linux/sys_soc.h>
55 #define DSS_REG(idx) ((const struct dss_reg) { idx })
57 #define DSS_REVISION DSS_REG(0x0000)
58 #define DSS_SYSCONFIG DSS_REG(0x0010)
59 #define DSS_SYSSTATUS DSS_REG(0x0014)
60 #define DSS_CONTROL DSS_REG(0x0040)
61 #define DSS_SDI_CONTROL DSS_REG(0x0044)
62 #define DSS_PLL_CONTROL DSS_REG(0x0048)
63 #define DSS_SDI_STATUS DSS_REG(0x005C)
65 #define REG_GET(dss, idx, start, end) \
66 FLD_GET(dss_read_reg(dss, idx), start, end)
68 #define REG_FLD_MOD(dss, idx, val, start, end) \
69 dss_write_reg(dss, idx, \
70 FLD_MOD(dss_read_reg(dss, idx), val, start, end))
73 int (*dpi_select_source)(struct dss_device *dss, int port,
74 enum omap_channel channel);
75 int (*select_lcd_source)(struct dss_device *dss,
76 enum omap_channel channel,
77 enum dss_clk_source clk_src);
83 unsigned int fck_freq_max;
84 u8 dss_fck_multiplier;
85 const char *parent_clk_name;
86 const enum omap_display_type *ports;
88 const enum omap_dss_output_id *outputs;
89 const struct dss_ops *ops;
90 struct dss_reg_field dispc_clk_switch;
94 static const char * const dss_generic_clk_source_names[] = {
95 [DSS_CLK_SRC_FCK] = "FCK",
96 [DSS_CLK_SRC_PLL1_1] = "PLL1:1",
97 [DSS_CLK_SRC_PLL1_2] = "PLL1:2",
98 [DSS_CLK_SRC_PLL1_3] = "PLL1:3",
99 [DSS_CLK_SRC_PLL2_1] = "PLL2:1",
100 [DSS_CLK_SRC_PLL2_2] = "PLL2:2",
101 [DSS_CLK_SRC_PLL2_3] = "PLL2:3",
102 [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL",
105 static inline void dss_write_reg(struct dss_device *dss,
106 const struct dss_reg idx, u32 val)
108 __raw_writel(val, dss->base + idx.idx);
111 static inline u32 dss_read_reg(struct dss_device *dss, const struct dss_reg idx)
113 return __raw_readl(dss->base + idx.idx);
116 #define SR(dss, reg) \
117 dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg)
118 #define RR(dss, reg) \
119 dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)])
121 static void dss_save_context(struct dss_device *dss)
123 DSSDBG("dss_save_context\n");
127 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
128 SR(dss, SDI_CONTROL);
129 SR(dss, PLL_CONTROL);
132 dss->ctx_valid = true;
134 DSSDBG("context saved\n");
137 static void dss_restore_context(struct dss_device *dss)
139 DSSDBG("dss_restore_context\n");
146 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
147 RR(dss, SDI_CONTROL);
148 RR(dss, PLL_CONTROL);
151 DSSDBG("context restored\n");
157 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable)
162 if (!pll->dss->syscon_pll_ctrl)
178 DSSERR("illegal DSS PLL ID %d\n", pll->id);
182 regmap_update_bits(pll->dss->syscon_pll_ctrl,
183 pll->dss->syscon_pll_ctrl_offset,
184 1 << shift, val << shift);
187 static int dss_ctrl_pll_set_control_mux(struct dss_device *dss,
188 enum dss_clk_source clk_src,
189 enum omap_channel channel)
191 unsigned int shift, val;
193 if (!dss->syscon_pll_ctrl)
197 case OMAP_DSS_CHANNEL_LCD:
201 case DSS_CLK_SRC_PLL1_1:
203 case DSS_CLK_SRC_HDMI_PLL:
206 DSSERR("error in PLL mux config for LCD\n");
211 case OMAP_DSS_CHANNEL_LCD2:
215 case DSS_CLK_SRC_PLL1_3:
217 case DSS_CLK_SRC_PLL2_3:
219 case DSS_CLK_SRC_HDMI_PLL:
222 DSSERR("error in PLL mux config for LCD2\n");
227 case OMAP_DSS_CHANNEL_LCD3:
231 case DSS_CLK_SRC_PLL2_1:
233 case DSS_CLK_SRC_PLL1_3:
235 case DSS_CLK_SRC_HDMI_PLL:
238 DSSERR("error in PLL mux config for LCD3\n");
244 DSSERR("error in PLL mux config\n");
248 regmap_update_bits(dss->syscon_pll_ctrl, dss->syscon_pll_ctrl_offset,
249 0x3 << shift, val << shift);
254 void dss_sdi_init(struct dss_device *dss, int datapairs)
258 BUG_ON(datapairs > 3 || datapairs < 1);
260 l = dss_read_reg(dss, DSS_SDI_CONTROL);
261 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
262 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
263 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
264 dss_write_reg(dss, DSS_SDI_CONTROL, l);
266 l = dss_read_reg(dss, DSS_PLL_CONTROL);
267 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
268 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
269 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
270 dss_write_reg(dss, DSS_PLL_CONTROL, l);
273 int dss_sdi_enable(struct dss_device *dss)
275 unsigned long timeout;
277 dispc_pck_free_enable(dss->dispc, 1);
280 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
281 udelay(1); /* wait 2x PCLK */
284 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
286 /* Waiting for PLL lock request to complete */
287 timeout = jiffies + msecs_to_jiffies(500);
288 while (dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 6)) {
289 if (time_after_eq(jiffies, timeout)) {
290 DSSERR("PLL lock request timed out\n");
295 /* Clearing PLL_GO bit */
296 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28);
298 /* Waiting for PLL to lock */
299 timeout = jiffies + msecs_to_jiffies(500);
300 while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 5))) {
301 if (time_after_eq(jiffies, timeout)) {
302 DSSERR("PLL lock timed out\n");
307 dispc_lcd_enable_signal(dss->dispc, 1);
309 /* Waiting for SDI reset to complete */
310 timeout = jiffies + msecs_to_jiffies(500);
311 while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 2))) {
312 if (time_after_eq(jiffies, timeout)) {
313 DSSERR("SDI reset timed out\n");
321 dispc_lcd_enable_signal(dss->dispc, 0);
324 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
326 dispc_pck_free_enable(dss->dispc, 0);
331 void dss_sdi_disable(struct dss_device *dss)
333 dispc_lcd_enable_signal(dss->dispc, 0);
335 dispc_pck_free_enable(dss->dispc, 0);
338 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
341 const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
343 return dss_generic_clk_source_names[clk_src];
346 static void dss_dump_clocks(struct dss_device *dss, struct seq_file *s)
348 const char *fclk_name;
349 unsigned long fclk_rate;
351 if (dss_runtime_get(dss))
354 seq_printf(s, "- DSS -\n");
356 fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK);
357 fclk_rate = clk_get_rate(dss->dss_clk);
359 seq_printf(s, "%s = %lu\n",
363 dss_runtime_put(dss);
366 static int dss_dump_regs(struct seq_file *s, void *p)
368 struct dss_device *dss = s->private;
370 #define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r))
372 if (dss_runtime_get(dss))
375 DUMPREG(dss, DSS_REVISION);
376 DUMPREG(dss, DSS_SYSCONFIG);
377 DUMPREG(dss, DSS_SYSSTATUS);
378 DUMPREG(dss, DSS_CONTROL);
380 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
381 DUMPREG(dss, DSS_SDI_CONTROL);
382 DUMPREG(dss, DSS_PLL_CONTROL);
383 DUMPREG(dss, DSS_SDI_STATUS);
386 dss_runtime_put(dss);
391 static int dss_debug_dump_clocks(struct seq_file *s, void *p)
393 struct dss_device *dss = s->private;
395 dss_dump_clocks(dss, s);
396 dispc_dump_clocks(dss->dispc, s);
397 #ifdef CONFIG_OMAP2_DSS_DSI
403 static int dss_get_channel_index(enum omap_channel channel)
406 case OMAP_DSS_CHANNEL_LCD:
408 case OMAP_DSS_CHANNEL_LCD2:
410 case OMAP_DSS_CHANNEL_LCD3:
418 static void dss_select_dispc_clk_source(struct dss_device *dss,
419 enum dss_clk_source clk_src)
424 * We always use PRCM clock as the DISPC func clock, except on DSS3,
425 * where we don't have separate DISPC and LCD clock sources.
427 if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK))
431 case DSS_CLK_SRC_FCK:
434 case DSS_CLK_SRC_PLL1_1:
437 case DSS_CLK_SRC_PLL2_1:
445 REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */
446 dss->feat->dispc_clk_switch.start,
447 dss->feat->dispc_clk_switch.end);
449 dss->dispc_clk_source = clk_src;
452 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
453 enum dss_clk_source clk_src)
458 case DSS_CLK_SRC_FCK:
461 case DSS_CLK_SRC_PLL1_2:
462 BUG_ON(dsi_module != 0);
465 case DSS_CLK_SRC_PLL2_2:
466 BUG_ON(dsi_module != 1);
474 pos = dsi_module == 0 ? 1 : 10;
475 REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
477 dss->dsi_clk_source[dsi_module] = clk_src;
480 static int dss_lcd_clk_mux_dra7(struct dss_device *dss,
481 enum omap_channel channel,
482 enum dss_clk_source clk_src)
484 const u8 ctrl_bits[] = {
485 [OMAP_DSS_CHANNEL_LCD] = 0,
486 [OMAP_DSS_CHANNEL_LCD2] = 12,
487 [OMAP_DSS_CHANNEL_LCD3] = 19,
490 u8 ctrl_bit = ctrl_bits[channel];
493 if (clk_src == DSS_CLK_SRC_FCK) {
494 /* LCDx_CLK_SWITCH */
495 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
499 r = dss_ctrl_pll_set_control_mux(dss, clk_src, channel);
503 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
508 static int dss_lcd_clk_mux_omap5(struct dss_device *dss,
509 enum omap_channel channel,
510 enum dss_clk_source clk_src)
512 const u8 ctrl_bits[] = {
513 [OMAP_DSS_CHANNEL_LCD] = 0,
514 [OMAP_DSS_CHANNEL_LCD2] = 12,
515 [OMAP_DSS_CHANNEL_LCD3] = 19,
517 const enum dss_clk_source allowed_plls[] = {
518 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
519 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK,
520 [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1,
523 u8 ctrl_bit = ctrl_bits[channel];
525 if (clk_src == DSS_CLK_SRC_FCK) {
526 /* LCDx_CLK_SWITCH */
527 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
531 if (WARN_ON(allowed_plls[channel] != clk_src))
534 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
539 static int dss_lcd_clk_mux_omap4(struct dss_device *dss,
540 enum omap_channel channel,
541 enum dss_clk_source clk_src)
543 const u8 ctrl_bits[] = {
544 [OMAP_DSS_CHANNEL_LCD] = 0,
545 [OMAP_DSS_CHANNEL_LCD2] = 12,
547 const enum dss_clk_source allowed_plls[] = {
548 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
549 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1,
552 u8 ctrl_bit = ctrl_bits[channel];
554 if (clk_src == DSS_CLK_SRC_FCK) {
555 /* LCDx_CLK_SWITCH */
556 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
560 if (WARN_ON(allowed_plls[channel] != clk_src))
563 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
568 void dss_select_lcd_clk_source(struct dss_device *dss,
569 enum omap_channel channel,
570 enum dss_clk_source clk_src)
572 int idx = dss_get_channel_index(channel);
575 if (!dss->feat->has_lcd_clk_src) {
576 dss_select_dispc_clk_source(dss, clk_src);
577 dss->lcd_clk_source[idx] = clk_src;
581 r = dss->feat->ops->select_lcd_source(dss, channel, clk_src);
585 dss->lcd_clk_source[idx] = clk_src;
588 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss)
590 return dss->dispc_clk_source;
593 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
596 return dss->dsi_clk_source[dsi_module];
599 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
600 enum omap_channel channel)
602 if (dss->feat->has_lcd_clk_src) {
603 int idx = dss_get_channel_index(channel);
604 return dss->lcd_clk_source[idx];
606 /* LCD_CLK source is the same as DISPC_FCLK source for
608 return dss->dispc_clk_source;
612 bool dss_div_calc(struct dss_device *dss, unsigned long pck,
613 unsigned long fck_min, dss_div_calc_func func, void *data)
615 int fckd, fckd_start, fckd_stop;
617 unsigned long fck_hw_max;
618 unsigned long fckd_hw_max;
622 fck_hw_max = dss->feat->fck_freq_max;
624 if (dss->parent_clk == NULL) {
627 pckd = fck_hw_max / pck;
631 fck = clk_round_rate(dss->dss_clk, fck);
633 return func(fck, data);
636 fckd_hw_max = dss->feat->fck_div_max;
638 m = dss->feat->dss_fck_multiplier;
639 prate = clk_get_rate(dss->parent_clk);
641 fck_min = fck_min ? fck_min : 1;
643 fckd_start = min(prate * m / fck_min, fckd_hw_max);
644 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
646 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
647 fck = DIV_ROUND_UP(prate, fckd) * m;
656 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate)
660 DSSDBG("set fck to %lu\n", rate);
662 r = clk_set_rate(dss->dss_clk, rate);
666 dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
668 WARN_ONCE(dss->dss_clk_rate != rate, "clk rate mismatch: %lu != %lu",
669 dss->dss_clk_rate, rate);
674 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss)
676 return dss->dss_clk_rate;
679 unsigned long dss_get_max_fck_rate(struct dss_device *dss)
681 return dss->feat->fck_freq_max;
684 enum omap_dss_output_id dss_get_supported_outputs(struct dss_device *dss,
685 enum omap_channel channel)
687 return dss->feat->outputs[channel];
690 static int dss_setup_default_clock(struct dss_device *dss)
692 unsigned long max_dss_fck, prate;
694 unsigned int fck_div;
697 max_dss_fck = dss->feat->fck_freq_max;
699 if (dss->parent_clk == NULL) {
700 fck = clk_round_rate(dss->dss_clk, max_dss_fck);
702 prate = clk_get_rate(dss->parent_clk);
704 fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier,
706 fck = DIV_ROUND_UP(prate, fck_div)
707 * dss->feat->dss_fck_multiplier;
710 r = dss_set_fck_rate(dss, fck);
717 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type)
721 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
723 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
728 /* venc out selection. 0 = comp, 1 = svideo */
729 REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);
732 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable)
734 /* DAC Power-Down Control */
735 REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);
738 void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
739 enum dss_hdmi_venc_clk_source_select src)
741 enum omap_dss_output_id outputs;
743 outputs = dss->feat->outputs[OMAP_DSS_CHANNEL_DIGIT];
745 /* Complain about invalid selections */
746 WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC));
747 WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI));
749 /* Select only if we have options */
750 if ((outputs & OMAP_DSS_OUTPUT_VENC) &&
751 (outputs & OMAP_DSS_OUTPUT_HDMI))
752 /* VENC_HDMI_SWITCH */
753 REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);
756 static int dss_dpi_select_source_omap2_omap3(struct dss_device *dss, int port,
757 enum omap_channel channel)
759 if (channel != OMAP_DSS_CHANNEL_LCD)
765 static int dss_dpi_select_source_omap4(struct dss_device *dss, int port,
766 enum omap_channel channel)
771 case OMAP_DSS_CHANNEL_LCD2:
774 case OMAP_DSS_CHANNEL_DIGIT:
781 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);
786 static int dss_dpi_select_source_omap5(struct dss_device *dss, int port,
787 enum omap_channel channel)
792 case OMAP_DSS_CHANNEL_LCD:
795 case OMAP_DSS_CHANNEL_LCD2:
798 case OMAP_DSS_CHANNEL_LCD3:
801 case OMAP_DSS_CHANNEL_DIGIT:
808 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);
813 static int dss_dpi_select_source_dra7xx(struct dss_device *dss, int port,
814 enum omap_channel channel)
818 return dss_dpi_select_source_omap5(dss, port, channel);
820 if (channel != OMAP_DSS_CHANNEL_LCD2)
824 if (channel != OMAP_DSS_CHANNEL_LCD3)
834 int dss_dpi_select_source(struct dss_device *dss, int port,
835 enum omap_channel channel)
837 return dss->feat->ops->dpi_select_source(dss, port, channel);
840 static int dss_get_clocks(struct dss_device *dss)
844 clk = devm_clk_get(&dss->pdev->dev, "fck");
846 DSSERR("can't get clock fck\n");
852 if (dss->feat->parent_clk_name) {
853 clk = clk_get(NULL, dss->feat->parent_clk_name);
855 DSSERR("Failed to get %s\n",
856 dss->feat->parent_clk_name);
863 dss->parent_clk = clk;
868 static void dss_put_clocks(struct dss_device *dss)
871 clk_put(dss->parent_clk);
874 int dss_runtime_get(struct dss_device *dss)
878 DSSDBG("dss_runtime_get\n");
880 r = pm_runtime_get_sync(&dss->pdev->dev);
882 return r < 0 ? r : 0;
885 void dss_runtime_put(struct dss_device *dss)
889 DSSDBG("dss_runtime_put\n");
891 r = pm_runtime_put_sync(&dss->pdev->dev);
892 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
895 struct dss_device *dss_get_device(struct device *dev)
897 return dev_get_drvdata(dev);
901 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
902 static int dss_initialize_debugfs(struct dss_device *dss)
906 dir = debugfs_create_dir("omapdss", NULL);
910 dss->debugfs.root = dir;
915 static void dss_uninitialize_debugfs(struct dss_device *dss)
917 debugfs_remove_recursive(dss->debugfs.root);
920 struct dss_debugfs_entry {
921 struct dentry *dentry;
922 int (*show_fn)(struct seq_file *s, void *data);
926 static int dss_debug_open(struct inode *inode, struct file *file)
928 struct dss_debugfs_entry *entry = inode->i_private;
930 return single_open(file, entry->show_fn, entry->data);
933 static const struct file_operations dss_debug_fops = {
934 .open = dss_debug_open,
937 .release = single_release,
940 struct dss_debugfs_entry *
941 dss_debugfs_create_file(struct dss_device *dss, const char *name,
942 int (*show_fn)(struct seq_file *s, void *data),
945 struct dss_debugfs_entry *entry;
948 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
950 return ERR_PTR(-ENOMEM);
952 entry->show_fn = show_fn;
955 d = debugfs_create_file(name, 0444, dss->debugfs.root, entry,
959 return ERR_PTR(PTR_ERR(d));
966 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
968 if (IS_ERR_OR_NULL(entry))
971 debugfs_remove(entry->dentry);
975 #else /* CONFIG_OMAP2_DSS_DEBUGFS */
976 static inline int dss_initialize_debugfs(struct dss_device *dss)
980 static inline void dss_uninitialize_debugfs(struct dss_device *dss)
983 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */
985 static const struct dss_ops dss_ops_omap2_omap3 = {
986 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
989 static const struct dss_ops dss_ops_omap4 = {
990 .dpi_select_source = &dss_dpi_select_source_omap4,
991 .select_lcd_source = &dss_lcd_clk_mux_omap4,
994 static const struct dss_ops dss_ops_omap5 = {
995 .dpi_select_source = &dss_dpi_select_source_omap5,
996 .select_lcd_source = &dss_lcd_clk_mux_omap5,
999 static const struct dss_ops dss_ops_dra7 = {
1000 .dpi_select_source = &dss_dpi_select_source_dra7xx,
1001 .select_lcd_source = &dss_lcd_clk_mux_dra7,
1004 static const enum omap_display_type omap2plus_ports[] = {
1005 OMAP_DISPLAY_TYPE_DPI,
1008 static const enum omap_display_type omap34xx_ports[] = {
1009 OMAP_DISPLAY_TYPE_DPI,
1010 OMAP_DISPLAY_TYPE_SDI,
1013 static const enum omap_display_type dra7xx_ports[] = {
1014 OMAP_DISPLAY_TYPE_DPI,
1015 OMAP_DISPLAY_TYPE_DPI,
1016 OMAP_DISPLAY_TYPE_DPI,
1019 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
1020 /* OMAP_DSS_CHANNEL_LCD */
1021 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
1023 /* OMAP_DSS_CHANNEL_DIGIT */
1024 OMAP_DSS_OUTPUT_VENC,
1027 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
1028 /* OMAP_DSS_CHANNEL_LCD */
1029 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1030 OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
1032 /* OMAP_DSS_CHANNEL_DIGIT */
1033 OMAP_DSS_OUTPUT_VENC,
1036 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
1037 /* OMAP_DSS_CHANNEL_LCD */
1038 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1039 OMAP_DSS_OUTPUT_DSI1,
1041 /* OMAP_DSS_CHANNEL_DIGIT */
1042 OMAP_DSS_OUTPUT_VENC,
1045 static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
1046 /* OMAP_DSS_CHANNEL_LCD */
1047 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
1050 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
1051 /* OMAP_DSS_CHANNEL_LCD */
1052 OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
1054 /* OMAP_DSS_CHANNEL_DIGIT */
1055 OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI,
1057 /* OMAP_DSS_CHANNEL_LCD2 */
1058 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1059 OMAP_DSS_OUTPUT_DSI2,
1062 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
1063 /* OMAP_DSS_CHANNEL_LCD */
1064 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1065 OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
1067 /* OMAP_DSS_CHANNEL_DIGIT */
1068 OMAP_DSS_OUTPUT_HDMI,
1070 /* OMAP_DSS_CHANNEL_LCD2 */
1071 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1072 OMAP_DSS_OUTPUT_DSI1,
1074 /* OMAP_DSS_CHANNEL_LCD3 */
1075 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1076 OMAP_DSS_OUTPUT_DSI2,
1079 static const struct dss_features omap24xx_dss_feats = {
1080 .model = DSS_MODEL_OMAP2,
1082 * fck div max is really 16, but the divider range has gaps. The range
1083 * from 1 to 6 has no gaps, so let's use that as a max.
1086 .fck_freq_max = 133000000,
1087 .dss_fck_multiplier = 2,
1088 .parent_clk_name = "core_ck",
1089 .ports = omap2plus_ports,
1090 .num_ports = ARRAY_SIZE(omap2plus_ports),
1091 .outputs = omap2_dss_supported_outputs,
1092 .ops = &dss_ops_omap2_omap3,
1093 .dispc_clk_switch = { 0, 0 },
1094 .has_lcd_clk_src = false,
1097 static const struct dss_features omap34xx_dss_feats = {
1098 .model = DSS_MODEL_OMAP3,
1100 .fck_freq_max = 173000000,
1101 .dss_fck_multiplier = 2,
1102 .parent_clk_name = "dpll4_ck",
1103 .ports = omap34xx_ports,
1104 .outputs = omap3430_dss_supported_outputs,
1105 .num_ports = ARRAY_SIZE(omap34xx_ports),
1106 .ops = &dss_ops_omap2_omap3,
1107 .dispc_clk_switch = { 0, 0 },
1108 .has_lcd_clk_src = false,
1111 static const struct dss_features omap3630_dss_feats = {
1112 .model = DSS_MODEL_OMAP3,
1114 .fck_freq_max = 173000000,
1115 .dss_fck_multiplier = 1,
1116 .parent_clk_name = "dpll4_ck",
1117 .ports = omap2plus_ports,
1118 .num_ports = ARRAY_SIZE(omap2plus_ports),
1119 .outputs = omap3630_dss_supported_outputs,
1120 .ops = &dss_ops_omap2_omap3,
1121 .dispc_clk_switch = { 0, 0 },
1122 .has_lcd_clk_src = false,
1125 static const struct dss_features omap44xx_dss_feats = {
1126 .model = DSS_MODEL_OMAP4,
1128 .fck_freq_max = 186000000,
1129 .dss_fck_multiplier = 1,
1130 .parent_clk_name = "dpll_per_x2_ck",
1131 .ports = omap2plus_ports,
1132 .num_ports = ARRAY_SIZE(omap2plus_ports),
1133 .outputs = omap4_dss_supported_outputs,
1134 .ops = &dss_ops_omap4,
1135 .dispc_clk_switch = { 9, 8 },
1136 .has_lcd_clk_src = true,
1139 static const struct dss_features omap54xx_dss_feats = {
1140 .model = DSS_MODEL_OMAP5,
1142 .fck_freq_max = 209250000,
1143 .dss_fck_multiplier = 1,
1144 .parent_clk_name = "dpll_per_x2_ck",
1145 .ports = omap2plus_ports,
1146 .num_ports = ARRAY_SIZE(omap2plus_ports),
1147 .outputs = omap5_dss_supported_outputs,
1148 .ops = &dss_ops_omap5,
1149 .dispc_clk_switch = { 9, 7 },
1150 .has_lcd_clk_src = true,
1153 static const struct dss_features am43xx_dss_feats = {
1154 .model = DSS_MODEL_OMAP3,
1156 .fck_freq_max = 200000000,
1157 .dss_fck_multiplier = 0,
1158 .parent_clk_name = NULL,
1159 .ports = omap2plus_ports,
1160 .num_ports = ARRAY_SIZE(omap2plus_ports),
1161 .outputs = am43xx_dss_supported_outputs,
1162 .ops = &dss_ops_omap2_omap3,
1163 .dispc_clk_switch = { 0, 0 },
1164 .has_lcd_clk_src = true,
1167 static const struct dss_features dra7xx_dss_feats = {
1168 .model = DSS_MODEL_DRA7,
1170 .fck_freq_max = 209250000,
1171 .dss_fck_multiplier = 1,
1172 .parent_clk_name = "dpll_per_x2_ck",
1173 .ports = dra7xx_ports,
1174 .num_ports = ARRAY_SIZE(dra7xx_ports),
1175 .outputs = omap5_dss_supported_outputs,
1176 .ops = &dss_ops_dra7,
1177 .dispc_clk_switch = { 9, 7 },
1178 .has_lcd_clk_src = true,
1181 static int dss_init_ports(struct dss_device *dss)
1183 struct platform_device *pdev = dss->pdev;
1184 struct device_node *parent = pdev->dev.of_node;
1185 struct device_node *port;
1188 for (i = 0; i < dss->feat->num_ports; i++) {
1189 port = of_graph_get_port_by_id(parent, i);
1193 switch (dss->feat->ports[i]) {
1194 case OMAP_DISPLAY_TYPE_DPI:
1195 dpi_init_port(dss, pdev, port, dss->feat->model);
1197 case OMAP_DISPLAY_TYPE_SDI:
1198 sdi_init_port(dss, pdev, port);
1208 static void dss_uninit_ports(struct dss_device *dss)
1210 struct platform_device *pdev = dss->pdev;
1211 struct device_node *parent = pdev->dev.of_node;
1212 struct device_node *port;
1215 for (i = 0; i < dss->feat->num_ports; i++) {
1216 port = of_graph_get_port_by_id(parent, i);
1220 switch (dss->feat->ports[i]) {
1221 case OMAP_DISPLAY_TYPE_DPI:
1222 dpi_uninit_port(port);
1224 case OMAP_DISPLAY_TYPE_SDI:
1225 sdi_uninit_port(port);
1233 static int dss_video_pll_probe(struct dss_device *dss)
1235 struct platform_device *pdev = dss->pdev;
1236 struct device_node *np = pdev->dev.of_node;
1237 struct regulator *pll_regulator;
1243 if (of_property_read_bool(np, "syscon-pll-ctrl")) {
1244 dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1246 if (IS_ERR(dss->syscon_pll_ctrl)) {
1248 "failed to get syscon-pll-ctrl regmap\n");
1249 return PTR_ERR(dss->syscon_pll_ctrl);
1252 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1253 &dss->syscon_pll_ctrl_offset)) {
1255 "failed to get syscon-pll-ctrl offset\n");
1260 pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
1261 if (IS_ERR(pll_regulator)) {
1262 r = PTR_ERR(pll_regulator);
1266 pll_regulator = NULL;
1270 return -EPROBE_DEFER;
1273 DSSERR("can't get DPLL VDDA regulator\n");
1278 if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1279 dss->video1_pll = dss_video_pll_init(dss, pdev, 0,
1281 if (IS_ERR(dss->video1_pll))
1282 return PTR_ERR(dss->video1_pll);
1285 if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1286 dss->video2_pll = dss_video_pll_init(dss, pdev, 1,
1288 if (IS_ERR(dss->video2_pll)) {
1289 dss_video_pll_uninit(dss->video1_pll);
1290 return PTR_ERR(dss->video2_pll);
1297 /* DSS HW IP initialisation */
1298 static const struct of_device_id dss_of_match[] = {
1299 { .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats },
1300 { .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats },
1301 { .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats },
1302 { .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats },
1303 { .compatible = "ti,dra7-dss", .data = &dra7xx_dss_feats },
1306 MODULE_DEVICE_TABLE(of, dss_of_match);
1308 static const struct soc_device_attribute dss_soc_devices[] = {
1309 { .machine = "OMAP3430/3530", .data = &omap34xx_dss_feats },
1310 { .machine = "AM35??", .data = &omap34xx_dss_feats },
1311 { .family = "AM43xx", .data = &am43xx_dss_feats },
1315 static int dss_bind(struct device *dev)
1317 struct dss_device *dss = dev_get_drvdata(dev);
1320 r = component_bind_all(dev, NULL);
1324 pm_set_vt_switch(0);
1326 omapdss_gather_components(dev);
1327 omapdss_set_dss(dss);
1332 static void dss_unbind(struct device *dev)
1334 omapdss_set_dss(NULL);
1336 component_unbind_all(dev, NULL);
1339 static const struct component_master_ops dss_component_ops = {
1341 .unbind = dss_unbind,
1344 static int dss_component_compare(struct device *dev, void *data)
1346 struct device *child = data;
1347 return dev == child;
1350 static int dss_add_child_component(struct device *dev, void *data)
1352 struct component_match **match = data;
1356 * We don't have a working driver for rfbi, so skip it here always.
1357 * Otherwise dss will never get probed successfully, as it will wait
1358 * for rfbi to get probed.
1360 if (strstr(dev_name(dev), "rfbi"))
1363 component_match_add(dev->parent, match, dss_component_compare, dev);
1368 static int dss_probe_hardware(struct dss_device *dss)
1373 r = dss_runtime_get(dss);
1377 dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
1380 REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);
1382 dss_select_dispc_clk_source(dss, DSS_CLK_SRC_FCK);
1384 #ifdef CONFIG_OMAP2_DSS_VENC
1385 REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */
1386 REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
1387 REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
1389 dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK;
1390 dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK;
1391 dss->dispc_clk_source = DSS_CLK_SRC_FCK;
1392 dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK;
1393 dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK;
1395 rev = dss_read_reg(dss, DSS_REVISION);
1396 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1398 dss_runtime_put(dss);
1403 static int dss_probe(struct platform_device *pdev)
1405 const struct soc_device_attribute *soc;
1406 struct component_match *match = NULL;
1407 struct resource *dss_mem;
1408 struct dss_device *dss;
1411 dss = kzalloc(sizeof(*dss), GFP_KERNEL);
1416 platform_set_drvdata(pdev, dss);
1418 r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1420 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
1425 * The various OMAP3-based SoCs can't be told apart using the compatible
1426 * string, use SoC device matching.
1428 soc = soc_device_match(dss_soc_devices);
1430 dss->feat = soc->data;
1432 dss->feat = of_match_device(dss_of_match, &pdev->dev)->data;
1434 /* Map I/O registers, get and setup clocks. */
1435 dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1436 dss->base = devm_ioremap_resource(&pdev->dev, dss_mem);
1437 if (IS_ERR(dss->base)) {
1438 r = PTR_ERR(dss->base);
1442 r = dss_get_clocks(dss);
1446 r = dss_setup_default_clock(dss);
1448 goto err_put_clocks;
1450 /* Setup the video PLLs and the DPI and SDI ports. */
1451 r = dss_video_pll_probe(dss);
1453 goto err_put_clocks;
1455 r = dss_init_ports(dss);
1457 goto err_uninit_plls;
1459 /* Enable runtime PM and probe the hardware. */
1460 pm_runtime_enable(&pdev->dev);
1462 r = dss_probe_hardware(dss);
1464 goto err_pm_runtime_disable;
1466 /* Initialize debugfs. */
1467 r = dss_initialize_debugfs(dss);
1469 goto err_pm_runtime_disable;
1471 dss->debugfs.clk = dss_debugfs_create_file(dss, "clk",
1472 dss_debug_dump_clocks, dss);
1473 dss->debugfs.dss = dss_debugfs_create_file(dss, "dss", dss_dump_regs,
1476 /* Add all the child devices as components. */
1477 device_for_each_child(&pdev->dev, &match, dss_add_child_component);
1479 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1481 goto err_uninit_debugfs;
1486 dss_debugfs_remove_file(dss->debugfs.clk);
1487 dss_debugfs_remove_file(dss->debugfs.dss);
1488 dss_uninitialize_debugfs(dss);
1490 err_pm_runtime_disable:
1491 pm_runtime_disable(&pdev->dev);
1492 dss_uninit_ports(dss);
1495 if (dss->video1_pll)
1496 dss_video_pll_uninit(dss->video1_pll);
1497 if (dss->video2_pll)
1498 dss_video_pll_uninit(dss->video2_pll);
1501 dss_put_clocks(dss);
1509 static int dss_remove(struct platform_device *pdev)
1511 struct dss_device *dss = platform_get_drvdata(pdev);
1513 component_master_del(&pdev->dev, &dss_component_ops);
1515 dss_debugfs_remove_file(dss->debugfs.clk);
1516 dss_debugfs_remove_file(dss->debugfs.dss);
1517 dss_uninitialize_debugfs(dss);
1519 pm_runtime_disable(&pdev->dev);
1521 dss_uninit_ports(dss);
1523 if (dss->video1_pll)
1524 dss_video_pll_uninit(dss->video1_pll);
1526 if (dss->video2_pll)
1527 dss_video_pll_uninit(dss->video2_pll);
1529 dss_put_clocks(dss);
1536 static void dss_shutdown(struct platform_device *pdev)
1538 struct omap_dss_device *dssdev = NULL;
1540 DSSDBG("shutdown\n");
1542 for_each_dss_dev(dssdev) {
1543 if (!dssdev->driver)
1546 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
1547 dssdev->driver->disable(dssdev);
1551 static int dss_runtime_suspend(struct device *dev)
1553 struct dss_device *dss = dev_get_drvdata(dev);
1555 dss_save_context(dss);
1556 dss_set_min_bus_tput(dev, 0);
1558 pinctrl_pm_select_sleep_state(dev);
1563 static int dss_runtime_resume(struct device *dev)
1565 struct dss_device *dss = dev_get_drvdata(dev);
1568 pinctrl_pm_select_default_state(dev);
1571 * Set an arbitrarily high tput request to ensure OPP100.
1572 * What we should really do is to make a request to stay in OPP100,
1573 * without any tput requirements, but that is not currently possible
1577 r = dss_set_min_bus_tput(dev, 1000000000);
1581 dss_restore_context(dss);
1585 static const struct dev_pm_ops dss_pm_ops = {
1586 .runtime_suspend = dss_runtime_suspend,
1587 .runtime_resume = dss_runtime_resume,
1590 struct platform_driver omap_dsshw_driver = {
1592 .remove = dss_remove,
1593 .shutdown = dss_shutdown,
1595 .name = "omapdss_dss",
1597 .of_match_table = dss_of_match,
1598 .suppress_bind_attrs = true,