drivers/gpu/drm/omapdrm/dss/hdmi.h

   1 /*
   2  * HDMI driver definition for TI OMAP4 Processor.
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef _HDMI_H
  20 #define _HDMI_H
  21
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/hdmi.h>
  26 #include <sound/omap-hdmi-audio.h>
  27 #include <media/cec.h>
  28
  29 #include "omapdss.h"
  30 #include "dss.h"
  31
  32 struct dss_device;
  33
  34 /* HDMI Wrapper */
  35
  36 #define HDMI_WP_REVISION                        0x0
  37 #define HDMI_WP_SYSCONFIG                       0x10
  38 #define HDMI_WP_IRQSTATUS_RAW                   0x24
  39 #define HDMI_WP_IRQSTATUS                       0x28
  40 #define HDMI_WP_IRQENABLE_SET                   0x2C
  41 #define HDMI_WP_IRQENABLE_CLR                   0x30
  42 #define HDMI_WP_IRQWAKEEN                       0x34
  43 #define HDMI_WP_PWR_CTRL                        0x40
  44 #define HDMI_WP_DEBOUNCE                        0x44
  45 #define HDMI_WP_VIDEO_CFG                       0x50
  46 #define HDMI_WP_VIDEO_SIZE                      0x60
  47 #define HDMI_WP_VIDEO_TIMING_H                  0x68
  48 #define HDMI_WP_VIDEO_TIMING_V                  0x6C
  49 #define HDMI_WP_CLK                             0x70
  50 #define HDMI_WP_AUDIO_CFG                       0x80
  51 #define HDMI_WP_AUDIO_CFG2                      0x84
  52 #define HDMI_WP_AUDIO_CTRL                      0x88
  53 #define HDMI_WP_AUDIO_DATA                      0x8C
  54
  55 /* HDMI WP IRQ flags */
  56 #define HDMI_IRQ_CORE                           (1 << 0)
  57 #define HDMI_IRQ_OCP_TIMEOUT                    (1 << 4)
  58 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW           (1 << 8)
  59 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW            (1 << 9)
  60 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ          (1 << 10)
  61 #define HDMI_IRQ_VIDEO_VSYNC                    (1 << 16)
  62 #define HDMI_IRQ_VIDEO_FRAME_DONE               (1 << 17)
  63 #define HDMI_IRQ_PHY_LINE5V_ASSERT              (1 << 24)
  64 #define HDMI_IRQ_LINK_CONNECT                   (1 << 25)
  65 #define HDMI_IRQ_LINK_DISCONNECT                (1 << 26)
  66 #define HDMI_IRQ_PLL_LOCK                       (1 << 29)
  67 #define HDMI_IRQ_PLL_UNLOCK                     (1 << 30)
  68 #define HDMI_IRQ_PLL_RECAL                      (1 << 31)
  69
  70 /* HDMI PLL */
  71
  72 #define PLLCTRL_PLL_CONTROL                     0x0
  73 #define PLLCTRL_PLL_STATUS                      0x4
  74 #define PLLCTRL_PLL_GO                          0x8
  75 #define PLLCTRL_CFG1                            0xC
  76 #define PLLCTRL_CFG2                            0x10
  77 #define PLLCTRL_CFG3                            0x14
  78 #define PLLCTRL_SSC_CFG1                        0x18
  79 #define PLLCTRL_SSC_CFG2                        0x1C
  80 #define PLLCTRL_CFG4                            0x20
  81
  82 /* HDMI PHY */
  83
  84 #define HDMI_TXPHY_TX_CTRL                      0x0
  85 #define HDMI_TXPHY_DIGITAL_CTRL                 0x4
  86 #define HDMI_TXPHY_POWER_CTRL                   0x8
  87 #define HDMI_TXPHY_PAD_CFG_CTRL                 0xC
  88 #define HDMI_TXPHY_BIST_CONTROL                 0x1C
  89
  90 enum hdmi_pll_pwr {
  91         HDMI_PLLPWRCMD_ALLOFF = 0,
  92         HDMI_PLLPWRCMD_PLLONLY = 1,
  93         HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
  94         HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
  95 };
  96
  97 enum hdmi_phy_pwr {
  98         HDMI_PHYPWRCMD_OFF = 0,
  99         HDMI_PHYPWRCMD_LDOON = 1,
 100         HDMI_PHYPWRCMD_TXON = 2
 101 };
 102
 103 enum hdmi_core_hdmi_dvi {
 104         HDMI_DVI = 0,
 105         HDMI_HDMI = 1
 106 };
 107
 108 enum hdmi_packing_mode {
 109         HDMI_PACK_10b_RGB_YUV444 = 0,
 110         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 111         HDMI_PACK_20b_YUV422 = 2,
 112         HDMI_PACK_ALREADYPACKED = 7
 113 };
 114
 115 enum hdmi_stereo_channels {
 116         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 117         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 118         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 119         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 120         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 121 };
 122
 123 enum hdmi_audio_type {
 124         HDMI_AUDIO_TYPE_LPCM = 0,
 125         HDMI_AUDIO_TYPE_IEC = 1
 126 };
 127
 128 enum hdmi_audio_justify {
 129         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 130         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 131 };
 132
 133 enum hdmi_audio_sample_order {
 134         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 135         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 136 };
 137
 138 enum hdmi_audio_samples_perword {
 139         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 140         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 141 };
 142
 143 enum hdmi_audio_sample_size_omap {
 144         HDMI_AUDIO_SAMPLE_16BITS = 0,
 145         HDMI_AUDIO_SAMPLE_24BITS = 1
 146 };
 147
 148 enum hdmi_audio_transf_mode {
 149         HDMI_AUDIO_TRANSF_DMA = 0,
 150         HDMI_AUDIO_TRANSF_IRQ = 1
 151 };
 152
 153 enum hdmi_audio_blk_strt_end_sig {
 154         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 155         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 156 };
 157
 158 enum hdmi_core_audio_layout {
 159         HDMI_AUDIO_LAYOUT_2CH = 0,
 160         HDMI_AUDIO_LAYOUT_8CH = 1,
 161         HDMI_AUDIO_LAYOUT_6CH = 2
 162 };
 163
 164 enum hdmi_core_cts_mode {
 165         HDMI_AUDIO_CTS_MODE_HW = 0,
 166         HDMI_AUDIO_CTS_MODE_SW = 1
 167 };
 168
 169 enum hdmi_audio_mclk_mode {
 170         HDMI_AUDIO_MCLK_128FS = 0,
 171         HDMI_AUDIO_MCLK_256FS = 1,
 172         HDMI_AUDIO_MCLK_384FS = 2,
 173         HDMI_AUDIO_MCLK_512FS = 3,
 174         HDMI_AUDIO_MCLK_768FS = 4,
 175         HDMI_AUDIO_MCLK_1024FS = 5,
 176         HDMI_AUDIO_MCLK_1152FS = 6,
 177         HDMI_AUDIO_MCLK_192FS = 7
 178 };
 179
 180 struct hdmi_video_format {
 181         enum hdmi_packing_mode  packing_mode;
 182         u32                     y_res;  /* Line per panel */
 183         u32                     x_res;  /* pixel per line */
 184 };
 185
 186 struct hdmi_config {
 187         struct videomode vm;
 188         struct hdmi_avi_infoframe infoframe;
 189         enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
 190 };
 191
 192 struct hdmi_audio_format {
 193         enum hdmi_stereo_channels               stereo_channels;
 194         u8                                      active_chnnls_msk;
 195         enum hdmi_audio_type                    type;
 196         enum hdmi_audio_justify                 justification;
 197         enum hdmi_audio_sample_order            sample_order;
 198         enum hdmi_audio_samples_perword         samples_per_word;
 199         enum hdmi_audio_sample_size_omap        sample_size;
 200         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 201 };
 202
 203 struct hdmi_audio_dma {
 204         u8                              transfer_size;
 205         u8                              block_size;
 206         enum hdmi_audio_transf_mode     mode;
 207         u16                             fifo_threshold;
 208 };
 209
 210 struct hdmi_core_audio_i2s_config {
 211         u8 in_length_bits;
 212         u8 justification;
 213         u8 sck_edge_mode;
 214         u8 vbit;
 215         u8 direction;
 216         u8 shift;
 217         u8 active_sds;
 218 };
 219
 220 struct hdmi_core_audio_config {
 221         struct hdmi_core_audio_i2s_config       i2s_cfg;
 222         struct snd_aes_iec958                   *iec60958_cfg;
 223         bool                                    fs_override;
 224         u32                                     n;
 225         u32                                     cts;
 226         u32                                     aud_par_busclk;
 227         enum hdmi_core_audio_layout             layout;
 228         enum hdmi_core_cts_mode                 cts_mode;
 229         bool                                    use_mclk;
 230         enum hdmi_audio_mclk_mode               mclk_mode;
 231         bool                                    en_acr_pkt;
 232         bool                                    en_dsd_audio;
 233         bool                                    en_parallel_aud_input;
 234         bool                                    en_spdif;
 235 };
 236
 237 struct hdmi_wp_data {
 238         void __iomem *base;
 239         phys_addr_t phys_base;
 240         unsigned int version;
 241 };
 242
 243 struct hdmi_pll_data {
 244         struct dss_pll pll;
 245
 246         void __iomem *base;
 247
 248         struct platform_device *pdev;
 249         struct hdmi_wp_data *wp;
 250 };
 251
 252 struct hdmi_phy_features {
 253         bool bist_ctrl;
 254         bool ldo_voltage;
 255         unsigned long max_phy;
 256 };
 257
 258 struct hdmi_phy_data {
 259         void __iomem *base;
 260
 261         const struct hdmi_phy_features *features;
 262         u8 lane_function[4];
 263         u8 lane_polarity[4];
 264 };
 265
 266 struct hdmi_core_data {
 267         void __iomem *base;
 268         bool cts_swmode;
 269         bool audio_use_mclk;
 270
 271         struct hdmi_wp_data *wp;
 272         unsigned int core_pwr_cnt;
 273         struct cec_adapter *adap;
 274 };
 275
 276 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
 277                 u32 val)
 278 {
 279         __raw_writel(val, base_addr + idx);
 280 }
 281
 282 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
 283 {
 284         return __raw_readl(base_addr + idx);
 285 }
 286
 287 #define REG_FLD_MOD(base, idx, val, start, end) \
 288         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
 289                                                         val, start, end))
 290 #define REG_GET(base, idx, start, end) \
 291         FLD_GET(hdmi_read_reg(base, idx), start, end)
 292
 293 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
 294                 const u32 idx, int b2, int b1, u32 val)
 295 {
 296         u32 t = 0, v;
 297         while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
 298                 if (t++ > 10000)
 299                         return v;
 300                 udelay(1);
 301         }
 302         return v;
 303 }
 304
 305 /* HDMI wrapper funcs */
 306 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
 307 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
 308 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
 309 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
 310 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
 311 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
 312 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
 313 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
 314 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
 315 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
 316                 struct hdmi_video_format *video_fmt);
 317 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
 318                 struct videomode *vm);
 319 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
 320                 struct videomode *vm);
 321 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
 322                 struct videomode *vm, struct hdmi_config *param);
 323 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,
 324                  unsigned int version);
 325 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
 326
 327 /* HDMI PLL funcs */
 328 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
 329 int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,
 330                   struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
 331 void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
 332
 333 /* HDMI PHY funcs */
 334 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
 335         unsigned long lfbitclk);
 336 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
 337 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy,
 338                   unsigned int version);
 339 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
 340
 341 /* HDMI common funcs */
 342 int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
 343         struct hdmi_phy_data *phy);
 344
 345 /* Audio funcs */
 346 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
 347 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
 348 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
 349 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
 350                 struct hdmi_audio_format *aud_fmt);
 351 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
 352                 struct hdmi_audio_dma *aud_dma);
 353 static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
 354 {
 355         return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
 356 }
 357
 358 /* HDMI DRV data */
 359 struct omap_hdmi {
 360         struct mutex lock;
 361         struct platform_device *pdev;
 362         struct dss_device *dss;
 363
 364         struct dss_debugfs_entry *debugfs;
 365
 366         struct hdmi_wp_data     wp;
 367         struct hdmi_pll_data    pll;
 368         struct hdmi_phy_data    phy;
 369         struct hdmi_core_data   core;
 370
 371         struct hdmi_config cfg;
 372
 373         struct regulator *vdda_reg;
 374
 375         bool core_enabled;
 376
 377         struct omap_dss_device output;
 378
 379         struct platform_device *audio_pdev;
 380         void (*audio_abort_cb)(struct device *dev);
 381         int wp_idlemode;
 382
 383         bool audio_configured;
 384         struct omap_dss_audio audio_config;
 385
 386         /* This lock should be taken when booleans below are touched. */
 387         spinlock_t audio_playing_lock;
 388         bool audio_playing;
 389         bool display_enabled;
 390 };
 391
 392 #define dssdev_to_hdmi(dssdev) container_of(dssdev, struct omap_hdmi, output)
 393
 394 #endif