2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #define DSS_SUBSYS_NAME "SDI"
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/export.h>
25 #include <linux/platform_device.h>
26 #include <linux/string.h>
33 struct platform_device *pdev;
34 struct dss_device *dss;
37 struct regulator *vdds_sdi_reg;
39 struct dss_lcd_mgr_config mgr_config;
43 struct omap_dss_device output;
46 #define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output)
48 struct sdi_clk_calc_ctx {
49 struct sdi_device *sdi;
50 unsigned long pck_min, pck_max;
53 struct dispc_clock_info dispc_cinfo;
56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
57 unsigned long pck, void *data)
59 struct sdi_clk_calc_ctx *ctx = data;
61 ctx->dispc_cinfo.lck_div = lckd;
62 ctx->dispc_cinfo.pck_div = pckd;
63 ctx->dispc_cinfo.lck = lck;
64 ctx->dispc_cinfo.pck = pck;
69 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
71 struct sdi_clk_calc_ctx *ctx = data;
75 return dispc_div_calc(ctx->sdi->dss->dispc, fck,
76 ctx->pck_min, ctx->pck_max,
77 dpi_calc_dispc_cb, ctx);
80 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
82 struct dispc_clock_info *dispc_cinfo)
85 struct sdi_clk_calc_ctx ctx;
88 * DSS fclk gives us very few possibilities, so finding a good pixel
89 * clock may not be possible. We try multiple times to find the clock,
90 * each time widening the pixel clock range we look for, up to
94 for (i = 0; i < 10; ++i) {
97 memset(&ctx, 0, sizeof(ctx));
101 if (pclk > 1000 * i * i * i)
102 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
105 ctx.pck_max = pclk + 1000 * i * i * i;
107 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
108 dpi_calc_dss_cb, &ctx);
111 *dispc_cinfo = ctx.dispc_cinfo;
119 static void sdi_config_lcd_manager(struct sdi_device *sdi)
121 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
123 sdi->mgr_config.stallmode = false;
124 sdi->mgr_config.fifohandcheck = false;
126 sdi->mgr_config.video_port_width = 24;
127 sdi->mgr_config.lcden_sig_polarity = 1;
129 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
132 static int sdi_display_enable(struct omap_dss_device *dssdev)
134 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
135 struct videomode *vm = &sdi->vm;
137 struct dispc_clock_info dispc_cinfo;
141 if (!sdi->output.dispc_channel_connected) {
142 DSSERR("failed to enable display: no output/manager\n");
146 r = regulator_enable(sdi->vdds_sdi_reg);
150 r = dispc_runtime_get(sdi->dss->dispc);
155 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
157 r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo);
159 goto err_calc_clock_div;
161 sdi->mgr_config.clock_info = dispc_cinfo;
163 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
165 if (pck != vm->pixelclock) {
166 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
167 vm->pixelclock, pck);
169 vm->pixelclock = pck;
173 dss_mgr_set_timings(&sdi->output, vm);
175 r = dss_set_fck_rate(sdi->dss, fck);
177 goto err_set_dss_clock_div;
179 sdi_config_lcd_manager(sdi);
182 * LCLK and PCLK divisors are located in shadow registers, and we
183 * normally write them to DISPC registers when enabling the output.
184 * However, SDI uses pck-free as source clock for its PLL, and pck-free
185 * is affected by the divisors. And as we need the PLL before enabling
186 * the output, we need to write the divisors early.
188 * It seems just writing to the DISPC register is enough, and we don't
189 * need to care about the shadow register mechanism for pck-free. The
190 * exact reason for this is unknown.
192 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
193 &sdi->mgr_config.clock_info);
195 dss_sdi_init(sdi->dss, sdi->datapairs);
196 r = dss_sdi_enable(sdi->dss);
201 r = dss_mgr_enable(&sdi->output);
208 dss_sdi_disable(sdi->dss);
210 err_set_dss_clock_div:
212 dispc_runtime_put(sdi->dss->dispc);
214 regulator_disable(sdi->vdds_sdi_reg);
219 static void sdi_display_disable(struct omap_dss_device *dssdev)
221 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
223 dss_mgr_disable(&sdi->output);
225 dss_sdi_disable(sdi->dss);
227 dispc_runtime_put(sdi->dss->dispc);
229 regulator_disable(sdi->vdds_sdi_reg);
232 static void sdi_set_timings(struct omap_dss_device *dssdev,
233 struct videomode *vm)
235 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
240 static void sdi_get_timings(struct omap_dss_device *dssdev,
241 struct videomode *vm)
243 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
248 static int sdi_check_timings(struct omap_dss_device *dssdev,
249 struct videomode *vm)
251 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
252 enum omap_channel channel = dssdev->dispc_channel;
254 if (!dispc_mgr_timings_ok(sdi->dss->dispc, channel, vm))
257 if (vm->pixelclock == 0)
263 static int sdi_init_regulator(struct sdi_device *sdi)
265 struct regulator *vdds_sdi;
267 if (sdi->vdds_sdi_reg)
270 vdds_sdi = devm_regulator_get(&sdi->pdev->dev, "vdds_sdi");
271 if (IS_ERR(vdds_sdi)) {
272 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
273 DSSERR("can't get VDDS_SDI regulator\n");
274 return PTR_ERR(vdds_sdi);
277 sdi->vdds_sdi_reg = vdds_sdi;
282 static int sdi_connect(struct omap_dss_device *dssdev,
283 struct omap_dss_device *dst)
285 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
288 r = sdi_init_regulator(sdi);
292 r = dss_mgr_connect(&sdi->output, dssdev);
296 r = omapdss_output_set_device(dssdev, dst);
298 DSSERR("failed to connect output to new device: %s\n",
300 dss_mgr_disconnect(&sdi->output, dssdev);
307 static void sdi_disconnect(struct omap_dss_device *dssdev,
308 struct omap_dss_device *dst)
310 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
312 WARN_ON(dst != dssdev->dst);
314 if (dst != dssdev->dst)
317 omapdss_output_unset_device(dssdev);
319 dss_mgr_disconnect(&sdi->output, dssdev);
322 static const struct omapdss_sdi_ops sdi_ops = {
323 .connect = sdi_connect,
324 .disconnect = sdi_disconnect,
326 .enable = sdi_display_enable,
327 .disable = sdi_display_disable,
329 .check_timings = sdi_check_timings,
330 .set_timings = sdi_set_timings,
331 .get_timings = sdi_get_timings,
334 static void sdi_init_output(struct sdi_device *sdi)
336 struct omap_dss_device *out = &sdi->output;
338 out->dev = &sdi->pdev->dev;
339 out->id = OMAP_DSS_OUTPUT_SDI;
340 out->output_type = OMAP_DISPLAY_TYPE_SDI;
342 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
343 /* We have SDI only on OMAP3, where it's on port 1 */
345 out->ops.sdi = &sdi_ops;
346 out->owner = THIS_MODULE;
348 omapdss_register_output(out);
351 static void sdi_uninit_output(struct sdi_device *sdi)
353 omapdss_unregister_output(&sdi->output);
356 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
357 struct device_node *port)
359 struct sdi_device *sdi;
360 struct device_node *ep;
364 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
368 ep = of_get_next_child(port, NULL);
374 r = of_property_read_u32(ep, "datapairs", &datapairs);
376 DSSERR("failed to parse datapairs\n");
380 sdi->datapairs = datapairs;
388 sdi_init_output(sdi);
400 void sdi_uninit_port(struct device_node *port)
402 struct sdi_device *sdi = port->data;
407 sdi_uninit_output(sdi);