drivers/gpu/drm/omapdrm/dss/video-pll.c

   1 /*
   2 * Copyright (C) 2014 Texas Instruments Ltd
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms of the GNU General Public License version 2 as published by
   6 * the Free Software Foundation.
   7 *
   8 * You should have received a copy of the GNU General Public License along with
   9 * this program.  If not, see <http://www.gnu.org/licenses/>.
  10 */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/sched.h>
  19
  20 #include "omapdss.h"
  21 #include "dss.h"
  22
  23 struct dss_video_pll {
  24         struct dss_pll pll;
  25
  26         struct device *dev;
  27
  28         void __iomem *clkctrl_base;
  29 };
  30
  31 #define REG_MOD(reg, val, start, end) \
  32         writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
  33
  34 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
  35 {
  36         REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
  37 }
  38
  39 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
  40 {
  41         REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
  42 }
  43
  44 static void dss_dpll_power_enable(struct dss_video_pll *vpll)
  45 {
  46         REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
  47
  48         /*
  49          * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
  50          * so we have to use fixed delay here.
  51          */
  52         msleep(1);
  53 }
  54
  55 static void dss_dpll_power_disable(struct dss_video_pll *vpll)
  56 {
  57         REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
  58 }
  59
  60 static int dss_video_pll_enable(struct dss_pll *pll)
  61 {
  62         struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
  63         int r;
  64
  65         r = dss_runtime_get();
  66         if (r)
  67                 return r;
  68
  69         dss_ctrl_pll_enable(pll->id, true);
  70
  71         dss_dpll_enable_scp_clk(vpll);
  72
  73         r = dss_pll_wait_reset_done(pll);
  74         if (r)
  75                 goto err_reset;
  76
  77         dss_dpll_power_enable(vpll);
  78
  79         return 0;
  80
  81 err_reset:
  82         dss_dpll_disable_scp_clk(vpll);
  83         dss_ctrl_pll_enable(pll->id, false);
  84         dss_runtime_put();
  85
  86         return r;
  87 }
  88
  89 static void dss_video_pll_disable(struct dss_pll *pll)
  90 {
  91         struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
  92
  93         dss_dpll_power_disable(vpll);
  94
  95         dss_dpll_disable_scp_clk(vpll);
  96
  97         dss_ctrl_pll_enable(pll->id, false);
  98
  99         dss_runtime_put();
 100 }
 101
 102 static const struct dss_pll_ops dss_pll_ops = {
 103         .enable = dss_video_pll_enable,
 104         .disable = dss_video_pll_disable,
 105         .set_config = dss_pll_write_config_type_a,
 106 };
 107
 108 static const struct dss_pll_hw dss_dra7_video_pll_hw = {
 109         .type = DSS_PLL_TYPE_A,
 110
 111         .n_max = (1 << 8) - 1,
 112         .m_max = (1 << 12) - 1,
 113         .mX_max = (1 << 5) - 1,
 114         .fint_min = 500000,
 115         .fint_max = 2500000,
 116         .clkdco_max = 1800000000,
 117
 118         .n_msb = 8,
 119         .n_lsb = 1,
 120         .m_msb = 20,
 121         .m_lsb = 9,
 122
 123         .mX_msb[0] = 25,
 124         .mX_lsb[0] = 21,
 125         .mX_msb[1] = 30,
 126         .mX_lsb[1] = 26,
 127         .mX_msb[2] = 4,
 128         .mX_lsb[2] = 0,
 129         .mX_msb[3] = 9,
 130         .mX_lsb[3] = 5,
 131
 132         .has_refsel = true,
 133
 134         .errata_i886 = true,
 135 };
 136
 137 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
 138         struct regulator *regulator)
 139 {
 140         const char * const reg_name[] = { "pll1", "pll2" };
 141         const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
 142         const char * const clkin_name[] = { "video1_clk", "video2_clk" };
 143
 144         struct resource *res;
 145         struct dss_video_pll *vpll;
 146         void __iomem *pll_base, *clkctrl_base;
 147         struct clk *clk;
 148         struct dss_pll *pll;
 149         int r;
 150
 151         /* PLL CONTROL */
 152
 153         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]);
 154         pll_base = devm_ioremap_resource(&pdev->dev, res);
 155         if (IS_ERR(pll_base))
 156                 return ERR_CAST(pll_base);
 157
 158         /* CLOCK CONTROL */
 159
 160         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 161                 clkctrl_name[id]);
 162         clkctrl_base = devm_ioremap_resource(&pdev->dev, res);
 163         if (IS_ERR(clkctrl_base))
 164                 return ERR_CAST(clkctrl_base);
 165
 166         /* CLKIN */
 167
 168         clk = devm_clk_get(&pdev->dev, clkin_name[id]);
 169         if (IS_ERR(clk)) {
 170                 DSSERR("can't get video pll clkin\n");
 171                 return ERR_CAST(clk);
 172         }
 173
 174         vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
 175         if (!vpll)
 176                 return ERR_PTR(-ENOMEM);
 177
 178         vpll->dev = &pdev->dev;
 179         vpll->clkctrl_base = clkctrl_base;
 180
 181         pll = &vpll->pll;
 182
 183         pll->name = id == 0 ? "video0" : "video1";
 184         pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
 185         pll->clkin = clk;
 186         pll->regulator = regulator;
 187         pll->base = pll_base;
 188         pll->hw = &dss_dra7_video_pll_hw;
 189         pll->ops = &dss_pll_ops;
 190
 191         r = dss_pll_register(pll);
 192         if (r)
 193                 return ERR_PTR(r);
 194
 195         return pll;
 196 }
 197
 198 void dss_video_pll_uninit(struct dss_pll *pll)
 199 {
 200         dss_pll_unregister(pll);
 201 }