drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

   1 /*
   2  * DMM IOMMU driver support functions for TI OMAP processors.
   3  *
   4  * Author: Rob Clark <rob@ti.com>
   5  *         Andy Gross <andy.gross@ti.com>
   6  *
   7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/list.h>
  26 #include <linux/mm.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h> /* platform_device() */
  29 #include <linux/sched.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/slab.h>
  32 #include <linux/time.h>
  33 #include <linux/vmalloc.h>
  34 #include <linux/wait.h>
  35
  36 #include "omap_dmm_tiler.h"
  37 #include "omap_dmm_priv.h"
  38
  39 #define DMM_DRIVER_NAME "dmm"
  40
  41 /* mappings for associating views to luts */
  42 static struct tcm *containers[TILFMT_NFORMATS];
  43 static struct dmm *omap_dmm;
  44
  45 #if defined(CONFIG_OF)
  46 static const struct of_device_id dmm_of_match[];
  47 #endif
  48
  49 /* global spinlock for protecting lists */
  50 static DEFINE_SPINLOCK(list_lock);
  51
  52 /* Geometry table */
  53 #define GEOM(xshift, yshift, bytes_per_pixel) { \
  54                 .x_shft = (xshift), \
  55                 .y_shft = (yshift), \
  56                 .cpp    = (bytes_per_pixel), \
  57                 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
  58                 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
  59         }
  60
  61 static const struct {
  62         uint32_t x_shft;        /* unused X-bits (as part of bpp) */
  63         uint32_t y_shft;        /* unused Y-bits (as part of bpp) */
  64         uint32_t cpp;           /* bytes/chars per pixel */
  65         uint32_t slot_w;        /* width of each slot (in pixels) */
  66         uint32_t slot_h;        /* height of each slot (in pixels) */
  67 } geom[TILFMT_NFORMATS] = {
  68         [TILFMT_8BIT]  = GEOM(0, 0, 1),
  69         [TILFMT_16BIT] = GEOM(0, 1, 2),
  70         [TILFMT_32BIT] = GEOM(1, 1, 4),
  71         [TILFMT_PAGE]  = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
  72 };
  73
  74
  75 /* lookup table for registers w/ per-engine instances */
  76 static const uint32_t reg[][4] = {
  77         [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
  78                         DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
  79         [PAT_DESCR]  = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
  80                         DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
  81 };
  82
  83 static u32 dmm_read(struct dmm *dmm, u32 reg)
  84 {
  85         return readl(dmm->base + reg);
  86 }
  87
  88 static void dmm_write(struct dmm *dmm, u32 val, u32 reg)
  89 {
  90         writel(val, dmm->base + reg);
  91 }
  92
  93 /* simple allocator to grab next 16 byte aligned memory from txn */
  94 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
  95 {
  96         void *ptr;
  97         struct refill_engine *engine = txn->engine_handle;
  98
  99         /* dmm programming requires 16 byte aligned addresses */
 100         txn->current_pa = round_up(txn->current_pa, 16);
 101         txn->current_va = (void *)round_up((long)txn->current_va, 16);
 102
 103         ptr = txn->current_va;
 104         *pa = txn->current_pa;
 105
 106         txn->current_pa += sz;
 107         txn->current_va += sz;
 108
 109         BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
 110
 111         return ptr;
 112 }
 113
 114 /* check status and spin until wait_mask comes true */
 115 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
 116 {
 117         struct dmm *dmm = engine->dmm;
 118         uint32_t r = 0, err, i;
 119
 120         i = DMM_FIXED_RETRY_COUNT;
 121         while (true) {
 122                 r = dmm_read(dmm, reg[PAT_STATUS][engine->id]);
 123                 err = r & DMM_PATSTATUS_ERR;
 124                 if (err)
 125                         return -EFAULT;
 126
 127                 if ((r & wait_mask) == wait_mask)
 128                         break;
 129
 130                 if (--i == 0)
 131                         return -ETIMEDOUT;
 132
 133                 udelay(1);
 134         }
 135
 136         return 0;
 137 }
 138
 139 static void release_engine(struct refill_engine *engine)
 140 {
 141         unsigned long flags;
 142
 143         spin_lock_irqsave(&list_lock, flags);
 144         list_add(&engine->idle_node, &omap_dmm->idle_head);
 145         spin_unlock_irqrestore(&list_lock, flags);
 146
 147         atomic_inc(&omap_dmm->engine_counter);
 148         wake_up_interruptible(&omap_dmm->engine_queue);
 149 }
 150
 151 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
 152 {
 153         struct dmm *dmm = arg;
 154         uint32_t status = dmm_read(dmm, DMM_PAT_IRQSTATUS);
 155         int i;
 156
 157         /* ack IRQ */
 158         dmm_write(dmm, status, DMM_PAT_IRQSTATUS);
 159
 160         for (i = 0; i < dmm->num_engines; i++) {
 161                 if (status & DMM_IRQSTAT_LST) {
 162                         if (dmm->engines[i].async)
 163                                 release_engine(&dmm->engines[i]);
 164
 165                         complete(&dmm->engines[i].compl);
 166                 }
 167
 168                 status >>= 8;
 169         }
 170
 171         return IRQ_HANDLED;
 172 }
 173
 174 /**
 175  * Get a handle for a DMM transaction
 176  */
 177 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
 178 {
 179         struct dmm_txn *txn = NULL;
 180         struct refill_engine *engine = NULL;
 181         int ret;
 182         unsigned long flags;
 183
 184
 185         /* wait until an engine is available */
 186         ret = wait_event_interruptible(omap_dmm->engine_queue,
 187                 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
 188         if (ret)
 189                 return ERR_PTR(ret);
 190
 191         /* grab an idle engine */
 192         spin_lock_irqsave(&list_lock, flags);
 193         if (!list_empty(&dmm->idle_head)) {
 194                 engine = list_entry(dmm->idle_head.next, struct refill_engine,
 195                                         idle_node);
 196                 list_del(&engine->idle_node);
 197         }
 198         spin_unlock_irqrestore(&list_lock, flags);
 199
 200         BUG_ON(!engine);
 201
 202         txn = &engine->txn;
 203         engine->tcm = tcm;
 204         txn->engine_handle = engine;
 205         txn->last_pat = NULL;
 206         txn->current_va = engine->refill_va;
 207         txn->current_pa = engine->refill_pa;
 208
 209         return txn;
 210 }
 211
 212 /**
 213  * Add region to DMM transaction.  If pages or pages[i] is NULL, then the
 214  * corresponding slot is cleared (ie. dummy_pa is programmed)
 215  */
 216 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
 217                 struct page **pages, uint32_t npages, uint32_t roll)
 218 {
 219         dma_addr_t pat_pa = 0, data_pa = 0;
 220         uint32_t *data;
 221         struct pat *pat;
 222         struct refill_engine *engine = txn->engine_handle;
 223         int columns = (1 + area->x1 - area->x0);
 224         int rows = (1 + area->y1 - area->y0);
 225         int i = columns*rows;
 226
 227         pat = alloc_dma(txn, sizeof(*pat), &pat_pa);
 228
 229         if (txn->last_pat)
 230                 txn->last_pat->next_pa = (uint32_t)pat_pa;
 231
 232         pat->area = *area;
 233
 234         /* adjust Y coordinates based off of container parameters */
 235         pat->area.y0 += engine->tcm->y_offset;
 236         pat->area.y1 += engine->tcm->y_offset;
 237
 238         pat->ctrl = (struct pat_ctrl){
 239                         .start = 1,
 240                         .lut_id = engine->tcm->lut_id,
 241                 };
 242
 243         data = alloc_dma(txn, 4*i, &data_pa);
 244         /* FIXME: what if data_pa is more than 32-bit ? */
 245         pat->data_pa = data_pa;
 246
 247         while (i--) {
 248                 int n = i + roll;
 249                 if (n >= npages)
 250                         n -= npages;
 251                 data[i] = (pages && pages[n]) ?
 252                         page_to_phys(pages[n]) : engine->dmm->dummy_pa;
 253         }
 254
 255         txn->last_pat = pat;
 256
 257         return;
 258 }
 259
 260 /**
 261  * Commit the DMM transaction.
 262  */
 263 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
 264 {
 265         int ret = 0;
 266         struct refill_engine *engine = txn->engine_handle;
 267         struct dmm *dmm = engine->dmm;
 268
 269         if (!txn->last_pat) {
 270                 dev_err(engine->dmm->dev, "need at least one txn\n");
 271                 ret = -EINVAL;
 272                 goto cleanup;
 273         }
 274
 275         txn->last_pat->next_pa = 0;
 276         /* ensure that the written descriptors are visible to DMM */
 277         wmb();
 278
 279         /*
 280          * NOTE: the wmb() above should be enough, but there seems to be a bug
 281          * in OMAP's memory barrier implementation, which in some rare cases may
 282          * cause the writes not to be observable after wmb().
 283          */
 284
 285         /* read back to ensure the data is in RAM */
 286         readl(&txn->last_pat->next_pa);
 287
 288         /* write to PAT_DESCR to clear out any pending transaction */
 289         dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);
 290
 291         /* wait for engine ready: */
 292         ret = wait_status(engine, DMM_PATSTATUS_READY);
 293         if (ret) {
 294                 ret = -EFAULT;
 295                 goto cleanup;
 296         }
 297
 298         /* mark whether it is async to denote list management in IRQ handler */
 299         engine->async = wait ? false : true;
 300         reinit_completion(&engine->compl);
 301         /* verify that the irq handler sees the 'async' and completion value */
 302         smp_mb();
 303
 304         /* kick reload */
 305         dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]);
 306
 307         if (wait) {
 308                 if (!wait_for_completion_timeout(&engine->compl,
 309                                 msecs_to_jiffies(100))) {
 310                         dev_err(dmm->dev, "timed out waiting for done\n");
 311                         ret = -ETIMEDOUT;
 312                         goto cleanup;
 313                 }
 314
 315                 /* Check the engine status before continue */
 316                 ret = wait_status(engine, DMM_PATSTATUS_READY |
 317                                   DMM_PATSTATUS_VALID | DMM_PATSTATUS_DONE);
 318         }
 319
 320 cleanup:
 321         /* only place engine back on list if we are done with it */
 322         if (ret || wait)
 323                 release_engine(engine);
 324
 325         return ret;
 326 }
 327
 328 /*
 329  * DMM programming
 330  */
 331 static int fill(struct tcm_area *area, struct page **pages,
 332                 uint32_t npages, uint32_t roll, bool wait)
 333 {
 334         int ret = 0;
 335         struct tcm_area slice, area_s;
 336         struct dmm_txn *txn;
 337
 338         /*
 339          * FIXME
 340          *
 341          * Asynchronous fill does not work reliably, as the driver does not
 342          * handle errors in the async code paths. The fill operation may
 343          * silently fail, leading to leaking DMM engines, which may eventually
 344          * lead to deadlock if we run out of DMM engines.
 345          *
 346          * For now, always set 'wait' so that we only use sync fills. Async
 347          * fills should be fixed, or alternatively we could decide to only
 348          * support sync fills and so the whole async code path could be removed.
 349          */
 350
 351         wait = true;
 352
 353         txn = dmm_txn_init(omap_dmm, area->tcm);
 354         if (IS_ERR_OR_NULL(txn))
 355                 return -ENOMEM;
 356
 357         tcm_for_each_slice(slice, *area, area_s) {
 358                 struct pat_area p_area = {
 359                                 .x0 = slice.p0.x,  .y0 = slice.p0.y,
 360                                 .x1 = slice.p1.x,  .y1 = slice.p1.y,
 361                 };
 362
 363                 dmm_txn_append(txn, &p_area, pages, npages, roll);
 364
 365                 roll += tcm_sizeof(slice);
 366         }
 367
 368         ret = dmm_txn_commit(txn, wait);
 369
 370         return ret;
 371 }
 372
 373 /*
 374  * Pin/unpin
 375  */
 376
 377 /* note: slots for which pages[i] == NULL are filled w/ dummy page
 378  */
 379 int tiler_pin(struct tiler_block *block, struct page **pages,
 380                 uint32_t npages, uint32_t roll, bool wait)
 381 {
 382         int ret;
 383
 384         ret = fill(&block->area, pages, npages, roll, wait);
 385
 386         if (ret)
 387                 tiler_unpin(block);
 388
 389         return ret;
 390 }
 391
 392 int tiler_unpin(struct tiler_block *block)
 393 {
 394         return fill(&block->area, NULL, 0, 0, false);
 395 }
 396
 397 /*
 398  * Reserve/release
 399  */
 400 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
 401                 uint16_t h, uint16_t align)
 402 {
 403         struct tiler_block *block;
 404         u32 min_align = 128;
 405         int ret;
 406         unsigned long flags;
 407         u32 slot_bytes;
 408
 409         block = kzalloc(sizeof(*block), GFP_KERNEL);
 410         if (!block)
 411                 return ERR_PTR(-ENOMEM);
 412
 413         BUG_ON(!validfmt(fmt));
 414
 415         /* convert width/height to slots */
 416         w = DIV_ROUND_UP(w, geom[fmt].slot_w);
 417         h = DIV_ROUND_UP(h, geom[fmt].slot_h);
 418
 419         /* convert alignment to slots */
 420         slot_bytes = geom[fmt].slot_w * geom[fmt].cpp;
 421         min_align = max(min_align, slot_bytes);
 422         align = (align > min_align) ? ALIGN(align, min_align) : min_align;
 423         align /= slot_bytes;
 424
 425         block->fmt = fmt;
 426
 427         ret = tcm_reserve_2d(containers[fmt], w, h, align, -1, slot_bytes,
 428                         &block->area);
 429         if (ret) {
 430                 kfree(block);
 431                 return ERR_PTR(-ENOMEM);
 432         }
 433
 434         /* add to allocation list */
 435         spin_lock_irqsave(&list_lock, flags);
 436         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 437         spin_unlock_irqrestore(&list_lock, flags);
 438
 439         return block;
 440 }
 441
 442 struct tiler_block *tiler_reserve_1d(size_t size)
 443 {
 444         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 445         int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 446         unsigned long flags;
 447
 448         if (!block)
 449                 return ERR_PTR(-ENOMEM);
 450
 451         block->fmt = TILFMT_PAGE;
 452
 453         if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
 454                                 &block->area)) {
 455                 kfree(block);
 456                 return ERR_PTR(-ENOMEM);
 457         }
 458
 459         spin_lock_irqsave(&list_lock, flags);
 460         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 461         spin_unlock_irqrestore(&list_lock, flags);
 462
 463         return block;
 464 }
 465
 466 /* note: if you have pin'd pages, you should have already unpin'd first! */
 467 int tiler_release(struct tiler_block *block)
 468 {
 469         int ret = tcm_free(&block->area);
 470         unsigned long flags;
 471
 472         if (block->area.tcm)
 473                 dev_err(omap_dmm->dev, "failed to release block\n");
 474
 475         spin_lock_irqsave(&list_lock, flags);
 476         list_del(&block->alloc_node);
 477         spin_unlock_irqrestore(&list_lock, flags);
 478
 479         kfree(block);
 480         return ret;
 481 }
 482
 483 /*
 484  * Utils
 485  */
 486
 487 /* calculate the tiler space address of a pixel in a view orientation...
 488  * below description copied from the display subsystem section of TRM:
 489  *
 490  * When the TILER is addressed, the bits:
 491  *   [28:27] = 0x0 for 8-bit tiled
 492  *             0x1 for 16-bit tiled
 493  *             0x2 for 32-bit tiled
 494  *             0x3 for page mode
 495  *   [31:29] = 0x0 for 0-degree view
 496  *             0x1 for 180-degree view + mirroring
 497  *             0x2 for 0-degree view + mirroring
 498  *             0x3 for 180-degree view
 499  *             0x4 for 270-degree view + mirroring
 500  *             0x5 for 270-degree view
 501  *             0x6 for 90-degree view
 502  *             0x7 for 90-degree view + mirroring
 503  * Otherwise the bits indicated the corresponding bit address to access
 504  * the SDRAM.
 505  */
 506 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
 507 {
 508         u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
 509
 510         x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
 511         y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
 512         alignment = geom[fmt].x_shft + geom[fmt].y_shft;
 513
 514         /* validate coordinate */
 515         x_mask = MASK(x_bits);
 516         y_mask = MASK(y_bits);
 517
 518         if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
 519                 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
 520                                 x, x, x_mask, y, y, y_mask);
 521                 return 0;
 522         }
 523
 524         /* account for mirroring */
 525         if (orient & MASK_X_INVERT)
 526                 x ^= x_mask;
 527         if (orient & MASK_Y_INVERT)
 528                 y ^= y_mask;
 529
 530         /* get coordinate address */
 531         if (orient & MASK_XY_FLIP)
 532                 tmp = ((x << y_bits) + y);
 533         else
 534                 tmp = ((y << x_bits) + x);
 535
 536         return TIL_ADDR((tmp << alignment), orient, fmt);
 537 }
 538
 539 dma_addr_t tiler_ssptr(struct tiler_block *block)
 540 {
 541         BUG_ON(!validfmt(block->fmt));
 542
 543         return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
 544                         block->area.p0.x * geom[block->fmt].slot_w,
 545                         block->area.p0.y * geom[block->fmt].slot_h);
 546 }
 547
 548 dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,
 549                 uint32_t x, uint32_t y)
 550 {
 551         struct tcm_pt *p = &block->area.p0;
 552         BUG_ON(!validfmt(block->fmt));
 553
 554         return tiler_get_address(block->fmt, orient,
 555                         (p->x * geom[block->fmt].slot_w) + x,
 556                         (p->y * geom[block->fmt].slot_h) + y);
 557 }
 558
 559 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
 560 {
 561         BUG_ON(!validfmt(fmt));
 562         *w = round_up(*w, geom[fmt].slot_w);
 563         *h = round_up(*h, geom[fmt].slot_h);
 564 }
 565
 566 uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)
 567 {
 568         BUG_ON(!validfmt(fmt));
 569
 570         if (orient & MASK_XY_FLIP)
 571                 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
 572         else
 573                 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
 574 }
 575
 576 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 577 {
 578         tiler_align(fmt, &w, &h);
 579         return geom[fmt].cpp * w * h;
 580 }
 581
 582 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 583 {
 584         BUG_ON(!validfmt(fmt));
 585         return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
 586 }
 587
 588 uint32_t tiler_get_cpu_cache_flags(void)
 589 {
 590         return omap_dmm->plat_data->cpu_cache_flags;
 591 }
 592
 593 bool dmm_is_available(void)
 594 {
 595         return omap_dmm ? true : false;
 596 }
 597
 598 static int omap_dmm_remove(struct platform_device *dev)
 599 {
 600         struct tiler_block *block, *_block;
 601         int i;
 602         unsigned long flags;
 603
 604         if (omap_dmm) {
 605                 /* free all area regions */
 606                 spin_lock_irqsave(&list_lock, flags);
 607                 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
 608                                         alloc_node) {
 609                         list_del(&block->alloc_node);
 610                         kfree(block);
 611                 }
 612                 spin_unlock_irqrestore(&list_lock, flags);
 613
 614                 for (i = 0; i < omap_dmm->num_lut; i++)
 615                         if (omap_dmm->tcm && omap_dmm->tcm[i])
 616                                 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
 617                 kfree(omap_dmm->tcm);
 618
 619                 kfree(omap_dmm->engines);
 620                 if (omap_dmm->refill_va)
 621                         dma_free_wc(omap_dmm->dev,
 622                                     REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 623                                     omap_dmm->refill_va, omap_dmm->refill_pa);
 624                 if (omap_dmm->dummy_page)
 625                         __free_page(omap_dmm->dummy_page);
 626
 627                 if (omap_dmm->irq > 0)
 628                         free_irq(omap_dmm->irq, omap_dmm);
 629
 630                 iounmap(omap_dmm->base);
 631                 kfree(omap_dmm);
 632                 omap_dmm = NULL;
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int omap_dmm_probe(struct platform_device *dev)
 639 {
 640         int ret = -EFAULT, i;
 641         struct tcm_area area = {0};
 642         u32 hwinfo, pat_geom;
 643         struct resource *mem;
 644
 645         omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
 646         if (!omap_dmm)
 647                 goto fail;
 648
 649         /* initialize lists */
 650         INIT_LIST_HEAD(&omap_dmm->alloc_head);
 651         INIT_LIST_HEAD(&omap_dmm->idle_head);
 652
 653         init_waitqueue_head(&omap_dmm->engine_queue);
 654
 655         if (dev->dev.of_node) {
 656                 const struct of_device_id *match;
 657
 658                 match = of_match_node(dmm_of_match, dev->dev.of_node);
 659                 if (!match) {
 660                         dev_err(&dev->dev, "failed to find matching device node\n");
 661                         ret = -ENODEV;
 662                         goto fail;
 663                 }
 664
 665                 omap_dmm->plat_data = match->data;
 666         }
 667
 668         /* lookup hwmod data - base address and irq */
 669         mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
 670         if (!mem) {
 671                 dev_err(&dev->dev, "failed to get base address resource\n");
 672                 goto fail;
 673         }
 674
 675         omap_dmm->base = ioremap(mem->start, SZ_2K);
 676
 677         if (!omap_dmm->base) {
 678                 dev_err(&dev->dev, "failed to get dmm base address\n");
 679                 goto fail;
 680         }
 681
 682         omap_dmm->irq = platform_get_irq(dev, 0);
 683         if (omap_dmm->irq < 0) {
 684                 dev_err(&dev->dev, "failed to get IRQ resource\n");
 685                 goto fail;
 686         }
 687
 688         omap_dmm->dev = &dev->dev;
 689
 690         hwinfo = dmm_read(omap_dmm, DMM_PAT_HWINFO);
 691         omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
 692         omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
 693         omap_dmm->container_width = 256;
 694         omap_dmm->container_height = 128;
 695
 696         atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
 697
 698         /* read out actual LUT width and height */
 699         pat_geom = dmm_read(omap_dmm, DMM_PAT_GEOMETRY);
 700         omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
 701         omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
 702
 703         /* increment LUT by one if on OMAP5 */
 704         /* LUT has twice the height, and is split into a separate container */
 705         if (omap_dmm->lut_height != omap_dmm->container_height)
 706                 omap_dmm->num_lut++;
 707
 708         /* initialize DMM registers */
 709         dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__0);
 710         dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__1);
 711         dmm_write(omap_dmm, 0x80808080, DMM_PAT_VIEW_MAP__0);
 712         dmm_write(omap_dmm, 0x80000000, DMM_PAT_VIEW_MAP_BASE);
 713         dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__0);
 714         dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__1);
 715
 716         ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
 717                                 "omap_dmm_irq_handler", omap_dmm);
 718
 719         if (ret) {
 720                 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
 721                         omap_dmm->irq, ret);
 722                 omap_dmm->irq = -1;
 723                 goto fail;
 724         }
 725
 726         /* Enable all interrupts for each refill engine except
 727          * ERR_LUT_MISS<n> (which is just advisory, and we don't care
 728          * about because we want to be able to refill live scanout
 729          * buffers for accelerated pan/scroll) and FILL_DSC<n> which
 730          * we just generally don't care about.
 731          */
 732         dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_SET);
 733
 734         omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
 735         if (!omap_dmm->dummy_page) {
 736                 dev_err(&dev->dev, "could not allocate dummy page\n");
 737                 ret = -ENOMEM;
 738                 goto fail;
 739         }
 740
 741         /* set dma mask for device */
 742         ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 743         if (ret)
 744                 goto fail;
 745
 746         omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
 747
 748         /* alloc refill memory */
 749         omap_dmm->refill_va = dma_alloc_wc(&dev->dev,
 750                                            REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 751                                            &omap_dmm->refill_pa, GFP_KERNEL);
 752         if (!omap_dmm->refill_va) {
 753                 dev_err(&dev->dev, "could not allocate refill memory\n");
 754                 ret = -ENOMEM;
 755                 goto fail;
 756         }
 757
 758         /* alloc engines */
 759         omap_dmm->engines = kcalloc(omap_dmm->num_engines,
 760                                     sizeof(*omap_dmm->engines), GFP_KERNEL);
 761         if (!omap_dmm->engines) {
 762                 ret = -ENOMEM;
 763                 goto fail;
 764         }
 765
 766         for (i = 0; i < omap_dmm->num_engines; i++) {
 767                 omap_dmm->engines[i].id = i;
 768                 omap_dmm->engines[i].dmm = omap_dmm;
 769                 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
 770                                                 (REFILL_BUFFER_SIZE * i);
 771                 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
 772                                                 (REFILL_BUFFER_SIZE * i);
 773                 init_completion(&omap_dmm->engines[i].compl);
 774
 775                 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
 776         }
 777
 778         omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm),
 779                                 GFP_KERNEL);
 780         if (!omap_dmm->tcm) {
 781                 ret = -ENOMEM;
 782                 goto fail;
 783         }
 784
 785         /* init containers */
 786         /* Each LUT is associated with a TCM (container manager).  We use the
 787            lut_id to denote the lut_id used to identify the correct LUT for
 788            programming during reill operations */
 789         for (i = 0; i < omap_dmm->num_lut; i++) {
 790                 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
 791                                                 omap_dmm->container_height);
 792
 793                 if (!omap_dmm->tcm[i]) {
 794                         dev_err(&dev->dev, "failed to allocate container\n");
 795                         ret = -ENOMEM;
 796                         goto fail;
 797                 }
 798
 799                 omap_dmm->tcm[i]->lut_id = i;
 800         }
 801
 802         /* assign access mode containers to applicable tcm container */
 803         /* OMAP 4 has 1 container for all 4 views */
 804         /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */
 805         containers[TILFMT_8BIT] = omap_dmm->tcm[0];
 806         containers[TILFMT_16BIT] = omap_dmm->tcm[0];
 807         containers[TILFMT_32BIT] = omap_dmm->tcm[0];
 808
 809         if (omap_dmm->container_height != omap_dmm->lut_height) {
 810                 /* second LUT is used for PAGE mode.  Programming must use
 811                    y offset that is added to all y coordinates.  LUT id is still
 812                    0, because it is the same LUT, just the upper 128 lines */
 813                 containers[TILFMT_PAGE] = omap_dmm->tcm[1];
 814                 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET;
 815                 omap_dmm->tcm[1]->lut_id = 0;
 816         } else {
 817                 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
 818         }
 819
 820         area = (struct tcm_area) {
 821                 .tcm = NULL,
 822                 .p1.x = omap_dmm->container_width - 1,
 823                 .p1.y = omap_dmm->container_height - 1,
 824         };
 825
 826         /* initialize all LUTs to dummy page entries */
 827         for (i = 0; i < omap_dmm->num_lut; i++) {
 828                 area.tcm = omap_dmm->tcm[i];
 829                 if (fill(&area, NULL, 0, 0, true))
 830                         dev_err(omap_dmm->dev, "refill failed");
 831         }
 832
 833         dev_info(omap_dmm->dev, "initialized all PAT entries\n");
 834
 835         return 0;
 836
 837 fail:
 838         if (omap_dmm_remove(dev))
 839                 dev_err(&dev->dev, "cleanup failed\n");
 840         return ret;
 841 }
 842
 843 /*
 844  * debugfs support
 845  */
 846
 847 #ifdef CONFIG_DEBUG_FS
 848
 849 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
 850                                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
 851 static const char *special = ".,:;'\"`~!^-+";
 852
 853 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
 854                                                         char c, bool ovw)
 855 {
 856         int x, y;
 857         for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
 858                 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
 859                         if (map[y][x] == ' ' || ovw)
 860                                 map[y][x] = c;
 861 }
 862
 863 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
 864                                                                         char c)
 865 {
 866         map[p->y / ydiv][p->x / xdiv] = c;
 867 }
 868
 869 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
 870 {
 871         return map[p->y / ydiv][p->x / xdiv];
 872 }
 873
 874 static int map_width(int xdiv, int x0, int x1)
 875 {
 876         return (x1 / xdiv) - (x0 / xdiv) + 1;
 877 }
 878
 879 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
 880 {
 881         char *p = map[yd] + (x0 / xdiv);
 882         int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
 883         if (w >= 0) {
 884                 p += w;
 885                 while (*nice)
 886                         *p++ = *nice++;
 887         }
 888 }
 889
 890 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
 891                                                         struct tcm_area *a)
 892 {
 893         sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
 894         if (a->p0.y + 1 < a->p1.y) {
 895                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
 896                                                         256 - 1);
 897         } else if (a->p0.y < a->p1.y) {
 898                 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
 899                         text_map(map, xdiv, nice, a->p0.y / ydiv,
 900                                         a->p0.x + xdiv, 256 - 1);
 901                 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
 902                         text_map(map, xdiv, nice, a->p1.y / ydiv,
 903                                         0, a->p1.y - xdiv);
 904         } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
 905                 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
 906         }
 907 }
 908
 909 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
 910                                                         struct tcm_area *a)
 911 {
 912         sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
 913         if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
 914                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
 915                                                         a->p0.x, a->p1.x);
 916 }
 917
 918 int tiler_map_show(struct seq_file *s, void *arg)
 919 {
 920         int xdiv = 2, ydiv = 1;
 921         char **map = NULL, *global_map;
 922         struct tiler_block *block;
 923         struct tcm_area a, p;
 924         int i;
 925         const char *m2d = alphabet;
 926         const char *a2d = special;
 927         const char *m2dp = m2d, *a2dp = a2d;
 928         char nice[128];
 929         int h_adj;
 930         int w_adj;
 931         unsigned long flags;
 932         int lut_idx;
 933
 934
 935         if (!omap_dmm) {
 936                 /* early return if dmm/tiler device is not initialized */
 937                 return 0;
 938         }
 939
 940         h_adj = omap_dmm->container_height / ydiv;
 941         w_adj = omap_dmm->container_width / xdiv;
 942
 943         map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL);
 944         global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL);
 945
 946         if (!map || !global_map)
 947                 goto error;
 948
 949         for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) {
 950                 memset(map, 0, h_adj * sizeof(*map));
 951                 memset(global_map, ' ', (w_adj + 1) * h_adj);
 952
 953                 for (i = 0; i < omap_dmm->container_height; i++) {
 954                         map[i] = global_map + i * (w_adj + 1);
 955                         map[i][w_adj] = 0;
 956                 }
 957
 958                 spin_lock_irqsave(&list_lock, flags);
 959
 960                 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
 961                         if (block->area.tcm == omap_dmm->tcm[lut_idx]) {
 962                                 if (block->fmt != TILFMT_PAGE) {
 963                                         fill_map(map, xdiv, ydiv, &block->area,
 964                                                 *m2dp, true);
 965                                         if (!*++a2dp)
 966                                                 a2dp = a2d;
 967                                         if (!*++m2dp)
 968                                                 m2dp = m2d;
 969                                         map_2d_info(map, xdiv, ydiv, nice,
 970                                                         &block->area);
 971                                 } else {
 972                                         bool start = read_map_pt(map, xdiv,
 973                                                 ydiv, &block->area.p0) == ' ';
 974                                         bool end = read_map_pt(map, xdiv, ydiv,
 975                                                         &block->area.p1) == ' ';
 976
 977                                         tcm_for_each_slice(a, block->area, p)
 978                                                 fill_map(map, xdiv, ydiv, &a,
 979                                                         '=', true);
 980                                         fill_map_pt(map, xdiv, ydiv,
 981                                                         &block->area.p0,
 982                                                         start ? '<' : 'X');
 983                                         fill_map_pt(map, xdiv, ydiv,
 984                                                         &block->area.p1,
 985                                                         end ? '>' : 'X');
 986                                         map_1d_info(map, xdiv, ydiv, nice,
 987                                                         &block->area);
 988                                 }
 989                         }
 990                 }
 991
 992                 spin_unlock_irqrestore(&list_lock, flags);
 993
 994                 if (s) {
 995                         seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx);
 996                         for (i = 0; i < 128; i++)
 997                                 seq_printf(s, "%03d:%s\n", i, map[i]);
 998                         seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx);
 999                 } else {
1000                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n",
1001                                 lut_idx);
1002                         for (i = 0; i < 128; i++)
1003                                 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
1004                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n",
1005                                 lut_idx);
1006                 }
1007         }
1008
1009 error:
1010         kfree(map);
1011         kfree(global_map);
1012
1013         return 0;
1014 }
1015 #endif
1016
1017 #ifdef CONFIG_PM_SLEEP
1018 static int omap_dmm_resume(struct device *dev)
1019 {
1020         struct tcm_area area;
1021         int i;
1022
1023         if (!omap_dmm)
1024                 return -ENODEV;
1025
1026         area = (struct tcm_area) {
1027                 .tcm = NULL,
1028                 .p1.x = omap_dmm->container_width - 1,
1029                 .p1.y = omap_dmm->container_height - 1,
1030         };
1031
1032         /* initialize all LUTs to dummy page entries */
1033         for (i = 0; i < omap_dmm->num_lut; i++) {
1034                 area.tcm = omap_dmm->tcm[i];
1035                 if (fill(&area, NULL, 0, 0, true))
1036                         dev_err(dev, "refill failed");
1037         }
1038
1039         return 0;
1040 }
1041 #endif
1042
1043 static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
1044
1045 #if defined(CONFIG_OF)
1046 static const struct dmm_platform_data dmm_omap4_platform_data = {
1047         .cpu_cache_flags = OMAP_BO_WC,
1048 };
1049
1050 static const struct dmm_platform_data dmm_omap5_platform_data = {
1051         .cpu_cache_flags = OMAP_BO_UNCACHED,
1052 };
1053
1054 static const struct of_device_id dmm_of_match[] = {
1055         {
1056                 .compatible = "ti,omap4-dmm",
1057                 .data = &dmm_omap4_platform_data,
1058         },
1059         {
1060                 .compatible = "ti,omap5-dmm",
1061                 .data = &dmm_omap5_platform_data,
1062         },
1063         {},
1064 };
1065 #endif
1066
1067 struct platform_driver omap_dmm_driver = {
1068         .probe = omap_dmm_probe,
1069         .remove = omap_dmm_remove,
1070         .driver = {
1071                 .owner = THIS_MODULE,
1072                 .name = DMM_DRIVER_NAME,
1073                 .of_match_table = of_match_ptr(dmm_of_match),
1074                 .pm = &omap_dmm_pm_ops,
1075         },
1076 };
1077
1078 MODULE_LICENSE("GPL v2");
1079 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
1080 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");