drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

   1 /*
   2  * DMM IOMMU driver support functions for TI OMAP processors.
   3  *
   4  * Author: Rob Clark <rob@ti.com>
   5  *         Andy Gross <andy.gross@ti.com>
   6  *
   7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/list.h>
  26 #include <linux/mm.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h> /* platform_device() */
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/time.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/wait.h>
  34
  35 #include "omap_dmm_tiler.h"
  36 #include "omap_dmm_priv.h"
  37
  38 #define DMM_DRIVER_NAME "dmm"
  39
  40 /* mappings for associating views to luts */
  41 static struct tcm *containers[TILFMT_NFORMATS];
  42 static struct dmm *omap_dmm;
  43
  44 #if defined(CONFIG_OF)
  45 static const struct of_device_id dmm_of_match[];
  46 #endif
  47
  48 /* global spinlock for protecting lists */
  49 static DEFINE_SPINLOCK(list_lock);
  50
  51 /* Geometry table */
  52 #define GEOM(xshift, yshift, bytes_per_pixel) { \
  53                 .x_shft = (xshift), \
  54                 .y_shft = (yshift), \
  55                 .cpp    = (bytes_per_pixel), \
  56                 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
  57                 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
  58         }
  59
  60 static const struct {
  61         uint32_t x_shft;        /* unused X-bits (as part of bpp) */
  62         uint32_t y_shft;        /* unused Y-bits (as part of bpp) */
  63         uint32_t cpp;           /* bytes/chars per pixel */
  64         uint32_t slot_w;        /* width of each slot (in pixels) */
  65         uint32_t slot_h;        /* height of each slot (in pixels) */
  66 } geom[TILFMT_NFORMATS] = {
  67         [TILFMT_8BIT]  = GEOM(0, 0, 1),
  68         [TILFMT_16BIT] = GEOM(0, 1, 2),
  69         [TILFMT_32BIT] = GEOM(1, 1, 4),
  70         [TILFMT_PAGE]  = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
  71 };
  72
  73
  74 /* lookup table for registers w/ per-engine instances */
  75 static const uint32_t reg[][4] = {
  76         [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
  77                         DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
  78         [PAT_DESCR]  = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
  79                         DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
  80 };
  81
  82 /* simple allocator to grab next 16 byte aligned memory from txn */
  83 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
  84 {
  85         void *ptr;
  86         struct refill_engine *engine = txn->engine_handle;
  87
  88         /* dmm programming requires 16 byte aligned addresses */
  89         txn->current_pa = round_up(txn->current_pa, 16);
  90         txn->current_va = (void *)round_up((long)txn->current_va, 16);
  91
  92         ptr = txn->current_va;
  93         *pa = txn->current_pa;
  94
  95         txn->current_pa += sz;
  96         txn->current_va += sz;
  97
  98         BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
  99
 100         return ptr;
 101 }
 102
 103 /* check status and spin until wait_mask comes true */
 104 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
 105 {
 106         struct dmm *dmm = engine->dmm;
 107         uint32_t r = 0, err, i;
 108
 109         i = DMM_FIXED_RETRY_COUNT;
 110         while (true) {
 111                 r = readl(dmm->base + reg[PAT_STATUS][engine->id]);
 112                 err = r & DMM_PATSTATUS_ERR;
 113                 if (err)
 114                         return -EFAULT;
 115
 116                 if ((r & wait_mask) == wait_mask)
 117                         break;
 118
 119                 if (--i == 0)
 120                         return -ETIMEDOUT;
 121
 122                 udelay(1);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static void release_engine(struct refill_engine *engine)
 129 {
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&list_lock, flags);
 133         list_add(&engine->idle_node, &omap_dmm->idle_head);
 134         spin_unlock_irqrestore(&list_lock, flags);
 135
 136         atomic_inc(&omap_dmm->engine_counter);
 137         wake_up_interruptible(&omap_dmm->engine_queue);
 138 }
 139
 140 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
 141 {
 142         struct dmm *dmm = arg;
 143         uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS);
 144         int i;
 145
 146         /* ack IRQ */
 147         writel(status, dmm->base + DMM_PAT_IRQSTATUS);
 148
 149         for (i = 0; i < dmm->num_engines; i++) {
 150                 if (status & DMM_IRQSTAT_LST) {
 151                         if (dmm->engines[i].async)
 152                                 release_engine(&dmm->engines[i]);
 153
 154                         complete(&dmm->engines[i].compl);
 155                 }
 156
 157                 status >>= 8;
 158         }
 159
 160         return IRQ_HANDLED;
 161 }
 162
 163 /**
 164  * Get a handle for a DMM transaction
 165  */
 166 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
 167 {
 168         struct dmm_txn *txn = NULL;
 169         struct refill_engine *engine = NULL;
 170         int ret;
 171         unsigned long flags;
 172
 173
 174         /* wait until an engine is available */
 175         ret = wait_event_interruptible(omap_dmm->engine_queue,
 176                 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
 177         if (ret)
 178                 return ERR_PTR(ret);
 179
 180         /* grab an idle engine */
 181         spin_lock_irqsave(&list_lock, flags);
 182         if (!list_empty(&dmm->idle_head)) {
 183                 engine = list_entry(dmm->idle_head.next, struct refill_engine,
 184                                         idle_node);
 185                 list_del(&engine->idle_node);
 186         }
 187         spin_unlock_irqrestore(&list_lock, flags);
 188
 189         BUG_ON(!engine);
 190
 191         txn = &engine->txn;
 192         engine->tcm = tcm;
 193         txn->engine_handle = engine;
 194         txn->last_pat = NULL;
 195         txn->current_va = engine->refill_va;
 196         txn->current_pa = engine->refill_pa;
 197
 198         return txn;
 199 }
 200
 201 /**
 202  * Add region to DMM transaction.  If pages or pages[i] is NULL, then the
 203  * corresponding slot is cleared (ie. dummy_pa is programmed)
 204  */
 205 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
 206                 struct page **pages, uint32_t npages, uint32_t roll)
 207 {
 208         dma_addr_t pat_pa = 0, data_pa = 0;
 209         uint32_t *data;
 210         struct pat *pat;
 211         struct refill_engine *engine = txn->engine_handle;
 212         int columns = (1 + area->x1 - area->x0);
 213         int rows = (1 + area->y1 - area->y0);
 214         int i = columns*rows;
 215
 216         pat = alloc_dma(txn, sizeof(struct pat), &pat_pa);
 217
 218         if (txn->last_pat)
 219                 txn->last_pat->next_pa = (uint32_t)pat_pa;
 220
 221         pat->area = *area;
 222
 223         /* adjust Y coordinates based off of container parameters */
 224         pat->area.y0 += engine->tcm->y_offset;
 225         pat->area.y1 += engine->tcm->y_offset;
 226
 227         pat->ctrl = (struct pat_ctrl){
 228                         .start = 1,
 229                         .lut_id = engine->tcm->lut_id,
 230                 };
 231
 232         data = alloc_dma(txn, 4*i, &data_pa);
 233         /* FIXME: what if data_pa is more than 32-bit ? */
 234         pat->data_pa = data_pa;
 235
 236         while (i--) {
 237                 int n = i + roll;
 238                 if (n >= npages)
 239                         n -= npages;
 240                 data[i] = (pages && pages[n]) ?
 241                         page_to_phys(pages[n]) : engine->dmm->dummy_pa;
 242         }
 243
 244         txn->last_pat = pat;
 245
 246         return;
 247 }
 248
 249 /**
 250  * Commit the DMM transaction.
 251  */
 252 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
 253 {
 254         int ret = 0;
 255         struct refill_engine *engine = txn->engine_handle;
 256         struct dmm *dmm = engine->dmm;
 257
 258         if (!txn->last_pat) {
 259                 dev_err(engine->dmm->dev, "need at least one txn\n");
 260                 ret = -EINVAL;
 261                 goto cleanup;
 262         }
 263
 264         txn->last_pat->next_pa = 0;
 265         /* ensure that the written descriptors are visible to DMM */
 266         wmb();
 267
 268         /*
 269          * NOTE: the wmb() above should be enough, but there seems to be a bug
 270          * in OMAP's memory barrier implementation, which in some rare cases may
 271          * cause the writes not to be observable after wmb().
 272          */
 273
 274         /* read back to ensure the data is in RAM */
 275         readl(&txn->last_pat->next_pa);
 276
 277         /* write to PAT_DESCR to clear out any pending transaction */
 278         writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]);
 279
 280         /* wait for engine ready: */
 281         ret = wait_status(engine, DMM_PATSTATUS_READY);
 282         if (ret) {
 283                 ret = -EFAULT;
 284                 goto cleanup;
 285         }
 286
 287         /* mark whether it is async to denote list management in IRQ handler */
 288         engine->async = wait ? false : true;
 289         reinit_completion(&engine->compl);
 290         /* verify that the irq handler sees the 'async' and completion value */
 291         smp_mb();
 292
 293         /* kick reload */
 294         writel(engine->refill_pa,
 295                 dmm->base + reg[PAT_DESCR][engine->id]);
 296
 297         if (wait) {
 298                 if (!wait_for_completion_timeout(&engine->compl,
 299                                 msecs_to_jiffies(100))) {
 300                         dev_err(dmm->dev, "timed out waiting for done\n");
 301                         ret = -ETIMEDOUT;
 302                         goto cleanup;
 303                 }
 304
 305                 /* Check the engine status before continue */
 306                 ret = wait_status(engine, DMM_PATSTATUS_READY |
 307                                   DMM_PATSTATUS_VALID | DMM_PATSTATUS_DONE);
 308         }
 309
 310 cleanup:
 311         /* only place engine back on list if we are done with it */
 312         if (ret || wait)
 313                 release_engine(engine);
 314
 315         return ret;
 316 }
 317
 318 /*
 319  * DMM programming
 320  */
 321 static int fill(struct tcm_area *area, struct page **pages,
 322                 uint32_t npages, uint32_t roll, bool wait)
 323 {
 324         int ret = 0;
 325         struct tcm_area slice, area_s;
 326         struct dmm_txn *txn;
 327
 328         txn = dmm_txn_init(omap_dmm, area->tcm);
 329         if (IS_ERR_OR_NULL(txn))
 330                 return -ENOMEM;
 331
 332         tcm_for_each_slice(slice, *area, area_s) {
 333                 struct pat_area p_area = {
 334                                 .x0 = slice.p0.x,  .y0 = slice.p0.y,
 335                                 .x1 = slice.p1.x,  .y1 = slice.p1.y,
 336                 };
 337
 338                 dmm_txn_append(txn, &p_area, pages, npages, roll);
 339
 340                 roll += tcm_sizeof(slice);
 341         }
 342
 343         ret = dmm_txn_commit(txn, wait);
 344
 345         return ret;
 346 }
 347
 348 /*
 349  * Pin/unpin
 350  */
 351
 352 /* note: slots for which pages[i] == NULL are filled w/ dummy page
 353  */
 354 int tiler_pin(struct tiler_block *block, struct page **pages,
 355                 uint32_t npages, uint32_t roll, bool wait)
 356 {
 357         int ret;
 358
 359         ret = fill(&block->area, pages, npages, roll, wait);
 360
 361         if (ret)
 362                 tiler_unpin(block);
 363
 364         return ret;
 365 }
 366
 367 int tiler_unpin(struct tiler_block *block)
 368 {
 369         return fill(&block->area, NULL, 0, 0, false);
 370 }
 371
 372 /*
 373  * Reserve/release
 374  */
 375 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
 376                 uint16_t h, uint16_t align)
 377 {
 378         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 379         u32 min_align = 128;
 380         int ret;
 381         unsigned long flags;
 382
 383         BUG_ON(!validfmt(fmt));
 384
 385         /* convert width/height to slots */
 386         w = DIV_ROUND_UP(w, geom[fmt].slot_w);
 387         h = DIV_ROUND_UP(h, geom[fmt].slot_h);
 388
 389         /* convert alignment to slots */
 390         min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp));
 391         align = ALIGN(align, min_align);
 392         align /= geom[fmt].slot_w * geom[fmt].cpp;
 393
 394         block->fmt = fmt;
 395
 396         ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area);
 397         if (ret) {
 398                 kfree(block);
 399                 return ERR_PTR(-ENOMEM);
 400         }
 401
 402         /* add to allocation list */
 403         spin_lock_irqsave(&list_lock, flags);
 404         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 405         spin_unlock_irqrestore(&list_lock, flags);
 406
 407         return block;
 408 }
 409
 410 struct tiler_block *tiler_reserve_1d(size_t size)
 411 {
 412         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 413         int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 414         unsigned long flags;
 415
 416         if (!block)
 417                 return ERR_PTR(-ENOMEM);
 418
 419         block->fmt = TILFMT_PAGE;
 420
 421         if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
 422                                 &block->area)) {
 423                 kfree(block);
 424                 return ERR_PTR(-ENOMEM);
 425         }
 426
 427         spin_lock_irqsave(&list_lock, flags);
 428         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 429         spin_unlock_irqrestore(&list_lock, flags);
 430
 431         return block;
 432 }
 433
 434 /* note: if you have pin'd pages, you should have already unpin'd first! */
 435 int tiler_release(struct tiler_block *block)
 436 {
 437         int ret = tcm_free(&block->area);
 438         unsigned long flags;
 439
 440         if (block->area.tcm)
 441                 dev_err(omap_dmm->dev, "failed to release block\n");
 442
 443         spin_lock_irqsave(&list_lock, flags);
 444         list_del(&block->alloc_node);
 445         spin_unlock_irqrestore(&list_lock, flags);
 446
 447         kfree(block);
 448         return ret;
 449 }
 450
 451 /*
 452  * Utils
 453  */
 454
 455 /* calculate the tiler space address of a pixel in a view orientation...
 456  * below description copied from the display subsystem section of TRM:
 457  *
 458  * When the TILER is addressed, the bits:
 459  *   [28:27] = 0x0 for 8-bit tiled
 460  *             0x1 for 16-bit tiled
 461  *             0x2 for 32-bit tiled
 462  *             0x3 for page mode
 463  *   [31:29] = 0x0 for 0-degree view
 464  *             0x1 for 180-degree view + mirroring
 465  *             0x2 for 0-degree view + mirroring
 466  *             0x3 for 180-degree view
 467  *             0x4 for 270-degree view + mirroring
 468  *             0x5 for 270-degree view
 469  *             0x6 for 90-degree view
 470  *             0x7 for 90-degree view + mirroring
 471  * Otherwise the bits indicated the corresponding bit address to access
 472  * the SDRAM.
 473  */
 474 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
 475 {
 476         u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
 477
 478         x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
 479         y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
 480         alignment = geom[fmt].x_shft + geom[fmt].y_shft;
 481
 482         /* validate coordinate */
 483         x_mask = MASK(x_bits);
 484         y_mask = MASK(y_bits);
 485
 486         if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
 487                 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
 488                                 x, x, x_mask, y, y, y_mask);
 489                 return 0;
 490         }
 491
 492         /* account for mirroring */
 493         if (orient & MASK_X_INVERT)
 494                 x ^= x_mask;
 495         if (orient & MASK_Y_INVERT)
 496                 y ^= y_mask;
 497
 498         /* get coordinate address */
 499         if (orient & MASK_XY_FLIP)
 500                 tmp = ((x << y_bits) + y);
 501         else
 502                 tmp = ((y << x_bits) + x);
 503
 504         return TIL_ADDR((tmp << alignment), orient, fmt);
 505 }
 506
 507 dma_addr_t tiler_ssptr(struct tiler_block *block)
 508 {
 509         BUG_ON(!validfmt(block->fmt));
 510
 511         return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
 512                         block->area.p0.x * geom[block->fmt].slot_w,
 513                         block->area.p0.y * geom[block->fmt].slot_h);
 514 }
 515
 516 dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,
 517                 uint32_t x, uint32_t y)
 518 {
 519         struct tcm_pt *p = &block->area.p0;
 520         BUG_ON(!validfmt(block->fmt));
 521
 522         return tiler_get_address(block->fmt, orient,
 523                         (p->x * geom[block->fmt].slot_w) + x,
 524                         (p->y * geom[block->fmt].slot_h) + y);
 525 }
 526
 527 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
 528 {
 529         BUG_ON(!validfmt(fmt));
 530         *w = round_up(*w, geom[fmt].slot_w);
 531         *h = round_up(*h, geom[fmt].slot_h);
 532 }
 533
 534 uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)
 535 {
 536         BUG_ON(!validfmt(fmt));
 537
 538         if (orient & MASK_XY_FLIP)
 539                 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
 540         else
 541                 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
 542 }
 543
 544 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 545 {
 546         tiler_align(fmt, &w, &h);
 547         return geom[fmt].cpp * w * h;
 548 }
 549
 550 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 551 {
 552         BUG_ON(!validfmt(fmt));
 553         return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
 554 }
 555
 556 uint32_t tiler_get_cpu_cache_flags(void)
 557 {
 558         return omap_dmm->plat_data->cpu_cache_flags;
 559 }
 560
 561 bool dmm_is_available(void)
 562 {
 563         return omap_dmm ? true : false;
 564 }
 565
 566 static int omap_dmm_remove(struct platform_device *dev)
 567 {
 568         struct tiler_block *block, *_block;
 569         int i;
 570         unsigned long flags;
 571
 572         if (omap_dmm) {
 573                 /* free all area regions */
 574                 spin_lock_irqsave(&list_lock, flags);
 575                 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
 576                                         alloc_node) {
 577                         list_del(&block->alloc_node);
 578                         kfree(block);
 579                 }
 580                 spin_unlock_irqrestore(&list_lock, flags);
 581
 582                 for (i = 0; i < omap_dmm->num_lut; i++)
 583                         if (omap_dmm->tcm && omap_dmm->tcm[i])
 584                                 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
 585                 kfree(omap_dmm->tcm);
 586
 587                 kfree(omap_dmm->engines);
 588                 if (omap_dmm->refill_va)
 589                         dma_free_writecombine(omap_dmm->dev,
 590                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 591                                 omap_dmm->refill_va,
 592                                 omap_dmm->refill_pa);
 593                 if (omap_dmm->dummy_page)
 594                         __free_page(omap_dmm->dummy_page);
 595
 596                 if (omap_dmm->irq > 0)
 597                         free_irq(omap_dmm->irq, omap_dmm);
 598
 599                 iounmap(omap_dmm->base);
 600                 kfree(omap_dmm);
 601                 omap_dmm = NULL;
 602         }
 603
 604         return 0;
 605 }
 606
 607 static int omap_dmm_probe(struct platform_device *dev)
 608 {
 609         int ret = -EFAULT, i;
 610         struct tcm_area area = {0};
 611         u32 hwinfo, pat_geom;
 612         struct resource *mem;
 613
 614         omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
 615         if (!omap_dmm)
 616                 goto fail;
 617
 618         /* initialize lists */
 619         INIT_LIST_HEAD(&omap_dmm->alloc_head);
 620         INIT_LIST_HEAD(&omap_dmm->idle_head);
 621
 622         init_waitqueue_head(&omap_dmm->engine_queue);
 623
 624         if (dev->dev.of_node) {
 625                 const struct of_device_id *match;
 626
 627                 match = of_match_node(dmm_of_match, dev->dev.of_node);
 628                 if (!match) {
 629                         dev_err(&dev->dev, "failed to find matching device node\n");
 630                         ret = -ENODEV;
 631                         goto fail;
 632                 }
 633
 634                 omap_dmm->plat_data = match->data;
 635         }
 636
 637         /* lookup hwmod data - base address and irq */
 638         mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
 639         if (!mem) {
 640                 dev_err(&dev->dev, "failed to get base address resource\n");
 641                 goto fail;
 642         }
 643
 644         omap_dmm->base = ioremap(mem->start, SZ_2K);
 645
 646         if (!omap_dmm->base) {
 647                 dev_err(&dev->dev, "failed to get dmm base address\n");
 648                 goto fail;
 649         }
 650
 651         omap_dmm->irq = platform_get_irq(dev, 0);
 652         if (omap_dmm->irq < 0) {
 653                 dev_err(&dev->dev, "failed to get IRQ resource\n");
 654                 goto fail;
 655         }
 656
 657         omap_dmm->dev = &dev->dev;
 658
 659         hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO);
 660         omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
 661         omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
 662         omap_dmm->container_width = 256;
 663         omap_dmm->container_height = 128;
 664
 665         atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
 666
 667         /* read out actual LUT width and height */
 668         pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY);
 669         omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
 670         omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
 671
 672         /* increment LUT by one if on OMAP5 */
 673         /* LUT has twice the height, and is split into a separate container */
 674         if (omap_dmm->lut_height != omap_dmm->container_height)
 675                 omap_dmm->num_lut++;
 676
 677         /* initialize DMM registers */
 678         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0);
 679         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1);
 680         writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0);
 681         writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE);
 682         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0);
 683         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1);
 684
 685         ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
 686                                 "omap_dmm_irq_handler", omap_dmm);
 687
 688         if (ret) {
 689                 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
 690                         omap_dmm->irq, ret);
 691                 omap_dmm->irq = -1;
 692                 goto fail;
 693         }
 694
 695         /* Enable all interrupts for each refill engine except
 696          * ERR_LUT_MISS<n> (which is just advisory, and we don't care
 697          * about because we want to be able to refill live scanout
 698          * buffers for accelerated pan/scroll) and FILL_DSC<n> which
 699          * we just generally don't care about.
 700          */
 701         writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET);
 702
 703         omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
 704         if (!omap_dmm->dummy_page) {
 705                 dev_err(&dev->dev, "could not allocate dummy page\n");
 706                 ret = -ENOMEM;
 707                 goto fail;
 708         }
 709
 710         /* set dma mask for device */
 711         ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 712         if (ret)
 713                 goto fail;
 714
 715         omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
 716
 717         /* alloc refill memory */
 718         omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev,
 719                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 720                                 &omap_dmm->refill_pa, GFP_KERNEL);
 721         if (!omap_dmm->refill_va) {
 722                 dev_err(&dev->dev, "could not allocate refill memory\n");
 723                 ret = -ENOMEM;
 724                 goto fail;
 725         }
 726
 727         /* alloc engines */
 728         omap_dmm->engines = kcalloc(omap_dmm->num_engines,
 729                                     sizeof(struct refill_engine), GFP_KERNEL);
 730         if (!omap_dmm->engines) {
 731                 ret = -ENOMEM;
 732                 goto fail;
 733         }
 734
 735         for (i = 0; i < omap_dmm->num_engines; i++) {
 736                 omap_dmm->engines[i].id = i;
 737                 omap_dmm->engines[i].dmm = omap_dmm;
 738                 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
 739                                                 (REFILL_BUFFER_SIZE * i);
 740                 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
 741                                                 (REFILL_BUFFER_SIZE * i);
 742                 init_completion(&omap_dmm->engines[i].compl);
 743
 744                 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
 745         }
 746
 747         omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm),
 748                                 GFP_KERNEL);
 749         if (!omap_dmm->tcm) {
 750                 ret = -ENOMEM;
 751                 goto fail;
 752         }
 753
 754         /* init containers */
 755         /* Each LUT is associated with a TCM (container manager).  We use the
 756            lut_id to denote the lut_id used to identify the correct LUT for
 757            programming during reill operations */
 758         for (i = 0; i < omap_dmm->num_lut; i++) {
 759                 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
 760                                                 omap_dmm->container_height,
 761                                                 NULL);
 762
 763                 if (!omap_dmm->tcm[i]) {
 764                         dev_err(&dev->dev, "failed to allocate container\n");
 765                         ret = -ENOMEM;
 766                         goto fail;
 767                 }
 768
 769                 omap_dmm->tcm[i]->lut_id = i;
 770         }
 771
 772         /* assign access mode containers to applicable tcm container */
 773         /* OMAP 4 has 1 container for all 4 views */
 774         /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */
 775         containers[TILFMT_8BIT] = omap_dmm->tcm[0];
 776         containers[TILFMT_16BIT] = omap_dmm->tcm[0];
 777         containers[TILFMT_32BIT] = omap_dmm->tcm[0];
 778
 779         if (omap_dmm->container_height != omap_dmm->lut_height) {
 780                 /* second LUT is used for PAGE mode.  Programming must use
 781                    y offset that is added to all y coordinates.  LUT id is still
 782                    0, because it is the same LUT, just the upper 128 lines */
 783                 containers[TILFMT_PAGE] = omap_dmm->tcm[1];
 784                 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET;
 785                 omap_dmm->tcm[1]->lut_id = 0;
 786         } else {
 787                 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
 788         }
 789
 790         area = (struct tcm_area) {
 791                 .tcm = NULL,
 792                 .p1.x = omap_dmm->container_width - 1,
 793                 .p1.y = omap_dmm->container_height - 1,
 794         };
 795
 796         /* initialize all LUTs to dummy page entries */
 797         for (i = 0; i < omap_dmm->num_lut; i++) {
 798                 area.tcm = omap_dmm->tcm[i];
 799                 if (fill(&area, NULL, 0, 0, true))
 800                         dev_err(omap_dmm->dev, "refill failed");
 801         }
 802
 803         dev_info(omap_dmm->dev, "initialized all PAT entries\n");
 804
 805         return 0;
 806
 807 fail:
 808         if (omap_dmm_remove(dev))
 809                 dev_err(&dev->dev, "cleanup failed\n");
 810         return ret;
 811 }
 812
 813 /*
 814  * debugfs support
 815  */
 816
 817 #ifdef CONFIG_DEBUG_FS
 818
 819 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
 820                                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
 821 static const char *special = ".,:;'\"`~!^-+";
 822
 823 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
 824                                                         char c, bool ovw)
 825 {
 826         int x, y;
 827         for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
 828                 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
 829                         if (map[y][x] == ' ' || ovw)
 830                                 map[y][x] = c;
 831 }
 832
 833 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
 834                                                                         char c)
 835 {
 836         map[p->y / ydiv][p->x / xdiv] = c;
 837 }
 838
 839 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
 840 {
 841         return map[p->y / ydiv][p->x / xdiv];
 842 }
 843
 844 static int map_width(int xdiv, int x0, int x1)
 845 {
 846         return (x1 / xdiv) - (x0 / xdiv) + 1;
 847 }
 848
 849 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
 850 {
 851         char *p = map[yd] + (x0 / xdiv);
 852         int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
 853         if (w >= 0) {
 854                 p += w;
 855                 while (*nice)
 856                         *p++ = *nice++;
 857         }
 858 }
 859
 860 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
 861                                                         struct tcm_area *a)
 862 {
 863         sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
 864         if (a->p0.y + 1 < a->p1.y) {
 865                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
 866                                                         256 - 1);
 867         } else if (a->p0.y < a->p1.y) {
 868                 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
 869                         text_map(map, xdiv, nice, a->p0.y / ydiv,
 870                                         a->p0.x + xdiv, 256 - 1);
 871                 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
 872                         text_map(map, xdiv, nice, a->p1.y / ydiv,
 873                                         0, a->p1.y - xdiv);
 874         } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
 875                 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
 876         }
 877 }
 878
 879 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
 880                                                         struct tcm_area *a)
 881 {
 882         sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
 883         if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
 884                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
 885                                                         a->p0.x, a->p1.x);
 886 }
 887
 888 int tiler_map_show(struct seq_file *s, void *arg)
 889 {
 890         int xdiv = 2, ydiv = 1;
 891         char **map = NULL, *global_map;
 892         struct tiler_block *block;
 893         struct tcm_area a, p;
 894         int i;
 895         const char *m2d = alphabet;
 896         const char *a2d = special;
 897         const char *m2dp = m2d, *a2dp = a2d;
 898         char nice[128];
 899         int h_adj;
 900         int w_adj;
 901         unsigned long flags;
 902         int lut_idx;
 903
 904
 905         if (!omap_dmm) {
 906                 /* early return if dmm/tiler device is not initialized */
 907                 return 0;
 908         }
 909
 910         h_adj = omap_dmm->container_height / ydiv;
 911         w_adj = omap_dmm->container_width / xdiv;
 912
 913         map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL);
 914         global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL);
 915
 916         if (!map || !global_map)
 917                 goto error;
 918
 919         for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) {
 920                 memset(map, 0, h_adj * sizeof(*map));
 921                 memset(global_map, ' ', (w_adj + 1) * h_adj);
 922
 923                 for (i = 0; i < omap_dmm->container_height; i++) {
 924                         map[i] = global_map + i * (w_adj + 1);
 925                         map[i][w_adj] = 0;
 926                 }
 927
 928                 spin_lock_irqsave(&list_lock, flags);
 929
 930                 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
 931                         if (block->area.tcm == omap_dmm->tcm[lut_idx]) {
 932                                 if (block->fmt != TILFMT_PAGE) {
 933                                         fill_map(map, xdiv, ydiv, &block->area,
 934                                                 *m2dp, true);
 935                                         if (!*++a2dp)
 936                                                 a2dp = a2d;
 937                                         if (!*++m2dp)
 938                                                 m2dp = m2d;
 939                                         map_2d_info(map, xdiv, ydiv, nice,
 940                                                         &block->area);
 941                                 } else {
 942                                         bool start = read_map_pt(map, xdiv,
 943                                                 ydiv, &block->area.p0) == ' ';
 944                                         bool end = read_map_pt(map, xdiv, ydiv,
 945                                                         &block->area.p1) == ' ';
 946
 947                                         tcm_for_each_slice(a, block->area, p)
 948                                                 fill_map(map, xdiv, ydiv, &a,
 949                                                         '=', true);
 950                                         fill_map_pt(map, xdiv, ydiv,
 951                                                         &block->area.p0,
 952                                                         start ? '<' : 'X');
 953                                         fill_map_pt(map, xdiv, ydiv,
 954                                                         &block->area.p1,
 955                                                         end ? '>' : 'X');
 956                                         map_1d_info(map, xdiv, ydiv, nice,
 957                                                         &block->area);
 958                                 }
 959                         }
 960                 }
 961
 962                 spin_unlock_irqrestore(&list_lock, flags);
 963
 964                 if (s) {
 965                         seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx);
 966                         for (i = 0; i < 128; i++)
 967                                 seq_printf(s, "%03d:%s\n", i, map[i]);
 968                         seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx);
 969                 } else {
 970                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n",
 971                                 lut_idx);
 972                         for (i = 0; i < 128; i++)
 973                                 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
 974                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n",
 975                                 lut_idx);
 976                 }
 977         }
 978
 979 error:
 980         kfree(map);
 981         kfree(global_map);
 982
 983         return 0;
 984 }
 985 #endif
 986
 987 #ifdef CONFIG_PM_SLEEP
 988 static int omap_dmm_resume(struct device *dev)
 989 {
 990         struct tcm_area area;
 991         int i;
 992
 993         if (!omap_dmm)
 994                 return -ENODEV;
 995
 996         area = (struct tcm_area) {
 997                 .tcm = NULL,
 998                 .p1.x = omap_dmm->container_width - 1,
 999                 .p1.y = omap_dmm->container_height - 1,
1000         };
1001
1002         /* initialize all LUTs to dummy page entries */
1003         for (i = 0; i < omap_dmm->num_lut; i++) {
1004                 area.tcm = omap_dmm->tcm[i];
1005                 if (fill(&area, NULL, 0, 0, true))
1006                         dev_err(dev, "refill failed");
1007         }
1008
1009         return 0;
1010 }
1011 #endif
1012
1013 static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
1014
1015 #if defined(CONFIG_OF)
1016 static const struct dmm_platform_data dmm_omap4_platform_data = {
1017         .cpu_cache_flags = OMAP_BO_WC,
1018 };
1019
1020 static const struct dmm_platform_data dmm_omap5_platform_data = {
1021         .cpu_cache_flags = OMAP_BO_UNCACHED,
1022 };
1023
1024 static const struct of_device_id dmm_of_match[] = {
1025         {
1026                 .compatible = "ti,omap4-dmm",
1027                 .data = &dmm_omap4_platform_data,
1028         },
1029         {
1030                 .compatible = "ti,omap5-dmm",
1031                 .data = &dmm_omap5_platform_data,
1032         },
1033         {},
1034 };
1035 #endif
1036
1037 struct platform_driver omap_dmm_driver = {
1038         .probe = omap_dmm_probe,
1039         .remove = omap_dmm_remove,
1040         .driver = {
1041                 .owner = THIS_MODULE,
1042                 .name = DMM_DRIVER_NAME,
1043                 .of_match_table = of_match_ptr(dmm_of_match),
1044                 .pm = &omap_dmm_pm_ops,
1045         },
1046 };
1047
1048 MODULE_LICENSE("GPL v2");
1049 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
1050 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");
1051 MODULE_ALIAS("platform:" DMM_DRIVER_NAME);