drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/slab.h>
  34 #include <linux/acpi.h>
  35 /*
  36  * BIOS.
  37  */
  38
  39 /* If you boot an IGP board with a discrete card as the primary,
  40  * the IGP rom is not accessible via the rom bar as the IGP rom is
  41  * part of the system bios.  On boot, the system bios puts a
  42  * copy of the igp rom at the start of vram if a discrete card is
  43  * present.
  44  */
  45 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  46 {
  47         uint8_t __iomem *bios;
  48         resource_size_t vram_base;
  49         resource_size_t size = 256 * 1024; /* ??? */
  50
  51         if (!(rdev->flags & RADEON_IS_IGP))
  52                 if (!radeon_card_posted(rdev))
  53                         return false;
  54
  55         rdev->bios = NULL;
  56         vram_base = pci_resource_start(rdev->pdev, 0);
  57         bios = ioremap(vram_base, size);
  58         if (!bios) {
  59                 return false;
  60         }
  61
  62         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  63                 iounmap(bios);
  64                 return false;
  65         }
  66         rdev->bios = kmalloc(size, GFP_KERNEL);
  67         if (rdev->bios == NULL) {
  68                 iounmap(bios);
  69                 return false;
  70         }
  71         memcpy_fromio(rdev->bios, bios, size);
  72         iounmap(bios);
  73         return true;
  74 }
  75
  76 static bool radeon_read_bios(struct radeon_device *rdev)
  77 {
  78         uint8_t __iomem *bios, val1, val2;
  79         size_t size;
  80
  81         rdev->bios = NULL;
  82         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  83         bios = pci_map_rom(rdev->pdev, &size);
  84         if (!bios) {
  85                 return false;
  86         }
  87
  88         val1 = readb(&bios[0]);
  89         val2 = readb(&bios[1]);
  90
  91         if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
  92                 pci_unmap_rom(rdev->pdev, bios);
  93                 return false;
  94         }
  95         rdev->bios = kzalloc(size, GFP_KERNEL);
  96         if (rdev->bios == NULL) {
  97                 pci_unmap_rom(rdev->pdev, bios);
  98                 return false;
  99         }
 100         memcpy_fromio(rdev->bios, bios, size);
 101         pci_unmap_rom(rdev->pdev, bios);
 102         return true;
 103 }
 104
 105 static bool radeon_read_platform_bios(struct radeon_device *rdev)
 106 {
 107         phys_addr_t rom = rdev->pdev->rom;
 108         size_t romlen = rdev->pdev->romlen;
 109         void __iomem *bios;
 110
 111         rdev->bios = NULL;
 112
 113         if (!rom || romlen == 0)
 114                 return false;
 115
 116         rdev->bios = kzalloc(romlen, GFP_KERNEL);
 117         if (!rdev->bios)
 118                 return false;
 119
 120         bios = ioremap(rom, romlen);
 121         if (!bios)
 122                 goto free_bios;
 123
 124         memcpy_fromio(rdev->bios, bios, romlen);
 125         iounmap(bios);
 126
 127         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
 128                 goto free_bios;
 129
 130         return true;
 131 free_bios:
 132         kfree(rdev->bios);
 133         return false;
 134 }
 135
 136 #ifdef CONFIG_ACPI
 137 /* ATRM is used to get the BIOS on the discrete cards in
 138  * dual-gpu systems.
 139  */
 140 /* retrieve the ROM in 4k blocks */
 141 #define ATRM_BIOS_PAGE 4096
 142 /**
 143  * radeon_atrm_call - fetch a chunk of the vbios
 144  *
 145  * @atrm_handle: acpi ATRM handle
 146  * @bios: vbios image pointer
 147  * @offset: offset of vbios image data to fetch
 148  * @len: length of vbios image data to fetch
 149  *
 150  * Executes ATRM to fetch a chunk of the discrete
 151  * vbios image on PX systems (all asics).
 152  * Returns the length of the buffer fetched.
 153  */
 154 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
 155                             int offset, int len)
 156 {
 157         acpi_status status;
 158         union acpi_object atrm_arg_elements[2], *obj;
 159         struct acpi_object_list atrm_arg;
 160         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 161
 162         atrm_arg.count = 2;
 163         atrm_arg.pointer = &atrm_arg_elements[0];
 164
 165         atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
 166         atrm_arg_elements[0].integer.value = offset;
 167
 168         atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
 169         atrm_arg_elements[1].integer.value = len;
 170
 171         status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
 172         if (ACPI_FAILURE(status)) {
 173                 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
 174                 return -ENODEV;
 175         }
 176
 177         obj = (union acpi_object *)buffer.pointer;
 178         memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
 179         len = obj->buffer.length;
 180         kfree(buffer.pointer);
 181         return len;
 182 }
 183
 184 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 185 {
 186         int ret;
 187         int size = 256 * 1024;
 188         int i;
 189         struct pci_dev *pdev = NULL;
 190         acpi_handle dhandle, atrm_handle;
 191         acpi_status status;
 192         bool found = false;
 193
 194         /* ATRM is for the discrete card only */
 195         if (rdev->flags & RADEON_IS_IGP)
 196                 return false;
 197
 198         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
 199                 dhandle = ACPI_HANDLE(&pdev->dev);
 200                 if (!dhandle)
 201                         continue;
 202
 203                 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 204                 if (!ACPI_FAILURE(status)) {
 205                         found = true;
 206                         break;
 207                 }
 208         }
 209
 210         if (!found) {
 211                 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
 212                         dhandle = ACPI_HANDLE(&pdev->dev);
 213                         if (!dhandle)
 214                                 continue;
 215
 216                         status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 217                         if (!ACPI_FAILURE(status)) {
 218                                 found = true;
 219                                 break;
 220                         }
 221                 }
 222         }
 223
 224         if (!found)
 225                 return false;
 226         pci_dev_put(pdev);
 227
 228         rdev->bios = kmalloc(size, GFP_KERNEL);
 229         if (!rdev->bios) {
 230                 DRM_ERROR("Unable to allocate bios\n");
 231                 return false;
 232         }
 233
 234         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 235                 ret = radeon_atrm_call(atrm_handle,
 236                                        rdev->bios,
 237                                        (i * ATRM_BIOS_PAGE),
 238                                        ATRM_BIOS_PAGE);
 239                 if (ret < ATRM_BIOS_PAGE)
 240                         break;
 241         }
 242
 243         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 244                 kfree(rdev->bios);
 245                 return false;
 246         }
 247         return true;
 248 }
 249 #else
 250 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
 251 {
 252         return false;
 253 }
 254 #endif
 255
 256 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 257 {
 258         u32 bus_cntl;
 259         u32 d1vga_control;
 260         u32 d2vga_control;
 261         u32 vga_render_control;
 262         u32 rom_cntl;
 263         bool r;
 264
 265         bus_cntl = RREG32(R600_BUS_CNTL);
 266         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 267         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 268         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 269         rom_cntl = RREG32(R600_ROM_CNTL);
 270
 271         /* enable the rom */
 272         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 273         if (!ASIC_IS_NODCE(rdev)) {
 274                 /* Disable VGA mode */
 275                 WREG32(AVIVO_D1VGA_CONTROL,
 276                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 277                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 278                 WREG32(AVIVO_D2VGA_CONTROL,
 279                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 280                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 281                 WREG32(AVIVO_VGA_RENDER_CONTROL,
 282                        (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 283         }
 284         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 285
 286         r = radeon_read_bios(rdev);
 287
 288         /* restore regs */
 289         WREG32(R600_BUS_CNTL, bus_cntl);
 290         if (!ASIC_IS_NODCE(rdev)) {
 291                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 292                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 293                 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 294         }
 295         WREG32(R600_ROM_CNTL, rom_cntl);
 296         return r;
 297 }
 298
 299 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 300 {
 301         uint32_t viph_control;
 302         uint32_t bus_cntl;
 303         uint32_t d1vga_control;
 304         uint32_t d2vga_control;
 305         uint32_t vga_render_control;
 306         uint32_t rom_cntl;
 307         uint32_t cg_spll_func_cntl = 0;
 308         uint32_t cg_spll_status;
 309         bool r;
 310
 311         viph_control = RREG32(RADEON_VIPH_CONTROL);
 312         bus_cntl = RREG32(R600_BUS_CNTL);
 313         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 314         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 315         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 316         rom_cntl = RREG32(R600_ROM_CNTL);
 317
 318         /* disable VIP */
 319         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 320         /* enable the rom */
 321         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 322         /* Disable VGA mode */
 323         WREG32(AVIVO_D1VGA_CONTROL,
 324                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 325                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 326         WREG32(AVIVO_D2VGA_CONTROL,
 327                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 328                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 329         WREG32(AVIVO_VGA_RENDER_CONTROL,
 330                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 331
 332         if (rdev->family == CHIP_RV730) {
 333                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 334
 335                 /* enable bypass mode */
 336                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 337                                                 R600_SPLL_BYPASS_EN));
 338
 339                 /* wait for SPLL_CHG_STATUS to change to 1 */
 340                 cg_spll_status = 0;
 341                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 342                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 343
 344                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 345         } else
 346                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 347
 348         r = radeon_read_bios(rdev);
 349
 350         /* restore regs */
 351         if (rdev->family == CHIP_RV730) {
 352                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 353
 354                 /* wait for SPLL_CHG_STATUS to change to 1 */
 355                 cg_spll_status = 0;
 356                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 357                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 358         }
 359         WREG32(RADEON_VIPH_CONTROL, viph_control);
 360         WREG32(R600_BUS_CNTL, bus_cntl);
 361         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 362         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 363         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 364         WREG32(R600_ROM_CNTL, rom_cntl);
 365         return r;
 366 }
 367
 368 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 369 {
 370         uint32_t viph_control;
 371         uint32_t bus_cntl;
 372         uint32_t d1vga_control;
 373         uint32_t d2vga_control;
 374         uint32_t vga_render_control;
 375         uint32_t rom_cntl;
 376         uint32_t general_pwrmgt;
 377         uint32_t low_vid_lower_gpio_cntl;
 378         uint32_t medium_vid_lower_gpio_cntl;
 379         uint32_t high_vid_lower_gpio_cntl;
 380         uint32_t ctxsw_vid_lower_gpio_cntl;
 381         uint32_t lower_gpio_enable;
 382         bool r;
 383
 384         viph_control = RREG32(RADEON_VIPH_CONTROL);
 385         bus_cntl = RREG32(R600_BUS_CNTL);
 386         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 387         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 388         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 389         rom_cntl = RREG32(R600_ROM_CNTL);
 390         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 391         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 392         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 393         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 394         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 395         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 396
 397         /* disable VIP */
 398         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 399         /* enable the rom */
 400         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 401         /* Disable VGA mode */
 402         WREG32(AVIVO_D1VGA_CONTROL,
 403                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 404                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 405         WREG32(AVIVO_D2VGA_CONTROL,
 406                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 407                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 408         WREG32(AVIVO_VGA_RENDER_CONTROL,
 409                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 410
 411         WREG32(R600_ROM_CNTL,
 412                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 413                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 414                 R600_SCK_OVERWRITE));
 415
 416         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 417         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 418                (low_vid_lower_gpio_cntl & ~0x400));
 419         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 420                (medium_vid_lower_gpio_cntl & ~0x400));
 421         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 422                (high_vid_lower_gpio_cntl & ~0x400));
 423         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 424                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 425         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 426
 427         r = radeon_read_bios(rdev);
 428
 429         /* restore regs */
 430         WREG32(RADEON_VIPH_CONTROL, viph_control);
 431         WREG32(R600_BUS_CNTL, bus_cntl);
 432         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 433         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 434         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 435         WREG32(R600_ROM_CNTL, rom_cntl);
 436         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 437         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 438         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 439         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 440         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 441         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 442         return r;
 443 }
 444
 445 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 446 {
 447         uint32_t seprom_cntl1;
 448         uint32_t viph_control;
 449         uint32_t bus_cntl;
 450         uint32_t d1vga_control;
 451         uint32_t d2vga_control;
 452         uint32_t vga_render_control;
 453         uint32_t gpiopad_a;
 454         uint32_t gpiopad_en;
 455         uint32_t gpiopad_mask;
 456         bool r;
 457
 458         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 459         viph_control = RREG32(RADEON_VIPH_CONTROL);
 460         bus_cntl = RREG32(RV370_BUS_CNTL);
 461         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 462         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 463         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 464         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 465         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 466         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 467
 468         WREG32(RADEON_SEPROM_CNTL1,
 469                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 470                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 471         WREG32(RADEON_GPIOPAD_A, 0);
 472         WREG32(RADEON_GPIOPAD_EN, 0);
 473         WREG32(RADEON_GPIOPAD_MASK, 0);
 474
 475         /* disable VIP */
 476         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 477
 478         /* enable the rom */
 479         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 480
 481         /* Disable VGA mode */
 482         WREG32(AVIVO_D1VGA_CONTROL,
 483                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 484                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 485         WREG32(AVIVO_D2VGA_CONTROL,
 486                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 487                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 488         WREG32(AVIVO_VGA_RENDER_CONTROL,
 489                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 490
 491         r = radeon_read_bios(rdev);
 492
 493         /* restore regs */
 494         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 495         WREG32(RADEON_VIPH_CONTROL, viph_control);
 496         WREG32(RV370_BUS_CNTL, bus_cntl);
 497         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 498         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 499         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 500         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 501         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 502         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 503         return r;
 504 }
 505
 506 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 507 {
 508         uint32_t seprom_cntl1;
 509         uint32_t viph_control;
 510         uint32_t bus_cntl;
 511         uint32_t crtc_gen_cntl;
 512         uint32_t crtc2_gen_cntl;
 513         uint32_t crtc_ext_cntl;
 514         uint32_t fp2_gen_cntl;
 515         bool r;
 516
 517         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 518         viph_control = RREG32(RADEON_VIPH_CONTROL);
 519         if (rdev->flags & RADEON_IS_PCIE)
 520                 bus_cntl = RREG32(RV370_BUS_CNTL);
 521         else
 522                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 523         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 524         crtc2_gen_cntl = 0;
 525         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 526         fp2_gen_cntl = 0;
 527
 528         if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 529                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 530         }
 531
 532         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 533                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 534         }
 535
 536         WREG32(RADEON_SEPROM_CNTL1,
 537                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 538                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 539
 540         /* disable VIP */
 541         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 542
 543         /* enable the rom */
 544         if (rdev->flags & RADEON_IS_PCIE)
 545                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 546         else
 547                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 548
 549         /* Turn off mem requests and CRTC for both controllers */
 550         WREG32(RADEON_CRTC_GEN_CNTL,
 551                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 552                 (RADEON_CRTC_DISP_REQ_EN_B |
 553                  RADEON_CRTC_EXT_DISP_EN)));
 554         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 555                 WREG32(RADEON_CRTC2_GEN_CNTL,
 556                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 557                         RADEON_CRTC2_DISP_REQ_EN_B));
 558         }
 559         /* Turn off CRTC */
 560         WREG32(RADEON_CRTC_EXT_CNTL,
 561                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 562                 (RADEON_CRTC_SYNC_TRISTAT |
 563                  RADEON_CRTC_DISPLAY_DIS)));
 564
 565         if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 566                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 567         }
 568
 569         r = radeon_read_bios(rdev);
 570
 571         /* restore regs */
 572         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 573         WREG32(RADEON_VIPH_CONTROL, viph_control);
 574         if (rdev->flags & RADEON_IS_PCIE)
 575                 WREG32(RV370_BUS_CNTL, bus_cntl);
 576         else
 577                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 578         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 579         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 580                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 581         }
 582         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 583         if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 584                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 585         }
 586         return r;
 587 }
 588
 589 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 590 {
 591         if (rdev->flags & RADEON_IS_IGP)
 592                 return igp_read_bios_from_vram(rdev);
 593         else if (rdev->family >= CHIP_BARTS)
 594                 return ni_read_disabled_bios(rdev);
 595         else if (rdev->family >= CHIP_RV770)
 596                 return r700_read_disabled_bios(rdev);
 597         else if (rdev->family >= CHIP_R600)
 598                 return r600_read_disabled_bios(rdev);
 599         else if (rdev->family >= CHIP_RS600)
 600                 return avivo_read_disabled_bios(rdev);
 601         else
 602                 return legacy_read_disabled_bios(rdev);
 603 }
 604
 605 #ifdef CONFIG_ACPI
 606 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 607 {
 608         struct acpi_table_header *hdr;
 609         acpi_size tbl_size;
 610         UEFI_ACPI_VFCT *vfct;
 611         unsigned offset;
 612         bool r = false;
 613
 614         if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
 615                 return false;
 616         tbl_size = hdr->length;
 617         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 618                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 619                 goto out;
 620         }
 621
 622         vfct = (UEFI_ACPI_VFCT *)hdr;
 623         offset = vfct->VBIOSImageOffset;
 624
 625         while (offset < tbl_size) {
 626                 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
 627                 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
 628
 629                 offset += sizeof(VFCT_IMAGE_HEADER);
 630                 if (offset > tbl_size) {
 631                         DRM_ERROR("ACPI VFCT image header truncated\n");
 632                         goto out;
 633                 }
 634
 635                 offset += vhdr->ImageLength;
 636                 if (offset > tbl_size) {
 637                         DRM_ERROR("ACPI VFCT image truncated\n");
 638                         goto out;
 639                 }
 640
 641                 if (vhdr->ImageLength &&
 642                     vhdr->PCIBus == rdev->pdev->bus->number &&
 643                     vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
 644                     vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
 645                     vhdr->VendorID == rdev->pdev->vendor &&
 646                     vhdr->DeviceID == rdev->pdev->device) {
 647                         rdev->bios = kmemdup(&vbios->VbiosContent,
 648                                              vhdr->ImageLength,
 649                                              GFP_KERNEL);
 650                         if (rdev->bios)
 651                                 r = true;
 652
 653                         goto out;
 654                 }
 655         }
 656
 657         DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 658
 659 out:
 660         acpi_put_table(hdr);
 661         return r;
 662 }
 663 #else
 664 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 665 {
 666         return false;
 667 }
 668 #endif
 669
 670 bool radeon_get_bios(struct radeon_device *rdev)
 671 {
 672         bool r;
 673         uint16_t tmp;
 674
 675         r = radeon_atrm_get_bios(rdev);
 676         if (r == false)
 677                 r = radeon_acpi_vfct_bios(rdev);
 678         if (r == false)
 679                 r = igp_read_bios_from_vram(rdev);
 680         if (r == false)
 681                 r = radeon_read_bios(rdev);
 682         if (r == false)
 683                 r = radeon_read_disabled_bios(rdev);
 684         if (r == false)
 685                 r = radeon_read_platform_bios(rdev);
 686         if (r == false || rdev->bios == NULL) {
 687                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 688                 rdev->bios = NULL;
 689                 return false;
 690         }
 691         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 692                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 693                 goto free_bios;
 694         }
 695
 696         tmp = RBIOS16(0x18);
 697         if (RBIOS8(tmp + 0x14) != 0x0) {
 698                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 699                 goto free_bios;
 700         }
 701
 702         rdev->bios_header_start = RBIOS16(0x48);
 703         if (!rdev->bios_header_start) {
 704                 goto free_bios;
 705         }
 706         tmp = rdev->bios_header_start + 4;
 707         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 708             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 709                 rdev->is_atom_bios = true;
 710         } else {
 711                 rdev->is_atom_bios = false;
 712         }
 713
 714         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 715         return true;
 716 free_bios:
 717         kfree(rdev->bios);
 718         rdev->bios = NULL;
 719         return false;
 720 }