drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #include "radeon_kfd.h"
  38
  39 #if defined(CONFIG_VGA_SWITCHEROO)
  40 bool radeon_has_atpx(void);
  41 #else
  42 static inline bool radeon_has_atpx(void) { return false; }
  43 #endif
  44
  45 /**
  46  * radeon_driver_unload_kms - Main unload function for KMS.
  47  *
  48  * @dev: drm dev pointer
  49  *
  50  * This is the main unload function for KMS (all asics).
  51  * It calls radeon_modeset_fini() to tear down the
  52  * displays, and radeon_device_fini() to tear down
  53  * the rest of the device (CP, writeback, etc.).
  54  * Returns 0 on success.
  55  */
  56 void radeon_driver_unload_kms(struct drm_device *dev)
  57 {
  58         struct radeon_device *rdev = dev->dev_private;
  59
  60         if (rdev == NULL)
  61                 return;
  62
  63         if (rdev->rmmio == NULL)
  64                 goto done_free;
  65
  66         if (radeon_is_px(dev)) {
  67                 pm_runtime_get_sync(dev->dev);
  68                 pm_runtime_forbid(dev->dev);
  69         }
  70
  71         radeon_kfd_device_fini(rdev);
  72
  73         radeon_acpi_fini(rdev);
  74
  75         radeon_modeset_fini(rdev);
  76         radeon_device_fini(rdev);
  77
  78 done_free:
  79         kfree(rdev);
  80         dev->dev_private = NULL;
  81 }
  82
  83 /**
  84  * radeon_driver_load_kms - Main load function for KMS.
  85  *
  86  * @dev: drm dev pointer
  87  * @flags: device flags
  88  *
  89  * This is the main load function for KMS (all asics).
  90  * It calls radeon_device_init() to set up the non-display
  91  * parts of the chip (asic init, CP, writeback, etc.), and
  92  * radeon_modeset_init() to set up the display parts
  93  * (crtcs, encoders, hotplug detect, etc.).
  94  * Returns 0 on success, error on failure.
  95  */
  96 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  97 {
  98         struct radeon_device *rdev;
  99         int r, acpi_status;
 100
 101         if (!radeon_si_support) {
 102                 switch (flags & RADEON_FAMILY_MASK) {
 103                 case CHIP_TAHITI:
 104                 case CHIP_PITCAIRN:
 105                 case CHIP_VERDE:
 106                 case CHIP_OLAND:
 107                 case CHIP_HAINAN:
 108                         dev_info(dev->dev,
 109                                  "SI support disabled by module param\n");
 110                         return -ENODEV;
 111                 }
 112         }
 113         if (!radeon_cik_support) {
 114                 switch (flags & RADEON_FAMILY_MASK) {
 115                 case CHIP_KAVERI:
 116                 case CHIP_BONAIRE:
 117                 case CHIP_HAWAII:
 118                 case CHIP_KABINI:
 119                 case CHIP_MULLINS:
 120                         dev_info(dev->dev,
 121                                  "CIK support disabled by module param\n");
 122                         return -ENODEV;
 123                 }
 124         }
 125
 126         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
 127         if (rdev == NULL) {
 128                 return -ENOMEM;
 129         }
 130         dev->dev_private = (void *)rdev;
 131
 132         /* update BUS flag */
 133         if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
 134                 flags |= RADEON_IS_AGP;
 135         } else if (pci_is_pcie(dev->pdev)) {
 136                 flags |= RADEON_IS_PCIE;
 137         } else {
 138                 flags |= RADEON_IS_PCI;
 139         }
 140
 141         if ((radeon_runtime_pm != 0) &&
 142             radeon_has_atpx() &&
 143             ((flags & RADEON_IS_IGP) == 0) &&
 144             !pci_is_thunderbolt_attached(dev->pdev))
 145                 flags |= RADEON_IS_PX;
 146
 147         /* radeon_device_init should report only fatal error
 148          * like memory allocation failure or iomapping failure,
 149          * or memory manager initialization failure, it must
 150          * properly initialize the GPU MC controller and permit
 151          * VRAM allocation
 152          */
 153         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 154         if (r) {
 155                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 156                 goto out;
 157         }
 158
 159         /* Again modeset_init should fail only on fatal error
 160          * otherwise it should provide enough functionalities
 161          * for shadowfb to run
 162          */
 163         r = radeon_modeset_init(rdev);
 164         if (r)
 165                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 166
 167         /* Call ACPI methods: require modeset init
 168          * but failure is not fatal
 169          */
 170         if (!r) {
 171                 acpi_status = radeon_acpi_init(rdev);
 172                 if (acpi_status)
 173                 dev_dbg(&dev->pdev->dev,
 174                                 "Error during ACPI methods call\n");
 175         }
 176
 177         radeon_kfd_device_probe(rdev);
 178         radeon_kfd_device_init(rdev);
 179
 180         if (radeon_is_px(dev)) {
 181                 pm_runtime_use_autosuspend(dev->dev);
 182                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 183                 pm_runtime_set_active(dev->dev);
 184                 pm_runtime_allow(dev->dev);
 185                 pm_runtime_mark_last_busy(dev->dev);
 186                 pm_runtime_put_autosuspend(dev->dev);
 187         }
 188
 189 out:
 190         if (r)
 191                 radeon_driver_unload_kms(dev);
 192
 193
 194         return r;
 195 }
 196
 197 /**
 198  * radeon_set_filp_rights - Set filp right.
 199  *
 200  * @dev: drm dev pointer
 201  * @owner: drm file
 202  * @applier: drm file
 203  * @value: value
 204  *
 205  * Sets the filp rights for the device (all asics).
 206  */
 207 static void radeon_set_filp_rights(struct drm_device *dev,
 208                                    struct drm_file **owner,
 209                                    struct drm_file *applier,
 210                                    uint32_t *value)
 211 {
 212         struct radeon_device *rdev = dev->dev_private;
 213
 214         mutex_lock(&rdev->gem.mutex);
 215         if (*value == 1) {
 216                 /* wants rights */
 217                 if (!*owner)
 218                         *owner = applier;
 219         } else if (*value == 0) {
 220                 /* revokes rights */
 221                 if (*owner == applier)
 222                         *owner = NULL;
 223         }
 224         *value = *owner == applier ? 1 : 0;
 225         mutex_unlock(&rdev->gem.mutex);
 226 }
 227
 228 /*
 229  * Userspace get information ioctl
 230  */
 231 /**
 232  * radeon_info_ioctl - answer a device specific request.
 233  *
 234  * @rdev: radeon device pointer
 235  * @data: request object
 236  * @filp: drm filp
 237  *
 238  * This function is used to pass device specific parameters to the userspace
 239  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 240  * etc. (all asics).
 241  * Returns 0 on success, -EINVAL on failure.
 242  */
 243 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 244 {
 245         struct radeon_device *rdev = dev->dev_private;
 246         struct drm_radeon_info *info = data;
 247         struct radeon_mode_info *minfo = &rdev->mode_info;
 248         uint32_t *value, value_tmp, *value_ptr, value_size;
 249         uint64_t value64;
 250         struct drm_crtc *crtc;
 251         int i, found;
 252
 253         value_ptr = (uint32_t *)((unsigned long)info->value);
 254         value = &value_tmp;
 255         value_size = sizeof(uint32_t);
 256
 257         switch (info->request) {
 258         case RADEON_INFO_DEVICE_ID:
 259                 *value = dev->pdev->device;
 260                 break;
 261         case RADEON_INFO_NUM_GB_PIPES:
 262                 *value = rdev->num_gb_pipes;
 263                 break;
 264         case RADEON_INFO_NUM_Z_PIPES:
 265                 *value = rdev->num_z_pipes;
 266                 break;
 267         case RADEON_INFO_ACCEL_WORKING:
 268                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 269                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 270                         *value = false;
 271                 else
 272                         *value = rdev->accel_working;
 273                 break;
 274         case RADEON_INFO_CRTC_FROM_ID:
 275                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 276                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 277                         return -EFAULT;
 278                 }
 279                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 280                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 281                         if (crtc && crtc->base.id == *value) {
 282                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 283                                 *value = radeon_crtc->crtc_id;
 284                                 found = 1;
 285                                 break;
 286                         }
 287                 }
 288                 if (!found) {
 289                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 290                         return -EINVAL;
 291                 }
 292                 break;
 293         case RADEON_INFO_ACCEL_WORKING2:
 294                 if (rdev->family == CHIP_HAWAII) {
 295                         if (rdev->accel_working) {
 296                                 if (rdev->new_fw)
 297                                         *value = 3;
 298                                 else
 299                                         *value = 2;
 300                         } else {
 301                                 *value = 0;
 302                         }
 303                 } else {
 304                         *value = rdev->accel_working;
 305                 }
 306                 break;
 307         case RADEON_INFO_TILING_CONFIG:
 308                 if (rdev->family >= CHIP_BONAIRE)
 309                         *value = rdev->config.cik.tile_config;
 310                 else if (rdev->family >= CHIP_TAHITI)
 311                         *value = rdev->config.si.tile_config;
 312                 else if (rdev->family >= CHIP_CAYMAN)
 313                         *value = rdev->config.cayman.tile_config;
 314                 else if (rdev->family >= CHIP_CEDAR)
 315                         *value = rdev->config.evergreen.tile_config;
 316                 else if (rdev->family >= CHIP_RV770)
 317                         *value = rdev->config.rv770.tile_config;
 318                 else if (rdev->family >= CHIP_R600)
 319                         *value = rdev->config.r600.tile_config;
 320                 else {
 321                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 322                         return -EINVAL;
 323                 }
 324                 break;
 325         case RADEON_INFO_WANT_HYPERZ:
 326                 /* The "value" here is both an input and output parameter.
 327                  * If the input value is 1, filp requests hyper-z access.
 328                  * If the input value is 0, filp revokes its hyper-z access.
 329                  *
 330                  * When returning, the value is 1 if filp owns hyper-z access,
 331                  * 0 otherwise. */
 332                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 333                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 334                         return -EFAULT;
 335                 }
 336                 if (*value >= 2) {
 337                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 338                         return -EINVAL;
 339                 }
 340                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 341                 break;
 342         case RADEON_INFO_WANT_CMASK:
 343                 /* The same logic as Hyper-Z. */
 344                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 345                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 346                         return -EFAULT;
 347                 }
 348                 if (*value >= 2) {
 349                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 350                         return -EINVAL;
 351                 }
 352                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 353                 break;
 354         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 355                 /* return clock value in KHz */
 356                 if (rdev->asic->get_xclk)
 357                         *value = radeon_get_xclk(rdev) * 10;
 358                 else
 359                         *value = rdev->clock.spll.reference_freq * 10;
 360                 break;
 361         case RADEON_INFO_NUM_BACKENDS:
 362                 if (rdev->family >= CHIP_BONAIRE)
 363                         *value = rdev->config.cik.max_backends_per_se *
 364                                 rdev->config.cik.max_shader_engines;
 365                 else if (rdev->family >= CHIP_TAHITI)
 366                         *value = rdev->config.si.max_backends_per_se *
 367                                 rdev->config.si.max_shader_engines;
 368                 else if (rdev->family >= CHIP_CAYMAN)
 369                         *value = rdev->config.cayman.max_backends_per_se *
 370                                 rdev->config.cayman.max_shader_engines;
 371                 else if (rdev->family >= CHIP_CEDAR)
 372                         *value = rdev->config.evergreen.max_backends;
 373                 else if (rdev->family >= CHIP_RV770)
 374                         *value = rdev->config.rv770.max_backends;
 375                 else if (rdev->family >= CHIP_R600)
 376                         *value = rdev->config.r600.max_backends;
 377                 else {
 378                         return -EINVAL;
 379                 }
 380                 break;
 381         case RADEON_INFO_NUM_TILE_PIPES:
 382                 if (rdev->family >= CHIP_BONAIRE)
 383                         *value = rdev->config.cik.max_tile_pipes;
 384                 else if (rdev->family >= CHIP_TAHITI)
 385                         *value = rdev->config.si.max_tile_pipes;
 386                 else if (rdev->family >= CHIP_CAYMAN)
 387                         *value = rdev->config.cayman.max_tile_pipes;
 388                 else if (rdev->family >= CHIP_CEDAR)
 389                         *value = rdev->config.evergreen.max_tile_pipes;
 390                 else if (rdev->family >= CHIP_RV770)
 391                         *value = rdev->config.rv770.max_tile_pipes;
 392                 else if (rdev->family >= CHIP_R600)
 393                         *value = rdev->config.r600.max_tile_pipes;
 394                 else {
 395                         return -EINVAL;
 396                 }
 397                 break;
 398         case RADEON_INFO_FUSION_GART_WORKING:
 399                 *value = 1;
 400                 break;
 401         case RADEON_INFO_BACKEND_MAP:
 402                 if (rdev->family >= CHIP_BONAIRE)
 403                         *value = rdev->config.cik.backend_map;
 404                 else if (rdev->family >= CHIP_TAHITI)
 405                         *value = rdev->config.si.backend_map;
 406                 else if (rdev->family >= CHIP_CAYMAN)
 407                         *value = rdev->config.cayman.backend_map;
 408                 else if (rdev->family >= CHIP_CEDAR)
 409                         *value = rdev->config.evergreen.backend_map;
 410                 else if (rdev->family >= CHIP_RV770)
 411                         *value = rdev->config.rv770.backend_map;
 412                 else if (rdev->family >= CHIP_R600)
 413                         *value = rdev->config.r600.backend_map;
 414                 else {
 415                         return -EINVAL;
 416                 }
 417                 break;
 418         case RADEON_INFO_VA_START:
 419                 /* this is where we report if vm is supported or not */
 420                 if (rdev->family < CHIP_CAYMAN)
 421                         return -EINVAL;
 422                 *value = RADEON_VA_RESERVED_SIZE;
 423                 break;
 424         case RADEON_INFO_IB_VM_MAX_SIZE:
 425                 /* this is where we report if vm is supported or not */
 426                 if (rdev->family < CHIP_CAYMAN)
 427                         return -EINVAL;
 428                 *value = RADEON_IB_VM_MAX_SIZE;
 429                 break;
 430         case RADEON_INFO_MAX_PIPES:
 431                 if (rdev->family >= CHIP_BONAIRE)
 432                         *value = rdev->config.cik.max_cu_per_sh;
 433                 else if (rdev->family >= CHIP_TAHITI)
 434                         *value = rdev->config.si.max_cu_per_sh;
 435                 else if (rdev->family >= CHIP_CAYMAN)
 436                         *value = rdev->config.cayman.max_pipes_per_simd;
 437                 else if (rdev->family >= CHIP_CEDAR)
 438                         *value = rdev->config.evergreen.max_pipes;
 439                 else if (rdev->family >= CHIP_RV770)
 440                         *value = rdev->config.rv770.max_pipes;
 441                 else if (rdev->family >= CHIP_R600)
 442                         *value = rdev->config.r600.max_pipes;
 443                 else {
 444                         return -EINVAL;
 445                 }
 446                 break;
 447         case RADEON_INFO_TIMESTAMP:
 448                 if (rdev->family < CHIP_R600) {
 449                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 450                         return -EINVAL;
 451                 }
 452                 value = (uint32_t*)&value64;
 453                 value_size = sizeof(uint64_t);
 454                 value64 = radeon_get_gpu_clock_counter(rdev);
 455                 break;
 456         case RADEON_INFO_MAX_SE:
 457                 if (rdev->family >= CHIP_BONAIRE)
 458                         *value = rdev->config.cik.max_shader_engines;
 459                 else if (rdev->family >= CHIP_TAHITI)
 460                         *value = rdev->config.si.max_shader_engines;
 461                 else if (rdev->family >= CHIP_CAYMAN)
 462                         *value = rdev->config.cayman.max_shader_engines;
 463                 else if (rdev->family >= CHIP_CEDAR)
 464                         *value = rdev->config.evergreen.num_ses;
 465                 else
 466                         *value = 1;
 467                 break;
 468         case RADEON_INFO_MAX_SH_PER_SE:
 469                 if (rdev->family >= CHIP_BONAIRE)
 470                         *value = rdev->config.cik.max_sh_per_se;
 471                 else if (rdev->family >= CHIP_TAHITI)
 472                         *value = rdev->config.si.max_sh_per_se;
 473                 else
 474                         return -EINVAL;
 475                 break;
 476         case RADEON_INFO_FASTFB_WORKING:
 477                 *value = rdev->fastfb_working;
 478                 break;
 479         case RADEON_INFO_RING_WORKING:
 480                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 481                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 482                         return -EFAULT;
 483                 }
 484                 switch (*value) {
 485                 case RADEON_CS_RING_GFX:
 486                 case RADEON_CS_RING_COMPUTE:
 487                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 488                         break;
 489                 case RADEON_CS_RING_DMA:
 490                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 491                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 492                         break;
 493                 case RADEON_CS_RING_UVD:
 494                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 495                         break;
 496                 case RADEON_CS_RING_VCE:
 497                         *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
 498                         break;
 499                 default:
 500                         return -EINVAL;
 501                 }
 502                 break;
 503         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 504                 if (rdev->family >= CHIP_BONAIRE) {
 505                         value = rdev->config.cik.tile_mode_array;
 506                         value_size = sizeof(uint32_t)*32;
 507                 } else if (rdev->family >= CHIP_TAHITI) {
 508                         value = rdev->config.si.tile_mode_array;
 509                         value_size = sizeof(uint32_t)*32;
 510                 } else {
 511                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 512                         return -EINVAL;
 513                 }
 514                 break;
 515         case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
 516                 if (rdev->family >= CHIP_BONAIRE) {
 517                         value = rdev->config.cik.macrotile_mode_array;
 518                         value_size = sizeof(uint32_t)*16;
 519                 } else {
 520                         DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
 521                         return -EINVAL;
 522                 }
 523                 break;
 524         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 525                 *value = 1;
 526                 break;
 527         case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
 528                 if (rdev->family >= CHIP_BONAIRE) {
 529                         *value = rdev->config.cik.backend_enable_mask;
 530                 } else if (rdev->family >= CHIP_TAHITI) {
 531                         *value = rdev->config.si.backend_enable_mask;
 532                 } else {
 533                         DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
 534                         return -EINVAL;
 535                 }
 536                 break;
 537         case RADEON_INFO_MAX_SCLK:
 538                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
 539                     rdev->pm.dpm_enabled)
 540                         *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
 541                 else
 542                         *value = rdev->pm.default_sclk * 10;
 543                 break;
 544         case RADEON_INFO_VCE_FW_VERSION:
 545                 *value = rdev->vce.fw_version;
 546                 break;
 547         case RADEON_INFO_VCE_FB_VERSION:
 548                 *value = rdev->vce.fb_version;
 549                 break;
 550         case RADEON_INFO_NUM_BYTES_MOVED:
 551                 value = (uint32_t*)&value64;
 552                 value_size = sizeof(uint64_t);
 553                 value64 = atomic64_read(&rdev->num_bytes_moved);
 554                 break;
 555         case RADEON_INFO_VRAM_USAGE:
 556                 value = (uint32_t*)&value64;
 557                 value_size = sizeof(uint64_t);
 558                 value64 = atomic64_read(&rdev->vram_usage);
 559                 break;
 560         case RADEON_INFO_GTT_USAGE:
 561                 value = (uint32_t*)&value64;
 562                 value_size = sizeof(uint64_t);
 563                 value64 = atomic64_read(&rdev->gtt_usage);
 564                 break;
 565         case RADEON_INFO_ACTIVE_CU_COUNT:
 566                 if (rdev->family >= CHIP_BONAIRE)
 567                         *value = rdev->config.cik.active_cus;
 568                 else if (rdev->family >= CHIP_TAHITI)
 569                         *value = rdev->config.si.active_cus;
 570                 else if (rdev->family >= CHIP_CAYMAN)
 571                         *value = rdev->config.cayman.active_simds;
 572                 else if (rdev->family >= CHIP_CEDAR)
 573                         *value = rdev->config.evergreen.active_simds;
 574                 else if (rdev->family >= CHIP_RV770)
 575                         *value = rdev->config.rv770.active_simds;
 576                 else if (rdev->family >= CHIP_R600)
 577                         *value = rdev->config.r600.active_simds;
 578                 else
 579                         *value = 1;
 580                 break;
 581         case RADEON_INFO_CURRENT_GPU_TEMP:
 582                 /* get temperature in millidegrees C */
 583                 if (rdev->asic->pm.get_temperature)
 584                         *value = radeon_get_temperature(rdev);
 585                 else
 586                         *value = 0;
 587                 break;
 588         case RADEON_INFO_CURRENT_GPU_SCLK:
 589                 /* get sclk in Mhz */
 590                 if (rdev->pm.dpm_enabled)
 591                         *value = radeon_dpm_get_current_sclk(rdev) / 100;
 592                 else
 593                         *value = rdev->pm.current_sclk / 100;
 594                 break;
 595         case RADEON_INFO_CURRENT_GPU_MCLK:
 596                 /* get mclk in Mhz */
 597                 if (rdev->pm.dpm_enabled)
 598                         *value = radeon_dpm_get_current_mclk(rdev) / 100;
 599                 else
 600                         *value = rdev->pm.current_mclk / 100;
 601                 break;
 602         case RADEON_INFO_READ_REG:
 603                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 604                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 605                         return -EFAULT;
 606                 }
 607                 if (radeon_get_allowed_info_register(rdev, *value, value))
 608                         return -EINVAL;
 609                 break;
 610         case RADEON_INFO_VA_UNMAP_WORKING:
 611                 *value = true;
 612                 break;
 613         case RADEON_INFO_GPU_RESET_COUNTER:
 614                 *value = atomic_read(&rdev->gpu_reset_counter);
 615                 break;
 616         default:
 617                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 618                 return -EINVAL;
 619         }
 620         if (copy_to_user(value_ptr, (char*)value, value_size)) {
 621                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 622                 return -EFAULT;
 623         }
 624         return 0;
 625 }
 626
 627
 628 /*
 629  * Outdated mess for old drm with Xorg being in charge (void function now).
 630  */
 631 /**
 632  * radeon_driver_lastclose_kms - drm callback for last close
 633  *
 634  * @dev: drm dev pointer
 635  *
 636  * Switch vga_switcheroo state after last close (all asics).
 637  */
 638 void radeon_driver_lastclose_kms(struct drm_device *dev)
 639 {
 640         struct radeon_device *rdev = dev->dev_private;
 641
 642         radeon_fbdev_restore_mode(rdev);
 643         vga_switcheroo_process_delayed_switch();
 644 }
 645
 646 /**
 647  * radeon_driver_open_kms - drm callback for open
 648  *
 649  * @dev: drm dev pointer
 650  * @file_priv: drm file
 651  *
 652  * On device open, init vm on cayman+ (all asics).
 653  * Returns 0 on success, error on failure.
 654  */
 655 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 656 {
 657         struct radeon_device *rdev = dev->dev_private;
 658         struct radeon_fpriv *fpriv;
 659         struct radeon_vm *vm;
 660         int r;
 661
 662         file_priv->driver_priv = NULL;
 663
 664         r = pm_runtime_get_sync(dev->dev);
 665         if (r < 0) {
 666                 pm_runtime_put_autosuspend(dev->dev);
 667                 return r;
 668         }
 669
 670         /* new gpu have virtual address space support */
 671         if (rdev->family >= CHIP_CAYMAN) {
 672
 673                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 674                 if (unlikely(!fpriv)) {
 675                         r = -ENOMEM;
 676                         goto err_suspend;
 677                 }
 678
 679                 if (rdev->accel_working) {
 680                         vm = &fpriv->vm;
 681                         r = radeon_vm_init(rdev, vm);
 682                         if (r)
 683                                 goto err_fpriv;
 684
 685                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 686                         if (r)
 687                                 goto err_vm_fini;
 688
 689                         /* map the ib pool buffer read only into
 690                          * virtual address space */
 691                         vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
 692                                                         rdev->ring_tmp_bo.bo);
 693                         if (!vm->ib_bo_va) {
 694                                 r = -ENOMEM;
 695                                 goto err_vm_fini;
 696                         }
 697
 698                         r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
 699                                                   RADEON_VA_IB_OFFSET,
 700                                                   RADEON_VM_PAGE_READABLE |
 701                                                   RADEON_VM_PAGE_SNOOPED);
 702                         if (r)
 703                                 goto err_vm_fini;
 704                 }
 705                 file_priv->driver_priv = fpriv;
 706         }
 707
 708         pm_runtime_mark_last_busy(dev->dev);
 709         pm_runtime_put_autosuspend(dev->dev);
 710         return 0;
 711
 712 err_vm_fini:
 713         radeon_vm_fini(rdev, vm);
 714 err_fpriv:
 715         kfree(fpriv);
 716
 717 err_suspend:
 718         pm_runtime_mark_last_busy(dev->dev);
 719         pm_runtime_put_autosuspend(dev->dev);
 720         return r;
 721 }
 722
 723 /**
 724  * radeon_driver_postclose_kms - drm callback for post close
 725  *
 726  * @dev: drm dev pointer
 727  * @file_priv: drm file
 728  *
 729  * On device close, tear down hyperz and cmask filps on r1xx-r5xx
 730  * (all asics).  And tear down vm on cayman+ (all asics).
 731  */
 732 void radeon_driver_postclose_kms(struct drm_device *dev,
 733                                  struct drm_file *file_priv)
 734 {
 735         struct radeon_device *rdev = dev->dev_private;
 736
 737         pm_runtime_get_sync(dev->dev);
 738
 739         mutex_lock(&rdev->gem.mutex);
 740         if (rdev->hyperz_filp == file_priv)
 741                 rdev->hyperz_filp = NULL;
 742         if (rdev->cmask_filp == file_priv)
 743                 rdev->cmask_filp = NULL;
 744         mutex_unlock(&rdev->gem.mutex);
 745
 746         radeon_uvd_free_handles(rdev, file_priv);
 747         radeon_vce_free_handles(rdev, file_priv);
 748
 749         /* new gpu have virtual address space support */
 750         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 751                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 752                 struct radeon_vm *vm = &fpriv->vm;
 753                 int r;
 754
 755                 if (rdev->accel_working) {
 756                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 757                         if (!r) {
 758                                 if (vm->ib_bo_va)
 759                                         radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
 760                                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 761                         }
 762                         radeon_vm_fini(rdev, vm);
 763                 }
 764
 765                 kfree(fpriv);
 766                 file_priv->driver_priv = NULL;
 767         }
 768         pm_runtime_mark_last_busy(dev->dev);
 769         pm_runtime_put_autosuspend(dev->dev);
 770 }
 771
 772 /*
 773  * VBlank related functions.
 774  */
 775 /**
 776  * radeon_get_vblank_counter_kms - get frame count
 777  *
 778  * @dev: drm dev pointer
 779  * @pipe: crtc to get the frame count from
 780  *
 781  * Gets the frame count on the requested crtc (all asics).
 782  * Returns frame count on success, -EINVAL on failure.
 783  */
 784 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 785 {
 786         int vpos, hpos, stat;
 787         u32 count;
 788         struct radeon_device *rdev = dev->dev_private;
 789
 790         if (pipe >= rdev->num_crtc) {
 791                 DRM_ERROR("Invalid crtc %u\n", pipe);
 792                 return -EINVAL;
 793         }
 794
 795         /* The hw increments its frame counter at start of vsync, not at start
 796          * of vblank, as is required by DRM core vblank counter handling.
 797          * Cook the hw count here to make it appear to the caller as if it
 798          * incremented at start of vblank. We measure distance to start of
 799          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 800          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 801          * result by 1 to give the proper appearance to caller.
 802          */
 803         if (rdev->mode_info.crtcs[pipe]) {
 804                 /* Repeat readout if needed to provide stable result if
 805                  * we cross start of vsync during the queries.
 806                  */
 807                 do {
 808                         count = radeon_get_vblank_counter(rdev, pipe);
 809                         /* Ask radeon_get_crtc_scanoutpos to return vpos as
 810                          * distance to start of vblank, instead of regular
 811                          * vertical scanout pos.
 812                          */
 813                         stat = radeon_get_crtc_scanoutpos(
 814                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 815                                 &vpos, &hpos, NULL, NULL,
 816                                 &rdev->mode_info.crtcs[pipe]->base.hwmode);
 817                 } while (count != radeon_get_vblank_counter(rdev, pipe));
 818
 819                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 820                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 821                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 822                 }
 823                 else {
 824                         DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
 825                                       pipe, vpos);
 826
 827                         /* Bump counter if we are at >= leading edge of vblank,
 828                          * but before vsync where vpos would turn negative and
 829                          * the hw counter really increments.
 830                          */
 831                         if (vpos >= 0)
 832                                 count++;
 833                 }
 834         }
 835         else {
 836             /* Fallback to use value as is. */
 837             count = radeon_get_vblank_counter(rdev, pipe);
 838             DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 839         }
 840
 841         return count;
 842 }
 843
 844 /**
 845  * radeon_enable_vblank_kms - enable vblank interrupt
 846  *
 847  * @dev: drm dev pointer
 848  * @crtc: crtc to enable vblank interrupt for
 849  *
 850  * Enable the interrupt on the requested crtc (all asics).
 851  * Returns 0 on success, -EINVAL on failure.
 852  */
 853 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 854 {
 855         struct radeon_device *rdev = dev->dev_private;
 856         unsigned long irqflags;
 857         int r;
 858
 859         if (crtc < 0 || crtc >= rdev->num_crtc) {
 860                 DRM_ERROR("Invalid crtc %d\n", crtc);
 861                 return -EINVAL;
 862         }
 863
 864         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 865         rdev->irq.crtc_vblank_int[crtc] = true;
 866         r = radeon_irq_set(rdev);
 867         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 868         return r;
 869 }
 870
 871 /**
 872  * radeon_disable_vblank_kms - disable vblank interrupt
 873  *
 874  * @dev: drm dev pointer
 875  * @crtc: crtc to disable vblank interrupt for
 876  *
 877  * Disable the interrupt on the requested crtc (all asics).
 878  */
 879 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 880 {
 881         struct radeon_device *rdev = dev->dev_private;
 882         unsigned long irqflags;
 883
 884         if (crtc < 0 || crtc >= rdev->num_crtc) {
 885                 DRM_ERROR("Invalid crtc %d\n", crtc);
 886                 return;
 887         }
 888
 889         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 890         rdev->irq.crtc_vblank_int[crtc] = false;
 891         radeon_irq_set(rdev);
 892         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 893 }
 894
 895 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
 896         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 897         DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 898         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 899         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 900         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
 901         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
 902         DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
 903         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
 904         DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
 905         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
 906         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
 907         DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
 908         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
 909         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
 910         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 911         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
 912         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
 913         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
 914         DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
 915         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
 916         DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
 917         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 918         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
 919         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
 920         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
 921         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
 922         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
 923         /* KMS */
 924         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 925         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 926         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 927         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 928         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
 929         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
 930         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 931         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 932         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 933         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 934         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 935         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 936         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 937         DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 938         DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 939 };
 940 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);