drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_plane_helper.h>
  22 #ifdef CONFIG_DRM_ANALOGIX_DP
  23 #include <drm/bridge/analogix_dp.h>
  24 #endif
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <linux/iopoll.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/component.h>
  35
  36 #include <linux/reset.h>
  37 #include <linux/delay.h>
  38
  39 #include "rockchip_drm_drv.h"
  40 #include "rockchip_drm_gem.h"
  41 #include "rockchip_drm_fb.h"
  42 #include "rockchip_drm_psr.h"
  43 #include "rockchip_drm_vop.h"
  44
  45 #define VOP_WIN_SET(x, win, name, v) \
  46                 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
  47 #define VOP_SCL_SET(x, win, name, v) \
  48                 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
  49 #define VOP_SCL_SET_EXT(x, win, name, v) \
  50                 vop_reg_set(vop, &win->phy->scl->ext->name, \
  51                             win->base, ~0, v, #name)
  52
  53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  54                 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
  55
  56 #define VOP_REG_SET(vop, group, name, v) \
  57                     vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
  58
  59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  60         do { \
  61                 int i, reg = 0, mask = 0; \
  62                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  63                         if (vop->data->intr->intrs[i] & type) { \
  64                                 reg |= (v) << i; \
  65                                 mask |= 1 << i; \
  66                         } \
  67                 } \
  68                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
  69         } while (0)
  70 #define VOP_INTR_GET_TYPE(vop, name, type) \
  71                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  72
  73 #define VOP_WIN_GET(x, win, name) \
  74                 vop_read_reg(x, win->offset, win->phy->name)
  75
  76 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  77                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  78
  79 #define VOP_WIN_TO_INDEX(vop_win) \
  80         ((vop_win) - (vop_win)->vop->win)
  81
  82 #define to_vop(x) container_of(x, struct vop, crtc)
  83 #define to_vop_win(x) container_of(x, struct vop_win, base)
  84
  85 enum vop_pending {
  86         VOP_PENDING_FB_UNREF,
  87 };
  88
  89 struct vop_win {
  90         struct drm_plane base;
  91         const struct vop_win_data *data;
  92         struct vop *vop;
  93 };
  94
  95 struct vop {
  96         struct drm_crtc crtc;
  97         struct device *dev;
  98         struct drm_device *drm_dev;
  99         bool is_enabled;
 100
 101         struct completion dsp_hold_completion;
 102
 103         /* protected by dev->event_lock */
 104         struct drm_pending_vblank_event *event;
 105
 106         struct drm_flip_work fb_unref_work;
 107         unsigned long pending;
 108
 109         struct completion line_flag_completion;
 110
 111         const struct vop_data *data;
 112
 113         uint32_t *regsbak;
 114         void __iomem *regs;
 115
 116         /* physical map length of vop register */
 117         uint32_t len;
 118
 119         /* one time only one process allowed to config the register */
 120         spinlock_t reg_lock;
 121         /* lock vop irq reg */
 122         spinlock_t irq_lock;
 123         /* protects crtc enable/disable */
 124         struct mutex vop_lock;
 125
 126         unsigned int irq;
 127
 128         /* vop AHP clk */
 129         struct clk *hclk;
 130         /* vop dclk */
 131         struct clk *dclk;
 132         /* vop share memory frequency */
 133         struct clk *aclk;
 134
 135         /* vop dclk reset */
 136         struct reset_control *dclk_rst;
 137
 138         struct vop_win win[];
 139 };
 140
 141 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 142 {
 143         writel(v, vop->regs + offset);
 144         vop->regsbak[offset >> 2] = v;
 145 }
 146
 147 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 148 {
 149         return readl(vop->regs + offset);
 150 }
 151
 152 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 153                                     const struct vop_reg *reg)
 154 {
 155         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 156 }
 157
 158 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
 159                         uint32_t _offset, uint32_t _mask, uint32_t v,
 160                         const char *reg_name)
 161 {
 162         int offset, mask, shift;
 163
 164         if (!reg || !reg->mask) {
 165                 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
 166                 return;
 167         }
 168
 169         offset = reg->offset + _offset;
 170         mask = reg->mask & _mask;
 171         shift = reg->shift;
 172
 173         if (reg->write_mask) {
 174                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 175         } else {
 176                 uint32_t cached_val = vop->regsbak[offset >> 2];
 177
 178                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 179                 vop->regsbak[offset >> 2] = v;
 180         }
 181
 182         if (reg->relaxed)
 183                 writel_relaxed(v, vop->regs + offset);
 184         else
 185                 writel(v, vop->regs + offset);
 186 }
 187
 188 static inline uint32_t vop_get_intr_type(struct vop *vop,
 189                                          const struct vop_reg *reg, int type)
 190 {
 191         uint32_t i, ret = 0;
 192         uint32_t regs = vop_read_reg(vop, 0, reg);
 193
 194         for (i = 0; i < vop->data->intr->nintrs; i++) {
 195                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 196                         ret |= vop->data->intr->intrs[i];
 197         }
 198
 199         return ret;
 200 }
 201
 202 static inline void vop_cfg_done(struct vop *vop)
 203 {
 204         VOP_REG_SET(vop, common, cfg_done, 1);
 205 }
 206
 207 static bool has_rb_swapped(uint32_t format)
 208 {
 209         switch (format) {
 210         case DRM_FORMAT_XBGR8888:
 211         case DRM_FORMAT_ABGR8888:
 212         case DRM_FORMAT_BGR888:
 213         case DRM_FORMAT_BGR565:
 214                 return true;
 215         default:
 216                 return false;
 217         }
 218 }
 219
 220 static enum vop_data_format vop_convert_format(uint32_t format)
 221 {
 222         switch (format) {
 223         case DRM_FORMAT_XRGB8888:
 224         case DRM_FORMAT_ARGB8888:
 225         case DRM_FORMAT_XBGR8888:
 226         case DRM_FORMAT_ABGR8888:
 227                 return VOP_FMT_ARGB8888;
 228         case DRM_FORMAT_RGB888:
 229         case DRM_FORMAT_BGR888:
 230                 return VOP_FMT_RGB888;
 231         case DRM_FORMAT_RGB565:
 232         case DRM_FORMAT_BGR565:
 233                 return VOP_FMT_RGB565;
 234         case DRM_FORMAT_NV12:
 235                 return VOP_FMT_YUV420SP;
 236         case DRM_FORMAT_NV16:
 237                 return VOP_FMT_YUV422SP;
 238         case DRM_FORMAT_NV24:
 239                 return VOP_FMT_YUV444SP;
 240         default:
 241                 DRM_ERROR("unsupported format[%08x]\n", format);
 242                 return -EINVAL;
 243         }
 244 }
 245
 246 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 247                                   uint32_t dst, bool is_horizontal,
 248                                   int vsu_mode, int *vskiplines)
 249 {
 250         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 251
 252         if (vskiplines)
 253                 *vskiplines = 0;
 254
 255         if (is_horizontal) {
 256                 if (mode == SCALE_UP)
 257                         val = GET_SCL_FT_BIC(src, dst);
 258                 else if (mode == SCALE_DOWN)
 259                         val = GET_SCL_FT_BILI_DN(src, dst);
 260         } else {
 261                 if (mode == SCALE_UP) {
 262                         if (vsu_mode == SCALE_UP_BIL)
 263                                 val = GET_SCL_FT_BILI_UP(src, dst);
 264                         else
 265                                 val = GET_SCL_FT_BIC(src, dst);
 266                 } else if (mode == SCALE_DOWN) {
 267                         if (vskiplines) {
 268                                 *vskiplines = scl_get_vskiplines(src, dst);
 269                                 val = scl_get_bili_dn_vskip(src, dst,
 270                                                             *vskiplines);
 271                         } else {
 272                                 val = GET_SCL_FT_BILI_DN(src, dst);
 273                         }
 274                 }
 275         }
 276
 277         return val;
 278 }
 279
 280 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 281                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 282                              uint32_t dst_h, uint32_t pixel_format)
 283 {
 284         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 285         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 286         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 287         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 288         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 289         const struct drm_format_info *info;
 290         bool is_yuv = false;
 291         uint16_t cbcr_src_w = src_w / hsub;
 292         uint16_t cbcr_src_h = src_h / vsub;
 293         uint16_t vsu_mode;
 294         uint16_t lb_mode;
 295         uint32_t val;
 296         int vskiplines;
 297
 298         info = drm_format_info(pixel_format);
 299
 300         if (info->is_yuv)
 301                 is_yuv = true;
 302
 303         if (dst_w > 3840) {
 304                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 305                 return;
 306         }
 307
 308         if (!win->phy->scl->ext) {
 309                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 310                             scl_cal_scale2(src_w, dst_w));
 311                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 312                             scl_cal_scale2(src_h, dst_h));
 313                 if (is_yuv) {
 314                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 315                                     scl_cal_scale2(cbcr_src_w, dst_w));
 316                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 317                                     scl_cal_scale2(cbcr_src_h, dst_h));
 318                 }
 319                 return;
 320         }
 321
 322         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 323         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 324
 325         if (is_yuv) {
 326                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 327                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 328                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 329                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 330                 else
 331                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 332         } else {
 333                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 334                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 335                 else
 336                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 337         }
 338
 339         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 340         if (lb_mode == LB_RGB_3840X2) {
 341                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 342                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 343                         return;
 344                 }
 345                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 346                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 347                         return;
 348                 }
 349                 vsu_mode = SCALE_UP_BIL;
 350         } else if (lb_mode == LB_RGB_2560X4) {
 351                 vsu_mode = SCALE_UP_BIL;
 352         } else {
 353                 vsu_mode = SCALE_UP_BIC;
 354         }
 355
 356         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 357                                 true, 0, NULL);
 358         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 359         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 360                                 false, vsu_mode, &vskiplines);
 361         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 362
 363         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 364         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 365
 366         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 367         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 368         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 369         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 370         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 371         if (is_yuv) {
 372                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 373                                         dst_w, true, 0, NULL);
 374                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 375                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 376                                         dst_h, false, vsu_mode, &vskiplines);
 377                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 378
 379                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 380                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 381                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 382                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 383                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 384                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 385                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 386         }
 387 }
 388
 389 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 390 {
 391         unsigned long flags;
 392
 393         if (WARN_ON(!vop->is_enabled))
 394                 return;
 395
 396         spin_lock_irqsave(&vop->irq_lock, flags);
 397
 398         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 399         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 400
 401         spin_unlock_irqrestore(&vop->irq_lock, flags);
 402 }
 403
 404 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 405 {
 406         unsigned long flags;
 407
 408         if (WARN_ON(!vop->is_enabled))
 409                 return;
 410
 411         spin_lock_irqsave(&vop->irq_lock, flags);
 412
 413         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 414
 415         spin_unlock_irqrestore(&vop->irq_lock, flags);
 416 }
 417
 418 /*
 419  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 420  *     the "FRAME_SYNC" interrupt.
 421  * (2) the active data region of each frame ends at dsp_vact_end
 422  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 423  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 424  *
 425  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 426  * Interrupts
 427  * LINE_FLAG -------------------------------+
 428  * FRAME_SYNC ----+                         |
 429  *                |                         |
 430  *                v                         v
 431  *                | Vsync | Vbp |  Vactive  | Vfp |
 432  *                        ^     ^           ^     ^
 433  *                        |     |           |     |
 434  *                        |     |           |     |
 435  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 436  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 437  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 438  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 439  */
 440 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 441 {
 442         uint32_t line_flag_irq;
 443         unsigned long flags;
 444
 445         spin_lock_irqsave(&vop->irq_lock, flags);
 446
 447         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 448
 449         spin_unlock_irqrestore(&vop->irq_lock, flags);
 450
 451         return !!line_flag_irq;
 452 }
 453
 454 static void vop_line_flag_irq_enable(struct vop *vop)
 455 {
 456         unsigned long flags;
 457
 458         if (WARN_ON(!vop->is_enabled))
 459                 return;
 460
 461         spin_lock_irqsave(&vop->irq_lock, flags);
 462
 463         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 464         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 465
 466         spin_unlock_irqrestore(&vop->irq_lock, flags);
 467 }
 468
 469 static void vop_line_flag_irq_disable(struct vop *vop)
 470 {
 471         unsigned long flags;
 472
 473         if (WARN_ON(!vop->is_enabled))
 474                 return;
 475
 476         spin_lock_irqsave(&vop->irq_lock, flags);
 477
 478         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 479
 480         spin_unlock_irqrestore(&vop->irq_lock, flags);
 481 }
 482
 483 static int vop_core_clks_enable(struct vop *vop)
 484 {
 485         int ret;
 486
 487         ret = clk_enable(vop->hclk);
 488         if (ret < 0)
 489                 return ret;
 490
 491         ret = clk_enable(vop->aclk);
 492         if (ret < 0)
 493                 goto err_disable_hclk;
 494
 495         return 0;
 496
 497 err_disable_hclk:
 498         clk_disable(vop->hclk);
 499         return ret;
 500 }
 501
 502 static void vop_core_clks_disable(struct vop *vop)
 503 {
 504         clk_disable(vop->aclk);
 505         clk_disable(vop->hclk);
 506 }
 507
 508 static void vop_win_disable(struct vop *vop, const struct vop_win_data *win)
 509 {
 510         if (win->phy->scl && win->phy->scl->ext) {
 511                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 512                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 513                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 514                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 515         }
 516
 517         VOP_WIN_SET(vop, win, enable, 0);
 518 }
 519
 520 static int vop_enable(struct drm_crtc *crtc)
 521 {
 522         struct vop *vop = to_vop(crtc);
 523         int ret, i;
 524
 525         ret = pm_runtime_get_sync(vop->dev);
 526         if (ret < 0) {
 527                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
 528                 return ret;
 529         }
 530
 531         ret = vop_core_clks_enable(vop);
 532         if (WARN_ON(ret < 0))
 533                 goto err_put_pm_runtime;
 534
 535         ret = clk_enable(vop->dclk);
 536         if (WARN_ON(ret < 0))
 537                 goto err_disable_core;
 538
 539         /*
 540          * Slave iommu shares power, irq and clock with vop.  It was associated
 541          * automatically with this master device via common driver code.
 542          * Now that we have enabled the clock we attach it to the shared drm
 543          * mapping.
 544          */
 545         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 546         if (ret) {
 547                 DRM_DEV_ERROR(vop->dev,
 548                               "failed to attach dma mapping, %d\n", ret);
 549                 goto err_disable_dclk;
 550         }
 551
 552         spin_lock(&vop->reg_lock);
 553         for (i = 0; i < vop->len; i += 4)
 554                 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
 555
 556         /*
 557          * We need to make sure that all windows are disabled before we
 558          * enable the crtc. Otherwise we might try to scan from a destroyed
 559          * buffer later.
 560          */
 561         for (i = 0; i < vop->data->win_size; i++) {
 562                 struct vop_win *vop_win = &vop->win[i];
 563                 const struct vop_win_data *win = vop_win->data;
 564
 565                 vop_win_disable(vop, win);
 566         }
 567         spin_unlock(&vop->reg_lock);
 568
 569         vop_cfg_done(vop);
 570
 571         /*
 572          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 573          */
 574         vop->is_enabled = true;
 575
 576         spin_lock(&vop->reg_lock);
 577
 578         VOP_REG_SET(vop, common, standby, 1);
 579
 580         spin_unlock(&vop->reg_lock);
 581
 582         drm_crtc_vblank_on(crtc);
 583
 584         return 0;
 585
 586 err_disable_dclk:
 587         clk_disable(vop->dclk);
 588 err_disable_core:
 589         vop_core_clks_disable(vop);
 590 err_put_pm_runtime:
 591         pm_runtime_put_sync(vop->dev);
 592         return ret;
 593 }
 594
 595 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
 596                                     struct drm_crtc_state *old_state)
 597 {
 598         struct vop *vop = to_vop(crtc);
 599
 600         WARN_ON(vop->event);
 601
 602         mutex_lock(&vop->vop_lock);
 603         drm_crtc_vblank_off(crtc);
 604
 605         /*
 606          * Vop standby will take effect at end of current frame,
 607          * if dsp hold valid irq happen, it means standby complete.
 608          *
 609          * we must wait standby complete when we want to disable aclk,
 610          * if not, memory bus maybe dead.
 611          */
 612         reinit_completion(&vop->dsp_hold_completion);
 613         vop_dsp_hold_valid_irq_enable(vop);
 614
 615         spin_lock(&vop->reg_lock);
 616
 617         VOP_REG_SET(vop, common, standby, 1);
 618
 619         spin_unlock(&vop->reg_lock);
 620
 621         wait_for_completion(&vop->dsp_hold_completion);
 622
 623         vop_dsp_hold_valid_irq_disable(vop);
 624
 625         vop->is_enabled = false;
 626
 627         /*
 628          * vop standby complete, so iommu detach is safe.
 629          */
 630         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 631
 632         clk_disable(vop->dclk);
 633         vop_core_clks_disable(vop);
 634         pm_runtime_put(vop->dev);
 635         mutex_unlock(&vop->vop_lock);
 636
 637         if (crtc->state->event && !crtc->state->active) {
 638                 spin_lock_irq(&crtc->dev->event_lock);
 639                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 640                 spin_unlock_irq(&crtc->dev->event_lock);
 641
 642                 crtc->state->event = NULL;
 643         }
 644 }
 645
 646 static void vop_plane_destroy(struct drm_plane *plane)
 647 {
 648         drm_plane_cleanup(plane);
 649 }
 650
 651 static int vop_plane_atomic_check(struct drm_plane *plane,
 652                            struct drm_plane_state *state)
 653 {
 654         struct drm_crtc *crtc = state->crtc;
 655         struct drm_crtc_state *crtc_state;
 656         struct drm_framebuffer *fb = state->fb;
 657         struct vop_win *vop_win = to_vop_win(plane);
 658         const struct vop_win_data *win = vop_win->data;
 659         int ret;
 660         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 661                                         DRM_PLANE_HELPER_NO_SCALING;
 662         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 663                                         DRM_PLANE_HELPER_NO_SCALING;
 664
 665         if (!crtc || !fb)
 666                 return 0;
 667
 668         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 669         if (WARN_ON(!crtc_state))
 670                 return -EINVAL;
 671
 672         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 673                                                   min_scale, max_scale,
 674                                                   true, true);
 675         if (ret)
 676                 return ret;
 677
 678         if (!state->visible)
 679                 return 0;
 680
 681         ret = vop_convert_format(fb->format->format);
 682         if (ret < 0)
 683                 return ret;
 684
 685         /*
 686          * Src.x1 can be odd when do clip, but yuv plane start point
 687          * need align with 2 pixel.
 688          */
 689         if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
 690                 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
 691                 return -EINVAL;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static void vop_plane_atomic_disable(struct drm_plane *plane,
 698                                      struct drm_plane_state *old_state)
 699 {
 700         struct vop_win *vop_win = to_vop_win(plane);
 701         const struct vop_win_data *win = vop_win->data;
 702         struct vop *vop = to_vop(old_state->crtc);
 703
 704         if (!old_state->crtc)
 705                 return;
 706
 707         spin_lock(&vop->reg_lock);
 708
 709         vop_win_disable(vop, win);
 710
 711         spin_unlock(&vop->reg_lock);
 712 }
 713
 714 static void vop_plane_atomic_update(struct drm_plane *plane,
 715                 struct drm_plane_state *old_state)
 716 {
 717         struct drm_plane_state *state = plane->state;
 718         struct drm_crtc *crtc = state->crtc;
 719         struct vop_win *vop_win = to_vop_win(plane);
 720         const struct vop_win_data *win = vop_win->data;
 721         struct vop *vop = to_vop(state->crtc);
 722         struct drm_framebuffer *fb = state->fb;
 723         unsigned int actual_w, actual_h;
 724         unsigned int dsp_stx, dsp_sty;
 725         uint32_t act_info, dsp_info, dsp_st;
 726         struct drm_rect *src = &state->src;
 727         struct drm_rect *dest = &state->dst;
 728         struct drm_gem_object *obj, *uv_obj;
 729         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 730         unsigned long offset;
 731         dma_addr_t dma_addr;
 732         uint32_t val;
 733         bool rb_swap;
 734         int win_index = VOP_WIN_TO_INDEX(vop_win);
 735         int format;
 736
 737         /*
 738          * can't update plane when vop is disabled.
 739          */
 740         if (WARN_ON(!crtc))
 741                 return;
 742
 743         if (WARN_ON(!vop->is_enabled))
 744                 return;
 745
 746         if (!state->visible) {
 747                 vop_plane_atomic_disable(plane, old_state);
 748                 return;
 749         }
 750
 751         obj = fb->obj[0];
 752         rk_obj = to_rockchip_obj(obj);
 753
 754         actual_w = drm_rect_width(src) >> 16;
 755         actual_h = drm_rect_height(src) >> 16;
 756         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 757
 758         dsp_info = (drm_rect_height(dest) - 1) << 16;
 759         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 760
 761         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 762         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 763         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 764
 765         offset = (src->x1 >> 16) * fb->format->cpp[0];
 766         offset += (src->y1 >> 16) * fb->pitches[0];
 767         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 768
 769         format = vop_convert_format(fb->format->format);
 770
 771         spin_lock(&vop->reg_lock);
 772
 773         VOP_WIN_SET(vop, win, format, format);
 774         VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
 775         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 776         if (fb->format->is_yuv) {
 777                 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
 778                 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
 779                 int bpp = fb->format->cpp[1];
 780
 781                 uv_obj = fb->obj[1];
 782                 rk_uv_obj = to_rockchip_obj(uv_obj);
 783
 784                 offset = (src->x1 >> 16) * bpp / hsub;
 785                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 786
 787                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 788                 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 789                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 790         }
 791
 792         if (win->phy->scl)
 793                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 794                                     drm_rect_width(dest), drm_rect_height(dest),
 795                                     fb->format->format);
 796
 797         VOP_WIN_SET(vop, win, act_info, act_info);
 798         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 799         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 800
 801         rb_swap = has_rb_swapped(fb->format->format);
 802         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 803
 804         /*
 805          * Blending win0 with the background color doesn't seem to work
 806          * correctly. We only get the background color, no matter the contents
 807          * of the win0 framebuffer.  However, blending pre-multiplied color
 808          * with the default opaque black default background color is a no-op,
 809          * so we can just disable blending to get the correct result.
 810          */
 811         if (fb->format->has_alpha && win_index > 0) {
 812                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 813                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 814                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 815                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 816                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 817                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 818                         SRC_FACTOR_M0(ALPHA_ONE);
 819                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 820         } else {
 821                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 822         }
 823
 824         VOP_WIN_SET(vop, win, enable, 1);
 825         spin_unlock(&vop->reg_lock);
 826 }
 827
 828 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 829         .atomic_check = vop_plane_atomic_check,
 830         .atomic_update = vop_plane_atomic_update,
 831         .atomic_disable = vop_plane_atomic_disable,
 832 };
 833
 834 static const struct drm_plane_funcs vop_plane_funcs = {
 835         .update_plane   = drm_atomic_helper_update_plane,
 836         .disable_plane  = drm_atomic_helper_disable_plane,
 837         .destroy = vop_plane_destroy,
 838         .reset = drm_atomic_helper_plane_reset,
 839         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 840         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 841 };
 842
 843 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 844 {
 845         struct vop *vop = to_vop(crtc);
 846         unsigned long flags;
 847
 848         if (WARN_ON(!vop->is_enabled))
 849                 return -EPERM;
 850
 851         spin_lock_irqsave(&vop->irq_lock, flags);
 852
 853         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
 854         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 855
 856         spin_unlock_irqrestore(&vop->irq_lock, flags);
 857
 858         return 0;
 859 }
 860
 861 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 862 {
 863         struct vop *vop = to_vop(crtc);
 864         unsigned long flags;
 865
 866         if (WARN_ON(!vop->is_enabled))
 867                 return;
 868
 869         spin_lock_irqsave(&vop->irq_lock, flags);
 870
 871         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 872
 873         spin_unlock_irqrestore(&vop->irq_lock, flags);
 874 }
 875
 876 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 877                                 const struct drm_display_mode *mode,
 878                                 struct drm_display_mode *adjusted_mode)
 879 {
 880         struct vop *vop = to_vop(crtc);
 881
 882         adjusted_mode->clock =
 883                 DIV_ROUND_UP(clk_round_rate(vop->dclk, mode->clock * 1000),
 884                              1000);
 885
 886         return true;
 887 }
 888
 889 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
 890                                    struct drm_crtc_state *old_state)
 891 {
 892         struct vop *vop = to_vop(crtc);
 893         const struct vop_data *vop_data = vop->data;
 894         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 895         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 896         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 897         u16 hdisplay = adjusted_mode->hdisplay;
 898         u16 htotal = adjusted_mode->htotal;
 899         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 900         u16 hact_end = hact_st + hdisplay;
 901         u16 vdisplay = adjusted_mode->vdisplay;
 902         u16 vtotal = adjusted_mode->vtotal;
 903         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 904         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 905         u16 vact_end = vact_st + vdisplay;
 906         uint32_t pin_pol, val;
 907         int ret;
 908
 909         mutex_lock(&vop->vop_lock);
 910
 911         WARN_ON(vop->event);
 912
 913         ret = vop_enable(crtc);
 914         if (ret) {
 915                 mutex_unlock(&vop->vop_lock);
 916                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
 917                 return;
 918         }
 919
 920         pin_pol = BIT(DCLK_INVERT);
 921         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
 922                    BIT(HSYNC_POSITIVE) : 0;
 923         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
 924                    BIT(VSYNC_POSITIVE) : 0;
 925         VOP_REG_SET(vop, output, pin_pol, pin_pol);
 926
 927         switch (s->output_type) {
 928         case DRM_MODE_CONNECTOR_LVDS:
 929                 VOP_REG_SET(vop, output, rgb_en, 1);
 930                 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
 931                 break;
 932         case DRM_MODE_CONNECTOR_eDP:
 933                 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
 934                 VOP_REG_SET(vop, output, edp_en, 1);
 935                 break;
 936         case DRM_MODE_CONNECTOR_HDMIA:
 937                 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
 938                 VOP_REG_SET(vop, output, hdmi_en, 1);
 939                 break;
 940         case DRM_MODE_CONNECTOR_DSI:
 941                 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
 942                 VOP_REG_SET(vop, output, mipi_en, 1);
 943                 break;
 944         case DRM_MODE_CONNECTOR_DisplayPort:
 945                 pin_pol &= ~BIT(DCLK_INVERT);
 946                 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
 947                 VOP_REG_SET(vop, output, dp_en, 1);
 948                 break;
 949         default:
 950                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
 951                               s->output_type);
 952         }
 953
 954         /*
 955          * if vop is not support RGB10 output, need force RGB10 to RGB888.
 956          */
 957         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
 958             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
 959                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 960
 961         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8)
 962                 VOP_REG_SET(vop, common, pre_dither_down, 1);
 963         else
 964                 VOP_REG_SET(vop, common, pre_dither_down, 0);
 965
 966         VOP_REG_SET(vop, common, out_mode, s->output_mode);
 967
 968         VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
 969         val = hact_st << 16;
 970         val |= hact_end;
 971         VOP_REG_SET(vop, modeset, hact_st_end, val);
 972         VOP_REG_SET(vop, modeset, hpost_st_end, val);
 973
 974         VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
 975         val = vact_st << 16;
 976         val |= vact_end;
 977         VOP_REG_SET(vop, modeset, vact_st_end, val);
 978         VOP_REG_SET(vop, modeset, vpost_st_end, val);
 979
 980         VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
 981
 982         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 983
 984         VOP_REG_SET(vop, common, standby, 0);
 985         mutex_unlock(&vop->vop_lock);
 986 }
 987
 988 static bool vop_fs_irq_is_pending(struct vop *vop)
 989 {
 990         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 991 }
 992
 993 static void vop_wait_for_irq_handler(struct vop *vop)
 994 {
 995         bool pending;
 996         int ret;
 997
 998         /*
 999          * Spin until frame start interrupt status bit goes low, which means
1000          * that interrupt handler was invoked and cleared it. The timeout of
1001          * 10 msecs is really too long, but it is just a safety measure if
1002          * something goes really wrong. The wait will only happen in the very
1003          * unlikely case of a vblank happening exactly at the same time and
1004          * shouldn't exceed microseconds range.
1005          */
1006         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1007                                         !pending, 0, 10 * 1000);
1008         if (ret)
1009                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1010
1011         synchronize_irq(vop->irq);
1012 }
1013
1014 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1015                                   struct drm_crtc_state *old_crtc_state)
1016 {
1017         struct drm_atomic_state *old_state = old_crtc_state->state;
1018         struct drm_plane_state *old_plane_state, *new_plane_state;
1019         struct vop *vop = to_vop(crtc);
1020         struct drm_plane *plane;
1021         int i;
1022
1023         if (WARN_ON(!vop->is_enabled))
1024                 return;
1025
1026         spin_lock(&vop->reg_lock);
1027
1028         vop_cfg_done(vop);
1029
1030         spin_unlock(&vop->reg_lock);
1031
1032         /*
1033          * There is a (rather unlikely) possiblity that a vblank interrupt
1034          * fired before we set the cfg_done bit. To avoid spuriously
1035          * signalling flip completion we need to wait for it to finish.
1036          */
1037         vop_wait_for_irq_handler(vop);
1038
1039         spin_lock_irq(&crtc->dev->event_lock);
1040         if (crtc->state->event) {
1041                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1042                 WARN_ON(vop->event);
1043
1044                 vop->event = crtc->state->event;
1045                 crtc->state->event = NULL;
1046         }
1047         spin_unlock_irq(&crtc->dev->event_lock);
1048
1049         for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1050                                        new_plane_state, i) {
1051                 if (!old_plane_state->fb)
1052                         continue;
1053
1054                 if (old_plane_state->fb == new_plane_state->fb)
1055                         continue;
1056
1057                 drm_framebuffer_get(old_plane_state->fb);
1058                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1059                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1060                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1061         }
1062 }
1063
1064 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1065         .mode_fixup = vop_crtc_mode_fixup,
1066         .atomic_flush = vop_crtc_atomic_flush,
1067         .atomic_enable = vop_crtc_atomic_enable,
1068         .atomic_disable = vop_crtc_atomic_disable,
1069 };
1070
1071 static void vop_crtc_destroy(struct drm_crtc *crtc)
1072 {
1073         drm_crtc_cleanup(crtc);
1074 }
1075
1076 static void vop_crtc_reset(struct drm_crtc *crtc)
1077 {
1078         if (crtc->state)
1079                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1080         kfree(crtc->state);
1081
1082         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1083         if (crtc->state)
1084                 crtc->state->crtc = crtc;
1085 }
1086
1087 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1088 {
1089         struct rockchip_crtc_state *rockchip_state;
1090
1091         if (WARN_ON(!crtc->state))
1092                 return NULL;
1093
1094         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1095         if (!rockchip_state)
1096                 return NULL;
1097
1098         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1099         return &rockchip_state->base;
1100 }
1101
1102 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1103                                    struct drm_crtc_state *state)
1104 {
1105         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1106
1107         __drm_atomic_helper_crtc_destroy_state(&s->base);
1108         kfree(s);
1109 }
1110
1111 #ifdef CONFIG_DRM_ANALOGIX_DP
1112 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1113 {
1114         struct drm_connector *connector;
1115         struct drm_connector_list_iter conn_iter;
1116
1117         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1118         drm_for_each_connector_iter(connector, &conn_iter) {
1119                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1120                         drm_connector_list_iter_end(&conn_iter);
1121                         return connector;
1122                 }
1123         }
1124         drm_connector_list_iter_end(&conn_iter);
1125
1126         return NULL;
1127 }
1128
1129 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1130                                    const char *source_name, size_t *values_cnt)
1131 {
1132         struct vop *vop = to_vop(crtc);
1133         struct drm_connector *connector;
1134         int ret;
1135
1136         connector = vop_get_edp_connector(vop);
1137         if (!connector)
1138                 return -EINVAL;
1139
1140         *values_cnt = 3;
1141
1142         if (source_name && strcmp(source_name, "auto") == 0)
1143                 ret = analogix_dp_start_crc(connector);
1144         else if (!source_name)
1145                 ret = analogix_dp_stop_crc(connector);
1146         else
1147                 ret = -EINVAL;
1148
1149         return ret;
1150 }
1151 #else
1152 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1153                                    const char *source_name, size_t *values_cnt)
1154 {
1155         return -ENODEV;
1156 }
1157 #endif
1158
1159 static const struct drm_crtc_funcs vop_crtc_funcs = {
1160         .set_config = drm_atomic_helper_set_config,
1161         .page_flip = drm_atomic_helper_page_flip,
1162         .destroy = vop_crtc_destroy,
1163         .reset = vop_crtc_reset,
1164         .atomic_duplicate_state = vop_crtc_duplicate_state,
1165         .atomic_destroy_state = vop_crtc_destroy_state,
1166         .enable_vblank = vop_crtc_enable_vblank,
1167         .disable_vblank = vop_crtc_disable_vblank,
1168         .set_crc_source = vop_crtc_set_crc_source,
1169 };
1170
1171 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1172 {
1173         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1174         struct drm_framebuffer *fb = val;
1175
1176         drm_crtc_vblank_put(&vop->crtc);
1177         drm_framebuffer_put(fb);
1178 }
1179
1180 static void vop_handle_vblank(struct vop *vop)
1181 {
1182         struct drm_device *drm = vop->drm_dev;
1183         struct drm_crtc *crtc = &vop->crtc;
1184
1185         spin_lock(&drm->event_lock);
1186         if (vop->event) {
1187                 drm_crtc_send_vblank_event(crtc, vop->event);
1188                 drm_crtc_vblank_put(crtc);
1189                 vop->event = NULL;
1190         }
1191         spin_unlock(&drm->event_lock);
1192
1193         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1194                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1195 }
1196
1197 static irqreturn_t vop_isr(int irq, void *data)
1198 {
1199         struct vop *vop = data;
1200         struct drm_crtc *crtc = &vop->crtc;
1201         uint32_t active_irqs;
1202         int ret = IRQ_NONE;
1203
1204         /*
1205          * The irq is shared with the iommu. If the runtime-pm state of the
1206          * vop-device is disabled the irq has to be targeted at the iommu.
1207          */
1208         if (!pm_runtime_get_if_in_use(vop->dev))
1209                 return IRQ_NONE;
1210
1211         if (vop_core_clks_enable(vop)) {
1212                 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1213                 goto out;
1214         }
1215
1216         /*
1217          * interrupt register has interrupt status, enable and clear bits, we
1218          * must hold irq_lock to avoid a race with enable/disable_vblank().
1219         */
1220         spin_lock(&vop->irq_lock);
1221
1222         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1223         /* Clear all active interrupt sources */
1224         if (active_irqs)
1225                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1226
1227         spin_unlock(&vop->irq_lock);
1228
1229         /* This is expected for vop iommu irqs, since the irq is shared */
1230         if (!active_irqs)
1231                 goto out_disable;
1232
1233         if (active_irqs & DSP_HOLD_VALID_INTR) {
1234                 complete(&vop->dsp_hold_completion);
1235                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1236                 ret = IRQ_HANDLED;
1237         }
1238
1239         if (active_irqs & LINE_FLAG_INTR) {
1240                 complete(&vop->line_flag_completion);
1241                 active_irqs &= ~LINE_FLAG_INTR;
1242                 ret = IRQ_HANDLED;
1243         }
1244
1245         if (active_irqs & FS_INTR) {
1246                 drm_crtc_handle_vblank(crtc);
1247                 vop_handle_vblank(vop);
1248                 active_irqs &= ~FS_INTR;
1249                 ret = IRQ_HANDLED;
1250         }
1251
1252         /* Unhandled irqs are spurious. */
1253         if (active_irqs)
1254                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1255                               active_irqs);
1256
1257 out_disable:
1258         vop_core_clks_disable(vop);
1259 out:
1260         pm_runtime_put(vop->dev);
1261         return ret;
1262 }
1263
1264 static int vop_create_crtc(struct vop *vop)
1265 {
1266         const struct vop_data *vop_data = vop->data;
1267         struct device *dev = vop->dev;
1268         struct drm_device *drm_dev = vop->drm_dev;
1269         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1270         struct drm_crtc *crtc = &vop->crtc;
1271         struct device_node *port;
1272         int ret;
1273         int i;
1274
1275         /*
1276          * Create drm_plane for primary and cursor planes first, since we need
1277          * to pass them to drm_crtc_init_with_planes, which sets the
1278          * "possible_crtcs" to the newly initialized crtc.
1279          */
1280         for (i = 0; i < vop_data->win_size; i++) {
1281                 struct vop_win *vop_win = &vop->win[i];
1282                 const struct vop_win_data *win_data = vop_win->data;
1283
1284                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1285                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1286                         continue;
1287
1288                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1289                                                0, &vop_plane_funcs,
1290                                                win_data->phy->data_formats,
1291                                                win_data->phy->nformats,
1292                                                NULL, win_data->type, NULL);
1293                 if (ret) {
1294                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1295                                       ret);
1296                         goto err_cleanup_planes;
1297                 }
1298
1299                 plane = &vop_win->base;
1300                 drm_plane_helper_add(plane, &plane_helper_funcs);
1301                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1302                         primary = plane;
1303                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1304                         cursor = plane;
1305         }
1306
1307         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1308                                         &vop_crtc_funcs, NULL);
1309         if (ret)
1310                 goto err_cleanup_planes;
1311
1312         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1313
1314         /*
1315          * Create drm_planes for overlay windows with possible_crtcs restricted
1316          * to the newly created crtc.
1317          */
1318         for (i = 0; i < vop_data->win_size; i++) {
1319                 struct vop_win *vop_win = &vop->win[i];
1320                 const struct vop_win_data *win_data = vop_win->data;
1321                 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1322
1323                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1324                         continue;
1325
1326                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1327                                                possible_crtcs,
1328                                                &vop_plane_funcs,
1329                                                win_data->phy->data_formats,
1330                                                win_data->phy->nformats,
1331                                                NULL, win_data->type, NULL);
1332                 if (ret) {
1333                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1334                                       ret);
1335                         goto err_cleanup_crtc;
1336                 }
1337                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1338         }
1339
1340         port = of_get_child_by_name(dev->of_node, "port");
1341         if (!port) {
1342                 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1343                               dev->of_node);
1344                 ret = -ENOENT;
1345                 goto err_cleanup_crtc;
1346         }
1347
1348         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1349                            vop_fb_unref_worker);
1350
1351         init_completion(&vop->dsp_hold_completion);
1352         init_completion(&vop->line_flag_completion);
1353         crtc->port = port;
1354
1355         return 0;
1356
1357 err_cleanup_crtc:
1358         drm_crtc_cleanup(crtc);
1359 err_cleanup_planes:
1360         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1361                                  head)
1362                 drm_plane_cleanup(plane);
1363         return ret;
1364 }
1365
1366 static void vop_destroy_crtc(struct vop *vop)
1367 {
1368         struct drm_crtc *crtc = &vop->crtc;
1369         struct drm_device *drm_dev = vop->drm_dev;
1370         struct drm_plane *plane, *tmp;
1371
1372         of_node_put(crtc->port);
1373
1374         /*
1375          * We need to cleanup the planes now.  Why?
1376          *
1377          * The planes are "&vop->win[i].base".  That means the memory is
1378          * all part of the big "struct vop" chunk of memory.  That memory
1379          * was devm allocated and associated with this component.  We need to
1380          * free it ourselves before vop_unbind() finishes.
1381          */
1382         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1383                                  head)
1384                 vop_plane_destroy(plane);
1385
1386         /*
1387          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1388          * references the CRTC.
1389          */
1390         drm_crtc_cleanup(crtc);
1391         drm_flip_work_cleanup(&vop->fb_unref_work);
1392 }
1393
1394 static int vop_initial(struct vop *vop)
1395 {
1396         const struct vop_data *vop_data = vop->data;
1397         struct reset_control *ahb_rst;
1398         int i, ret;
1399
1400         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1401         if (IS_ERR(vop->hclk)) {
1402                 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1403                 return PTR_ERR(vop->hclk);
1404         }
1405         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1406         if (IS_ERR(vop->aclk)) {
1407                 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1408                 return PTR_ERR(vop->aclk);
1409         }
1410         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1411         if (IS_ERR(vop->dclk)) {
1412                 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1413                 return PTR_ERR(vop->dclk);
1414         }
1415
1416         ret = pm_runtime_get_sync(vop->dev);
1417         if (ret < 0) {
1418                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1419                 return ret;
1420         }
1421
1422         ret = clk_prepare(vop->dclk);
1423         if (ret < 0) {
1424                 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1425                 goto err_put_pm_runtime;
1426         }
1427
1428         /* Enable both the hclk and aclk to setup the vop */
1429         ret = clk_prepare_enable(vop->hclk);
1430         if (ret < 0) {
1431                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1432                 goto err_unprepare_dclk;
1433         }
1434
1435         ret = clk_prepare_enable(vop->aclk);
1436         if (ret < 0) {
1437                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1438                 goto err_disable_hclk;
1439         }
1440
1441         /*
1442          * do hclk_reset, reset all vop registers.
1443          */
1444         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1445         if (IS_ERR(ahb_rst)) {
1446                 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1447                 ret = PTR_ERR(ahb_rst);
1448                 goto err_disable_aclk;
1449         }
1450         reset_control_assert(ahb_rst);
1451         usleep_range(10, 20);
1452         reset_control_deassert(ahb_rst);
1453
1454         VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1455         VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1456
1457         for (i = 0; i < vop->len; i += sizeof(u32))
1458                 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1459
1460         VOP_REG_SET(vop, misc, global_regdone_en, 1);
1461         VOP_REG_SET(vop, common, dsp_blank, 0);
1462
1463         for (i = 0; i < vop_data->win_size; i++) {
1464                 const struct vop_win_data *win = &vop_data->win[i];
1465                 int channel = i * 2 + 1;
1466
1467                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1468                 vop_win_disable(vop, win);
1469                 VOP_WIN_SET(vop, win, gate, 1);
1470         }
1471
1472         vop_cfg_done(vop);
1473
1474         /*
1475          * do dclk_reset, let all config take affect.
1476          */
1477         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1478         if (IS_ERR(vop->dclk_rst)) {
1479                 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1480                 ret = PTR_ERR(vop->dclk_rst);
1481                 goto err_disable_aclk;
1482         }
1483         reset_control_assert(vop->dclk_rst);
1484         usleep_range(10, 20);
1485         reset_control_deassert(vop->dclk_rst);
1486
1487         clk_disable(vop->hclk);
1488         clk_disable(vop->aclk);
1489
1490         vop->is_enabled = false;
1491
1492         pm_runtime_put_sync(vop->dev);
1493
1494         return 0;
1495
1496 err_disable_aclk:
1497         clk_disable_unprepare(vop->aclk);
1498 err_disable_hclk:
1499         clk_disable_unprepare(vop->hclk);
1500 err_unprepare_dclk:
1501         clk_unprepare(vop->dclk);
1502 err_put_pm_runtime:
1503         pm_runtime_put_sync(vop->dev);
1504         return ret;
1505 }
1506
1507 /*
1508  * Initialize the vop->win array elements.
1509  */
1510 static void vop_win_init(struct vop *vop)
1511 {
1512         const struct vop_data *vop_data = vop->data;
1513         unsigned int i;
1514
1515         for (i = 0; i < vop_data->win_size; i++) {
1516                 struct vop_win *vop_win = &vop->win[i];
1517                 const struct vop_win_data *win_data = &vop_data->win[i];
1518
1519                 vop_win->data = win_data;
1520                 vop_win->vop = vop;
1521         }
1522 }
1523
1524 /**
1525  * rockchip_drm_wait_vact_end
1526  * @crtc: CRTC to enable line flag
1527  * @mstimeout: millisecond for timeout
1528  *
1529  * Wait for vact_end line flag irq or timeout.
1530  *
1531  * Returns:
1532  * Zero on success, negative errno on failure.
1533  */
1534 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1535 {
1536         struct vop *vop = to_vop(crtc);
1537         unsigned long jiffies_left;
1538         int ret = 0;
1539
1540         if (!crtc || !vop->is_enabled)
1541                 return -ENODEV;
1542
1543         mutex_lock(&vop->vop_lock);
1544         if (mstimeout <= 0) {
1545                 ret = -EINVAL;
1546                 goto out;
1547         }
1548
1549         if (vop_line_flag_irq_is_enabled(vop)) {
1550                 ret = -EBUSY;
1551                 goto out;
1552         }
1553
1554         reinit_completion(&vop->line_flag_completion);
1555         vop_line_flag_irq_enable(vop);
1556
1557         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1558                                                    msecs_to_jiffies(mstimeout));
1559         vop_line_flag_irq_disable(vop);
1560
1561         if (jiffies_left == 0) {
1562                 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
1563                 ret = -ETIMEDOUT;
1564                 goto out;
1565         }
1566
1567 out:
1568         mutex_unlock(&vop->vop_lock);
1569         return ret;
1570 }
1571 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1572
1573 static int vop_bind(struct device *dev, struct device *master, void *data)
1574 {
1575         struct platform_device *pdev = to_platform_device(dev);
1576         const struct vop_data *vop_data;
1577         struct drm_device *drm_dev = data;
1578         struct vop *vop;
1579         struct resource *res;
1580         size_t alloc_size;
1581         int ret, irq;
1582
1583         vop_data = of_device_get_match_data(dev);
1584         if (!vop_data)
1585                 return -ENODEV;
1586
1587         /* Allocate vop struct and its vop_win array */
1588         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1589         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1590         if (!vop)
1591                 return -ENOMEM;
1592
1593         vop->dev = dev;
1594         vop->data = vop_data;
1595         vop->drm_dev = drm_dev;
1596         dev_set_drvdata(dev, vop);
1597
1598         vop_win_init(vop);
1599
1600         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1601         vop->regs = devm_ioremap_resource(dev, res);
1602         if (IS_ERR(vop->regs))
1603                 return PTR_ERR(vop->regs);
1604         vop->len = resource_size(res);
1605
1606         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1607         if (!vop->regsbak)
1608                 return -ENOMEM;
1609
1610         irq = platform_get_irq(pdev, 0);
1611         if (irq < 0) {
1612                 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
1613                 return irq;
1614         }
1615         vop->irq = (unsigned int)irq;
1616
1617         spin_lock_init(&vop->reg_lock);
1618         spin_lock_init(&vop->irq_lock);
1619         mutex_init(&vop->vop_lock);
1620
1621         ret = vop_create_crtc(vop);
1622         if (ret)
1623                 return ret;
1624
1625         pm_runtime_enable(&pdev->dev);
1626
1627         ret = vop_initial(vop);
1628         if (ret < 0) {
1629                 DRM_DEV_ERROR(&pdev->dev,
1630                               "cannot initial vop dev - err %d\n", ret);
1631                 goto err_disable_pm_runtime;
1632         }
1633
1634         ret = devm_request_irq(dev, vop->irq, vop_isr,
1635                                IRQF_SHARED, dev_name(dev), vop);
1636         if (ret)
1637                 goto err_disable_pm_runtime;
1638
1639         return 0;
1640
1641 err_disable_pm_runtime:
1642         pm_runtime_disable(&pdev->dev);
1643         vop_destroy_crtc(vop);
1644         return ret;
1645 }
1646
1647 static void vop_unbind(struct device *dev, struct device *master, void *data)
1648 {
1649         struct vop *vop = dev_get_drvdata(dev);
1650
1651         pm_runtime_disable(dev);
1652         vop_destroy_crtc(vop);
1653
1654         clk_unprepare(vop->aclk);
1655         clk_unprepare(vop->hclk);
1656         clk_unprepare(vop->dclk);
1657 }
1658
1659 const struct component_ops vop_component_ops = {
1660         .bind = vop_bind,
1661         .unbind = vop_unbind,
1662 };
1663 EXPORT_SYMBOL_GPL(vop_component_ops);