drivers/gpu/drm/sun4i/sun4i_backend.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_fb_cma_helper.h>
  18 #include <drm/drm_gem_cma_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <linux/component.h>
  22 #include <linux/reset.h>
  23
  24 #include "sun4i_backend.h"
  25 #include "sun4i_drv.h"
  26
  27 static u32 sunxi_rgb2yuv_coef[12] = {
  28         0x00000107, 0x00000204, 0x00000064, 0x00000108,
  29         0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  30         0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  31 };
  32
  33 void sun4i_backend_apply_color_correction(struct sun4i_backend *backend)
  34 {
  35         int i;
  36
  37         DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
  38
  39         /* Set color correction */
  40         regmap_write(backend->regs, SUN4I_BACKEND_OCCTL_REG,
  41                      SUN4I_BACKEND_OCCTL_ENABLE);
  42
  43         for (i = 0; i < 12; i++)
  44                 regmap_write(backend->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
  45                              sunxi_rgb2yuv_coef[i]);
  46 }
  47 EXPORT_SYMBOL(sun4i_backend_apply_color_correction);
  48
  49 void sun4i_backend_disable_color_correction(struct sun4i_backend *backend)
  50 {
  51         DRM_DEBUG_DRIVER("Disabling color correction\n");
  52
  53         /* Disable color correction */
  54         regmap_update_bits(backend->regs, SUN4I_BACKEND_OCCTL_REG,
  55                            SUN4I_BACKEND_OCCTL_ENABLE, 0);
  56 }
  57 EXPORT_SYMBOL(sun4i_backend_disable_color_correction);
  58
  59 void sun4i_backend_commit(struct sun4i_backend *backend)
  60 {
  61         DRM_DEBUG_DRIVER("Committing changes\n");
  62
  63         regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
  64                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
  65                      SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
  66 }
  67 EXPORT_SYMBOL(sun4i_backend_commit);
  68
  69 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
  70                                 int layer, bool enable)
  71 {
  72         u32 val;
  73
  74         DRM_DEBUG_DRIVER("Enabling layer %d\n", layer);
  75
  76         if (enable)
  77                 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
  78         else
  79                 val = 0;
  80
  81         regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
  82                            SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
  83 }
  84 EXPORT_SYMBOL(sun4i_backend_layer_enable);
  85
  86 static int sun4i_backend_drm_format_to_layer(struct drm_plane *plane,
  87                                              u32 format, u32 *mode)
  88 {
  89         if ((plane->type == DRM_PLANE_TYPE_PRIMARY) &&
  90             (format == DRM_FORMAT_ARGB8888))
  91                 format = DRM_FORMAT_XRGB8888;
  92
  93         switch (format) {
  94         case DRM_FORMAT_ARGB8888:
  95                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
  96                 break;
  97
  98         case DRM_FORMAT_XRGB8888:
  99                 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
 100                 break;
 101
 102         case DRM_FORMAT_RGB888:
 103                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
 104                 break;
 105
 106         default:
 107                 return -EINVAL;
 108         }
 109
 110         return 0;
 111 }
 112
 113 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 114                                      int layer, struct drm_plane *plane)
 115 {
 116         struct drm_plane_state *state = plane->state;
 117         struct drm_framebuffer *fb = state->fb;
 118
 119         DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 120
 121         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 122                 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
 123                                  state->crtc_w, state->crtc_h);
 124                 regmap_write(backend->regs, SUN4I_BACKEND_DISSIZE_REG,
 125                              SUN4I_BACKEND_DISSIZE(state->crtc_w,
 126                                                    state->crtc_h));
 127         }
 128
 129         /* Set the line width */
 130         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 131         regmap_write(backend->regs, SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
 132                      fb->pitches[0] * 8);
 133
 134         /* Set height and width */
 135         DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
 136                          state->crtc_w, state->crtc_h);
 137         regmap_write(backend->regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
 138                      SUN4I_BACKEND_LAYSIZE(state->crtc_w,
 139                                            state->crtc_h));
 140
 141         /* Set base coordinates */
 142         DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
 143                          state->crtc_x, state->crtc_y);
 144         regmap_write(backend->regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
 145                      SUN4I_BACKEND_LAYCOOR(state->crtc_x,
 146                                            state->crtc_y));
 147
 148         return 0;
 149 }
 150 EXPORT_SYMBOL(sun4i_backend_update_layer_coord);
 151
 152 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 153                                        int layer, struct drm_plane *plane)
 154 {
 155         struct drm_plane_state *state = plane->state;
 156         struct drm_framebuffer *fb = state->fb;
 157         bool interlaced = false;
 158         u32 val;
 159         int ret;
 160
 161         if (plane->state->crtc)
 162                 interlaced = plane->state->crtc->state->adjusted_mode.flags
 163                         & DRM_MODE_FLAG_INTERLACE;
 164
 165         regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
 166                            SUN4I_BACKEND_MODCTL_ITLMOD_EN,
 167                            interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
 168
 169         DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
 170                          interlaced ? "on" : "off");
 171
 172         ret = sun4i_backend_drm_format_to_layer(plane, fb->pixel_format, &val);
 173         if (ret) {
 174                 DRM_DEBUG_DRIVER("Invalid format\n");
 175                 return val;
 176         }
 177
 178         regmap_update_bits(backend->regs, SUN4I_BACKEND_ATTCTL_REG1(layer),
 179                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 180
 181         return 0;
 182 }
 183 EXPORT_SYMBOL(sun4i_backend_update_layer_formats);
 184
 185 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 186                                       int layer, struct drm_plane *plane)
 187 {
 188         struct drm_plane_state *state = plane->state;
 189         struct drm_framebuffer *fb = state->fb;
 190         struct drm_gem_cma_object *gem;
 191         u32 lo_paddr, hi_paddr;
 192         dma_addr_t paddr;
 193         int bpp;
 194
 195         /* Get the physical address of the buffer in memory */
 196         gem = drm_fb_cma_get_gem_obj(fb, 0);
 197
 198         DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
 199
 200         /* Compute the start of the displayed memory */
 201         bpp = drm_format_plane_cpp(fb->pixel_format, 0);
 202         paddr = gem->paddr + fb->offsets[0];
 203         paddr += (state->src_x >> 16) * bpp;
 204         paddr += (state->src_y >> 16) * fb->pitches[0];
 205
 206         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 207
 208         /* Write the 32 lower bits of the address (in bits) */
 209         lo_paddr = paddr << 3;
 210         DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
 211         regmap_write(backend->regs, SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
 212                      lo_paddr);
 213
 214         /* And the upper bits */
 215         hi_paddr = paddr >> 29;
 216         DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
 217         regmap_update_bits(backend->regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
 218                            SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
 219                            SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
 220
 221         return 0;
 222 }
 223 EXPORT_SYMBOL(sun4i_backend_update_layer_buffer);
 224
 225 static int sun4i_backend_init_sat(struct device *dev) {
 226         struct sun4i_backend *backend = dev_get_drvdata(dev);
 227         int ret;
 228
 229         backend->sat_reset = devm_reset_control_get(dev, "sat");
 230         if (IS_ERR(backend->sat_reset)) {
 231                 dev_err(dev, "Couldn't get the SAT reset line\n");
 232                 return PTR_ERR(backend->sat_reset);
 233         }
 234
 235         ret = reset_control_deassert(backend->sat_reset);
 236         if (ret) {
 237                 dev_err(dev, "Couldn't deassert the SAT reset line\n");
 238                 return ret;
 239         }
 240
 241         backend->sat_clk = devm_clk_get(dev, "sat");
 242         if (IS_ERR(backend->sat_clk)) {
 243                 dev_err(dev, "Couldn't get our SAT clock\n");
 244                 ret = PTR_ERR(backend->sat_clk);
 245                 goto err_assert_reset;
 246         }
 247
 248         ret = clk_prepare_enable(backend->sat_clk);
 249         if (ret) {
 250                 dev_err(dev, "Couldn't enable the SAT clock\n");
 251                 return ret;
 252         }
 253
 254         return 0;
 255
 256 err_assert_reset:
 257         reset_control_assert(backend->sat_reset);
 258         return ret;
 259 }
 260
 261 static int sun4i_backend_free_sat(struct device *dev) {
 262         struct sun4i_backend *backend = dev_get_drvdata(dev);
 263
 264         clk_disable_unprepare(backend->sat_clk);
 265         reset_control_assert(backend->sat_reset);
 266
 267         return 0;
 268 }
 269
 270 static struct regmap_config sun4i_backend_regmap_config = {
 271         .reg_bits       = 32,
 272         .val_bits       = 32,
 273         .reg_stride     = 4,
 274         .max_register   = 0x5800,
 275 };
 276
 277 static int sun4i_backend_bind(struct device *dev, struct device *master,
 278                               void *data)
 279 {
 280         struct platform_device *pdev = to_platform_device(dev);
 281         struct drm_device *drm = data;
 282         struct sun4i_drv *drv = drm->dev_private;
 283         struct sun4i_backend *backend;
 284         struct resource *res;
 285         void __iomem *regs;
 286         int i, ret;
 287
 288         backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
 289         if (!backend)
 290                 return -ENOMEM;
 291         dev_set_drvdata(dev, backend);
 292         drv->backend = backend;
 293
 294         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 295         regs = devm_ioremap_resource(dev, res);
 296         if (IS_ERR(regs))
 297                 return PTR_ERR(regs);
 298
 299         backend->regs = devm_regmap_init_mmio(dev, regs,
 300                                               &sun4i_backend_regmap_config);
 301         if (IS_ERR(backend->regs)) {
 302                 dev_err(dev, "Couldn't create the backend0 regmap\n");
 303                 return PTR_ERR(backend->regs);
 304         }
 305
 306         backend->reset = devm_reset_control_get(dev, NULL);
 307         if (IS_ERR(backend->reset)) {
 308                 dev_err(dev, "Couldn't get our reset line\n");
 309                 return PTR_ERR(backend->reset);
 310         }
 311
 312         ret = reset_control_deassert(backend->reset);
 313         if (ret) {
 314                 dev_err(dev, "Couldn't deassert our reset line\n");
 315                 return ret;
 316         }
 317
 318         backend->bus_clk = devm_clk_get(dev, "ahb");
 319         if (IS_ERR(backend->bus_clk)) {
 320                 dev_err(dev, "Couldn't get the backend bus clock\n");
 321                 ret = PTR_ERR(backend->bus_clk);
 322                 goto err_assert_reset;
 323         }
 324         clk_prepare_enable(backend->bus_clk);
 325
 326         backend->mod_clk = devm_clk_get(dev, "mod");
 327         if (IS_ERR(backend->mod_clk)) {
 328                 dev_err(dev, "Couldn't get the backend module clock\n");
 329                 ret = PTR_ERR(backend->mod_clk);
 330                 goto err_disable_bus_clk;
 331         }
 332         clk_prepare_enable(backend->mod_clk);
 333
 334         backend->ram_clk = devm_clk_get(dev, "ram");
 335         if (IS_ERR(backend->ram_clk)) {
 336                 dev_err(dev, "Couldn't get the backend RAM clock\n");
 337                 ret = PTR_ERR(backend->ram_clk);
 338                 goto err_disable_mod_clk;
 339         }
 340         clk_prepare_enable(backend->ram_clk);
 341
 342         if (of_device_is_compatible(dev->of_node,
 343                                     "allwinner,sun8i-a33-display-backend")) {
 344                 ret = sun4i_backend_init_sat(dev);
 345                 if (ret) {
 346                         dev_err(dev, "Couldn't init SAT resources\n");
 347                         goto err_disable_ram_clk;
 348                 }
 349         }
 350
 351         /* Reset the registers */
 352         for (i = 0x800; i < 0x1000; i += 4)
 353                 regmap_write(backend->regs, i, 0);
 354
 355         /* Disable registers autoloading */
 356         regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 357                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
 358
 359         /* Enable the backend */
 360         regmap_write(backend->regs, SUN4I_BACKEND_MODCTL_REG,
 361                      SUN4I_BACKEND_MODCTL_DEBE_EN |
 362                      SUN4I_BACKEND_MODCTL_START_CTL);
 363
 364         return 0;
 365
 366 err_disable_ram_clk:
 367         clk_disable_unprepare(backend->ram_clk);
 368 err_disable_mod_clk:
 369         clk_disable_unprepare(backend->mod_clk);
 370 err_disable_bus_clk:
 371         clk_disable_unprepare(backend->bus_clk);
 372 err_assert_reset:
 373         reset_control_assert(backend->reset);
 374         return ret;
 375 }
 376
 377 static void sun4i_backend_unbind(struct device *dev, struct device *master,
 378                                  void *data)
 379 {
 380         struct sun4i_backend *backend = dev_get_drvdata(dev);
 381
 382         if (of_device_is_compatible(dev->of_node,
 383                                     "allwinner,sun8i-a33-display-backend"))
 384                 sun4i_backend_free_sat(dev);
 385
 386         clk_disable_unprepare(backend->ram_clk);
 387         clk_disable_unprepare(backend->mod_clk);
 388         clk_disable_unprepare(backend->bus_clk);
 389         reset_control_assert(backend->reset);
 390 }
 391
 392 static struct component_ops sun4i_backend_ops = {
 393         .bind   = sun4i_backend_bind,
 394         .unbind = sun4i_backend_unbind,
 395 };
 396
 397 static int sun4i_backend_probe(struct platform_device *pdev)
 398 {
 399         return component_add(&pdev->dev, &sun4i_backend_ops);
 400 }
 401
 402 static int sun4i_backend_remove(struct platform_device *pdev)
 403 {
 404         component_del(&pdev->dev, &sun4i_backend_ops);
 405
 406         return 0;
 407 }
 408
 409 static const struct of_device_id sun4i_backend_of_table[] = {
 410         { .compatible = "allwinner,sun5i-a13-display-backend" },
 411         { .compatible = "allwinner,sun8i-a33-display-backend" },
 412         { }
 413 };
 414 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
 415
 416 static struct platform_driver sun4i_backend_platform_driver = {
 417         .probe          = sun4i_backend_probe,
 418         .remove         = sun4i_backend_remove,
 419         .driver         = {
 420                 .name           = "sun4i-backend",
 421                 .of_match_table = sun4i_backend_of_table,
 422         },
 423 };
 424 module_platform_driver(sun4i_backend_platform_driver);
 425
 426 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 427 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
 428 MODULE_LICENSE("GPL");