drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

   1 /*
   2  * Copyright (C) 2016 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 #include <drm/drmP.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_edid.h>
  16 #include <drm/drm_encoder.h>
  17 #include <drm/drm_of.h>
  18 #include <drm/drm_panel.h>
  19
  20 #include <linux/clk.h>
  21 #include <linux/component.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include "sun4i_backend.h"
  27 #include "sun4i_crtc.h"
  28 #include "sun4i_drv.h"
  29 #include "sun4i_hdmi.h"
  30 #include "sun4i_tcon.h"
  31
  32 static inline struct sun4i_hdmi *
  33 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
  34 {
  35         return container_of(encoder, struct sun4i_hdmi,
  36                             encoder);
  37 }
  38
  39 static inline struct sun4i_hdmi *
  40 drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
  41 {
  42         return container_of(connector, struct sun4i_hdmi,
  43                             connector);
  44 }
  45
  46 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
  47                                            struct drm_display_mode *mode)
  48 {
  49         struct hdmi_avi_infoframe frame;
  50         u8 buffer[17];
  51         int i, ret;
  52
  53         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
  54         if (ret < 0) {
  55                 DRM_ERROR("Failed to get infoframes from mode\n");
  56                 return ret;
  57         }
  58
  59         ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  60         if (ret < 0) {
  61                 DRM_ERROR("Failed to pack infoframes\n");
  62                 return ret;
  63         }
  64
  65         for (i = 0; i < sizeof(buffer); i++)
  66                 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
  67
  68         return 0;
  69 }
  70
  71 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
  72                                    struct drm_crtc_state *crtc_state,
  73                                    struct drm_connector_state *conn_state)
  74 {
  75         struct drm_display_mode *mode = &crtc_state->mode;
  76
  77         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  78                 return -EINVAL;
  79
  80         return 0;
  81 }
  82
  83 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
  84 {
  85         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
  86         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
  87         struct sun4i_tcon *tcon = crtc->tcon;
  88         u32 val;
  89
  90         DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
  91
  92         val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
  93         val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
  94         writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
  95
  96         sun4i_tcon_channel_disable(tcon, 1);
  97 }
  98
  99 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
 100 {
 101         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 102         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
 103         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
 104         struct sun4i_tcon *tcon = crtc->tcon;
 105         u32 val = 0;
 106
 107         DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
 108
 109         sun4i_tcon_channel_enable(tcon, 1);
 110
 111         sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
 112         val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
 113         val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
 114         writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
 115
 116         val = SUN4I_HDMI_VID_CTRL_ENABLE;
 117         if (hdmi->hdmi_monitor)
 118                 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
 119
 120         writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
 121 }
 122
 123 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
 124                                 struct drm_display_mode *mode,
 125                                 struct drm_display_mode *adjusted_mode)
 126 {
 127         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
 128         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
 129         struct sun4i_tcon *tcon = crtc->tcon;
 130         unsigned int x, y;
 131         u32 val;
 132
 133         sun4i_tcon1_mode_set(tcon, mode);
 134         sun4i_tcon_set_mux(tcon, 1, encoder);
 135
 136         clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 137         clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
 138         clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
 139
 140         /* Set input sync enable */
 141         writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
 142                hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
 143
 144         /* Setup timing registers */
 145         writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
 146                SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
 147                hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
 148
 149         x = mode->htotal - mode->hsync_start;
 150         y = mode->vtotal - mode->vsync_start;
 151         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 152                hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
 153
 154         x = mode->hsync_start - mode->hdisplay;
 155         y = mode->vsync_start - mode->vdisplay;
 156         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 157                hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
 158
 159         x = mode->hsync_end - mode->hsync_start;
 160         y = mode->vsync_end - mode->vsync_start;
 161         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 162                hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
 163
 164         val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
 165         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 166                 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
 167
 168         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 169                 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
 170
 171         writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
 172 }
 173
 174 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
 175         .atomic_check   = sun4i_hdmi_atomic_check,
 176         .disable        = sun4i_hdmi_disable,
 177         .enable         = sun4i_hdmi_enable,
 178         .mode_set       = sun4i_hdmi_mode_set,
 179 };
 180
 181 static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
 182         .destroy        = drm_encoder_cleanup,
 183 };
 184
 185 static int sun4i_hdmi_get_modes(struct drm_connector *connector)
 186 {
 187         struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
 188         struct edid *edid;
 189         int ret;
 190
 191         edid = drm_get_edid(connector, hdmi->i2c);
 192         if (!edid)
 193                 return 0;
 194
 195         hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 196         DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
 197                          hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
 198
 199         drm_mode_connector_update_edid_property(connector, edid);
 200         cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
 201         ret = drm_add_edid_modes(connector, edid);
 202         kfree(edid);
 203
 204         return ret;
 205 }
 206
 207 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
 208         .get_modes      = sun4i_hdmi_get_modes,
 209 };
 210
 211 static enum drm_connector_status
 212 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
 213 {
 214         struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
 215         unsigned long reg;
 216
 217         reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG);
 218         if (!(reg & SUN4I_HDMI_HPD_HIGH)) {
 219                 cec_phys_addr_invalidate(hdmi->cec_adap);
 220                 return connector_status_disconnected;
 221         }
 222
 223         return connector_status_connected;
 224 }
 225
 226 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
 227         .detect                 = sun4i_hdmi_connector_detect,
 228         .fill_modes             = drm_helper_probe_single_connector_modes,
 229         .destroy                = drm_connector_cleanup,
 230         .reset                  = drm_atomic_helper_connector_reset,
 231         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 232         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 233 };
 234
 235 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
 236 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
 237 {
 238         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 239
 240         return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
 241 }
 242
 243 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
 244 {
 245         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 246
 247         /* Start driving the CEC pin low */
 248         writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
 249 }
 250
 251 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
 252 {
 253         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 254
 255         /*
 256          * Stop driving the CEC pin, the pull up will take over
 257          * unless another CEC device is driving the pin low.
 258          */
 259         writel(0, hdmi->base + SUN4I_HDMI_CEC);
 260 }
 261
 262 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
 263         .read = sun4i_hdmi_cec_pin_read,
 264         .low = sun4i_hdmi_cec_pin_low,
 265         .high = sun4i_hdmi_cec_pin_high,
 266 };
 267 #endif
 268
 269 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
 270                            void *data)
 271 {
 272         struct platform_device *pdev = to_platform_device(dev);
 273         struct drm_device *drm = data;
 274         struct sun4i_drv *drv = drm->dev_private;
 275         struct sun4i_hdmi *hdmi;
 276         struct resource *res;
 277         u32 reg;
 278         int ret;
 279
 280         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 281         if (!hdmi)
 282                 return -ENOMEM;
 283         dev_set_drvdata(dev, hdmi);
 284         hdmi->dev = dev;
 285         hdmi->drv = drv;
 286
 287         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 288         hdmi->base = devm_ioremap_resource(dev, res);
 289         if (IS_ERR(hdmi->base)) {
 290                 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
 291                 return PTR_ERR(hdmi->base);
 292         }
 293
 294         hdmi->bus_clk = devm_clk_get(dev, "ahb");
 295         if (IS_ERR(hdmi->bus_clk)) {
 296                 dev_err(dev, "Couldn't get the HDMI bus clock\n");
 297                 return PTR_ERR(hdmi->bus_clk);
 298         }
 299         clk_prepare_enable(hdmi->bus_clk);
 300
 301         hdmi->mod_clk = devm_clk_get(dev, "mod");
 302         if (IS_ERR(hdmi->mod_clk)) {
 303                 dev_err(dev, "Couldn't get the HDMI mod clock\n");
 304                 ret = PTR_ERR(hdmi->mod_clk);
 305                 goto err_disable_bus_clk;
 306         }
 307         clk_prepare_enable(hdmi->mod_clk);
 308
 309         hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
 310         if (IS_ERR(hdmi->pll0_clk)) {
 311                 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
 312                 ret = PTR_ERR(hdmi->pll0_clk);
 313                 goto err_disable_mod_clk;
 314         }
 315
 316         hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
 317         if (IS_ERR(hdmi->pll1_clk)) {
 318                 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
 319                 ret = PTR_ERR(hdmi->pll1_clk);
 320                 goto err_disable_mod_clk;
 321         }
 322
 323         ret = sun4i_tmds_create(hdmi);
 324         if (ret) {
 325                 dev_err(dev, "Couldn't create the TMDS clock\n");
 326                 goto err_disable_mod_clk;
 327         }
 328
 329         writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
 330
 331         writel(SUN4I_HDMI_PAD_CTRL0_TXEN | SUN4I_HDMI_PAD_CTRL0_CKEN |
 332                SUN4I_HDMI_PAD_CTRL0_PWENG | SUN4I_HDMI_PAD_CTRL0_PWEND |
 333                SUN4I_HDMI_PAD_CTRL0_PWENC | SUN4I_HDMI_PAD_CTRL0_LDODEN |
 334                SUN4I_HDMI_PAD_CTRL0_LDOCEN | SUN4I_HDMI_PAD_CTRL0_BIASEN,
 335                hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
 336
 337         /*
 338          * We can't just initialize the register there, we need to
 339          * protect the clock bits that have already been read out and
 340          * cached by the clock framework.
 341          */
 342         reg = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
 343         reg &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
 344         reg |= SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
 345                 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
 346                 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
 347                 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
 348                 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
 349                 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
 350                 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
 351                 SUN4I_HDMI_PAD_CTRL1_AMP_OPT;
 352         writel(reg, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
 353
 354         reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 355         reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
 356         reg |= SUN4I_HDMI_PLL_CTRL_VCO_S(8) | SUN4I_HDMI_PLL_CTRL_CS(7) |
 357                 SUN4I_HDMI_PLL_CTRL_CP_S(15) | SUN4I_HDMI_PLL_CTRL_S(7) |
 358                 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | SUN4I_HDMI_PLL_CTRL_SDIV2 |
 359                 SUN4I_HDMI_PLL_CTRL_LDO2_EN | SUN4I_HDMI_PLL_CTRL_LDO1_EN |
 360                 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | SUN4I_HDMI_PLL_CTRL_BWS |
 361                 SUN4I_HDMI_PLL_CTRL_PLL_EN;
 362         writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 363
 364         ret = sun4i_hdmi_i2c_create(dev, hdmi);
 365         if (ret) {
 366                 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
 367                 goto err_disable_mod_clk;
 368         }
 369
 370         drm_encoder_helper_add(&hdmi->encoder,
 371                                &sun4i_hdmi_helper_funcs);
 372         ret = drm_encoder_init(drm,
 373                                &hdmi->encoder,
 374                                &sun4i_hdmi_funcs,
 375                                DRM_MODE_ENCODER_TMDS,
 376                                NULL);
 377         if (ret) {
 378                 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
 379                 goto err_del_i2c_adapter;
 380         }
 381
 382         hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
 383                                                                   dev->of_node);
 384         if (!hdmi->encoder.possible_crtcs) {
 385                 ret = -EPROBE_DEFER;
 386                 goto err_del_i2c_adapter;
 387         }
 388
 389 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
 390         hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
 391                 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
 392                 CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
 393         ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
 394         if (ret < 0)
 395                 goto err_cleanup_connector;
 396         writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
 397                hdmi->base + SUN4I_HDMI_CEC);
 398 #endif
 399
 400         drm_connector_helper_add(&hdmi->connector,
 401                                  &sun4i_hdmi_connector_helper_funcs);
 402         ret = drm_connector_init(drm, &hdmi->connector,
 403                                  &sun4i_hdmi_connector_funcs,
 404                                  DRM_MODE_CONNECTOR_HDMIA);
 405         if (ret) {
 406                 dev_err(dev,
 407                         "Couldn't initialise the HDMI connector\n");
 408                 goto err_cleanup_connector;
 409         }
 410
 411         /* There is no HPD interrupt, so we need to poll the controller */
 412         hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
 413                 DRM_CONNECTOR_POLL_DISCONNECT;
 414
 415         ret = cec_register_adapter(hdmi->cec_adap, dev);
 416         if (ret < 0)
 417                 goto err_cleanup_connector;
 418         drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
 419
 420         return 0;
 421
 422 err_cleanup_connector:
 423         cec_delete_adapter(hdmi->cec_adap);
 424         drm_encoder_cleanup(&hdmi->encoder);
 425 err_del_i2c_adapter:
 426         i2c_del_adapter(hdmi->i2c);
 427 err_disable_mod_clk:
 428         clk_disable_unprepare(hdmi->mod_clk);
 429 err_disable_bus_clk:
 430         clk_disable_unprepare(hdmi->bus_clk);
 431         return ret;
 432 }
 433
 434 static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
 435                             void *data)
 436 {
 437         struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
 438
 439         cec_unregister_adapter(hdmi->cec_adap);
 440         i2c_del_adapter(hdmi->i2c);
 441         clk_disable_unprepare(hdmi->mod_clk);
 442         clk_disable_unprepare(hdmi->bus_clk);
 443 }
 444
 445 static const struct component_ops sun4i_hdmi_ops = {
 446         .bind   = sun4i_hdmi_bind,
 447         .unbind = sun4i_hdmi_unbind,
 448 };
 449
 450 static int sun4i_hdmi_probe(struct platform_device *pdev)
 451 {
 452         return component_add(&pdev->dev, &sun4i_hdmi_ops);
 453 }
 454
 455 static int sun4i_hdmi_remove(struct platform_device *pdev)
 456 {
 457         component_del(&pdev->dev, &sun4i_hdmi_ops);
 458
 459         return 0;
 460 }
 461
 462 static const struct of_device_id sun4i_hdmi_of_table[] = {
 463         { .compatible = "allwinner,sun5i-a10s-hdmi" },
 464         { }
 465 };
 466 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
 467
 468 static struct platform_driver sun4i_hdmi_driver = {
 469         .probe          = sun4i_hdmi_probe,
 470         .remove         = sun4i_hdmi_remove,
 471         .driver         = {
 472                 .name           = "sun4i-hdmi",
 473                 .of_match_table = sun4i_hdmi_of_table,
 474         },
 475 };
 476 module_platform_driver(sun4i_hdmi_driver);
 477
 478 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 479 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
 480 MODULE_LICENSE("GPL");