drivers/gpu/drm/sun4i/sun8i_mixer.c

   1 /*
   2  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   3  *
   4  * Based on sun4i_backend.c, which is:
   5  *   Copyright (C) 2015 Free Electrons
   6  *   Copyright (C) 2015 NextThing Co
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <drm/drm_fb_cma_helper.h>
  19 #include <drm/drm_gem_cma_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/component.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_graph.h>
  26 #include <linux/reset.h>
  27
  28 #include "sun4i_drv.h"
  29 #include "sun8i_mixer.h"
  30 #include "sun8i_ui_layer.h"
  31 #include "sun8i_vi_layer.h"
  32 #include "sunxi_engine.h"
  33
  34 static const struct de2_fmt_info de2_formats[] = {
  35         {
  36                 .drm_fmt = DRM_FORMAT_ARGB8888,
  37                 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888,
  38                 .rgb = true,
  39                 .csc = SUN8I_CSC_MODE_OFF,
  40         },
  41         {
  42                 .drm_fmt = DRM_FORMAT_ABGR8888,
  43                 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888,
  44                 .rgb = true,
  45                 .csc = SUN8I_CSC_MODE_OFF,
  46         },
  47         {
  48                 .drm_fmt = DRM_FORMAT_RGBA8888,
  49                 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888,
  50                 .rgb = true,
  51                 .csc = SUN8I_CSC_MODE_OFF,
  52         },
  53         {
  54                 .drm_fmt = DRM_FORMAT_BGRA8888,
  55                 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888,
  56                 .rgb = true,
  57                 .csc = SUN8I_CSC_MODE_OFF,
  58         },
  59         {
  60                 .drm_fmt = DRM_FORMAT_XRGB8888,
  61                 .de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888,
  62                 .rgb = true,
  63                 .csc = SUN8I_CSC_MODE_OFF,
  64         },
  65         {
  66                 .drm_fmt = DRM_FORMAT_XBGR8888,
  67                 .de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888,
  68                 .rgb = true,
  69                 .csc = SUN8I_CSC_MODE_OFF,
  70         },
  71         {
  72                 .drm_fmt = DRM_FORMAT_RGBX8888,
  73                 .de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888,
  74                 .rgb = true,
  75                 .csc = SUN8I_CSC_MODE_OFF,
  76         },
  77         {
  78                 .drm_fmt = DRM_FORMAT_BGRX8888,
  79                 .de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888,
  80                 .rgb = true,
  81                 .csc = SUN8I_CSC_MODE_OFF,
  82         },
  83         {
  84                 .drm_fmt = DRM_FORMAT_RGB888,
  85                 .de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
  86                 .rgb = true,
  87                 .csc = SUN8I_CSC_MODE_OFF,
  88         },
  89         {
  90                 .drm_fmt = DRM_FORMAT_BGR888,
  91                 .de2_fmt = SUN8I_MIXER_FBFMT_BGR888,
  92                 .rgb = true,
  93                 .csc = SUN8I_CSC_MODE_OFF,
  94         },
  95         {
  96                 .drm_fmt = DRM_FORMAT_RGB565,
  97                 .de2_fmt = SUN8I_MIXER_FBFMT_RGB565,
  98                 .rgb = true,
  99                 .csc = SUN8I_CSC_MODE_OFF,
 100         },
 101         {
 102                 .drm_fmt = DRM_FORMAT_BGR565,
 103                 .de2_fmt = SUN8I_MIXER_FBFMT_BGR565,
 104                 .rgb = true,
 105                 .csc = SUN8I_CSC_MODE_OFF,
 106         },
 107         {
 108                 .drm_fmt = DRM_FORMAT_ARGB4444,
 109                 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
 110                 .rgb = true,
 111                 .csc = SUN8I_CSC_MODE_OFF,
 112         },
 113         {
 114                 /* for DE2 VI layer which ignores alpha */
 115                 .drm_fmt = DRM_FORMAT_XRGB4444,
 116                 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
 117                 .rgb = true,
 118                 .csc = SUN8I_CSC_MODE_OFF,
 119         },
 120         {
 121                 .drm_fmt = DRM_FORMAT_ABGR4444,
 122                 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
 123                 .rgb = true,
 124                 .csc = SUN8I_CSC_MODE_OFF,
 125         },
 126         {
 127                 /* for DE2 VI layer which ignores alpha */
 128                 .drm_fmt = DRM_FORMAT_XBGR4444,
 129                 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
 130                 .rgb = true,
 131                 .csc = SUN8I_CSC_MODE_OFF,
 132         },
 133         {
 134                 .drm_fmt = DRM_FORMAT_RGBA4444,
 135                 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
 136                 .rgb = true,
 137                 .csc = SUN8I_CSC_MODE_OFF,
 138         },
 139         {
 140                 /* for DE2 VI layer which ignores alpha */
 141                 .drm_fmt = DRM_FORMAT_RGBX4444,
 142                 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
 143                 .rgb = true,
 144                 .csc = SUN8I_CSC_MODE_OFF,
 145         },
 146         {
 147                 .drm_fmt = DRM_FORMAT_BGRA4444,
 148                 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
 149                 .rgb = true,
 150                 .csc = SUN8I_CSC_MODE_OFF,
 151         },
 152         {
 153                 /* for DE2 VI layer which ignores alpha */
 154                 .drm_fmt = DRM_FORMAT_BGRX4444,
 155                 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
 156                 .rgb = true,
 157                 .csc = SUN8I_CSC_MODE_OFF,
 158         },
 159         {
 160                 .drm_fmt = DRM_FORMAT_ARGB1555,
 161                 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
 162                 .rgb = true,
 163                 .csc = SUN8I_CSC_MODE_OFF,
 164         },
 165         {
 166                 /* for DE2 VI layer which ignores alpha */
 167                 .drm_fmt = DRM_FORMAT_XRGB1555,
 168                 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
 169                 .rgb = true,
 170                 .csc = SUN8I_CSC_MODE_OFF,
 171         },
 172         {
 173                 .drm_fmt = DRM_FORMAT_ABGR1555,
 174                 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
 175                 .rgb = true,
 176                 .csc = SUN8I_CSC_MODE_OFF,
 177         },
 178         {
 179                 /* for DE2 VI layer which ignores alpha */
 180                 .drm_fmt = DRM_FORMAT_XBGR1555,
 181                 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
 182                 .rgb = true,
 183                 .csc = SUN8I_CSC_MODE_OFF,
 184         },
 185         {
 186                 .drm_fmt = DRM_FORMAT_RGBA5551,
 187                 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
 188                 .rgb = true,
 189                 .csc = SUN8I_CSC_MODE_OFF,
 190         },
 191         {
 192                 /* for DE2 VI layer which ignores alpha */
 193                 .drm_fmt = DRM_FORMAT_RGBX5551,
 194                 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
 195                 .rgb = true,
 196                 .csc = SUN8I_CSC_MODE_OFF,
 197         },
 198         {
 199                 .drm_fmt = DRM_FORMAT_BGRA5551,
 200                 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
 201                 .rgb = true,
 202                 .csc = SUN8I_CSC_MODE_OFF,
 203         },
 204         {
 205                 /* for DE2 VI layer which ignores alpha */
 206                 .drm_fmt = DRM_FORMAT_BGRX5551,
 207                 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
 208                 .rgb = true,
 209                 .csc = SUN8I_CSC_MODE_OFF,
 210         },
 211         {
 212                 .drm_fmt = DRM_FORMAT_UYVY,
 213                 .de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
 214                 .rgb = false,
 215                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 216         },
 217         {
 218                 .drm_fmt = DRM_FORMAT_VYUY,
 219                 .de2_fmt = SUN8I_MIXER_FBFMT_VYUY,
 220                 .rgb = false,
 221                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 222         },
 223         {
 224                 .drm_fmt = DRM_FORMAT_YUYV,
 225                 .de2_fmt = SUN8I_MIXER_FBFMT_YUYV,
 226                 .rgb = false,
 227                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 228         },
 229         {
 230                 .drm_fmt = DRM_FORMAT_YVYU,
 231                 .de2_fmt = SUN8I_MIXER_FBFMT_YVYU,
 232                 .rgb = false,
 233                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 234         },
 235         {
 236                 .drm_fmt = DRM_FORMAT_NV16,
 237                 .de2_fmt = SUN8I_MIXER_FBFMT_NV16,
 238                 .rgb = false,
 239                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 240         },
 241         {
 242                 .drm_fmt = DRM_FORMAT_NV61,
 243                 .de2_fmt = SUN8I_MIXER_FBFMT_NV61,
 244                 .rgb = false,
 245                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 246         },
 247         {
 248                 .drm_fmt = DRM_FORMAT_NV12,
 249                 .de2_fmt = SUN8I_MIXER_FBFMT_NV12,
 250                 .rgb = false,
 251                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 252         },
 253         {
 254                 .drm_fmt = DRM_FORMAT_NV21,
 255                 .de2_fmt = SUN8I_MIXER_FBFMT_NV21,
 256                 .rgb = false,
 257                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 258         },
 259         {
 260                 .drm_fmt = DRM_FORMAT_YUV422,
 261                 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
 262                 .rgb = false,
 263                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 264         },
 265         {
 266                 .drm_fmt = DRM_FORMAT_YUV420,
 267                 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
 268                 .rgb = false,
 269                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 270         },
 271         {
 272                 .drm_fmt = DRM_FORMAT_YUV411,
 273                 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
 274                 .rgb = false,
 275                 .csc = SUN8I_CSC_MODE_YUV2RGB,
 276         },
 277         {
 278                 .drm_fmt = DRM_FORMAT_YVU422,
 279                 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
 280                 .rgb = false,
 281                 .csc = SUN8I_CSC_MODE_YVU2RGB,
 282         },
 283         {
 284                 .drm_fmt = DRM_FORMAT_YVU420,
 285                 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
 286                 .rgb = false,
 287                 .csc = SUN8I_CSC_MODE_YVU2RGB,
 288         },
 289         {
 290                 .drm_fmt = DRM_FORMAT_YVU411,
 291                 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
 292                 .rgb = false,
 293                 .csc = SUN8I_CSC_MODE_YVU2RGB,
 294         },
 295 };
 296
 297 const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)
 298 {
 299         unsigned int i;
 300
 301         for (i = 0; i < ARRAY_SIZE(de2_formats); ++i)
 302                 if (de2_formats[i].drm_fmt == format)
 303                         return &de2_formats[i];
 304
 305         return NULL;
 306 }
 307
 308 static void sun8i_mixer_commit(struct sunxi_engine *engine)
 309 {
 310         DRM_DEBUG_DRIVER("Committing changes\n");
 311
 312         regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
 313                      SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
 314 }
 315
 316 static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
 317                                             struct sunxi_engine *engine)
 318 {
 319         struct drm_plane **planes;
 320         struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
 321         int i;
 322
 323         planes = devm_kcalloc(drm->dev,
 324                               mixer->cfg->vi_num + mixer->cfg->ui_num + 1,
 325                               sizeof(*planes), GFP_KERNEL);
 326         if (!planes)
 327                 return ERR_PTR(-ENOMEM);
 328
 329         for (i = 0; i < mixer->cfg->vi_num; i++) {
 330                 struct sun8i_vi_layer *layer;
 331
 332                 layer = sun8i_vi_layer_init_one(drm, mixer, i);
 333                 if (IS_ERR(layer)) {
 334                         dev_err(drm->dev,
 335                                 "Couldn't initialize overlay plane\n");
 336                         return ERR_CAST(layer);
 337                 };
 338
 339                 planes[i] = &layer->plane;
 340         };
 341
 342         for (i = 0; i < mixer->cfg->ui_num; i++) {
 343                 struct sun8i_ui_layer *layer;
 344
 345                 layer = sun8i_ui_layer_init_one(drm, mixer, i);
 346                 if (IS_ERR(layer)) {
 347                         dev_err(drm->dev, "Couldn't initialize %s plane\n",
 348                                 i ? "overlay" : "primary");
 349                         return ERR_CAST(layer);
 350                 };
 351
 352                 planes[mixer->cfg->vi_num + i] = &layer->plane;
 353         };
 354
 355         return planes;
 356 }
 357
 358 static const struct sunxi_engine_ops sun8i_engine_ops = {
 359         .commit         = sun8i_mixer_commit,
 360         .layers_init    = sun8i_layers_init,
 361 };
 362
 363 static struct regmap_config sun8i_mixer_regmap_config = {
 364         .reg_bits       = 32,
 365         .val_bits       = 32,
 366         .reg_stride     = 4,
 367         .max_register   = 0xffffc, /* guessed */
 368 };
 369
 370 static int sun8i_mixer_of_get_id(struct device_node *node)
 371 {
 372         struct device_node *port, *ep;
 373         int ret = -EINVAL;
 374
 375         /* output is port 1 */
 376         port = of_graph_get_port_by_id(node, 1);
 377         if (!port)
 378                 return -EINVAL;
 379
 380         /* try to find downstream endpoint */
 381         for_each_available_child_of_node(port, ep) {
 382                 struct device_node *remote;
 383                 u32 reg;
 384
 385                 remote = of_graph_get_remote_endpoint(ep);
 386                 if (!remote)
 387                         continue;
 388
 389                 ret = of_property_read_u32(remote, "reg", &reg);
 390                 if (!ret) {
 391                         of_node_put(remote);
 392                         of_node_put(ep);
 393                         of_node_put(port);
 394
 395                         return reg;
 396                 }
 397
 398                 of_node_put(remote);
 399         }
 400
 401         of_node_put(port);
 402
 403         return ret;
 404 }
 405
 406 static int sun8i_mixer_bind(struct device *dev, struct device *master,
 407                               void *data)
 408 {
 409         struct platform_device *pdev = to_platform_device(dev);
 410         struct drm_device *drm = data;
 411         struct sun4i_drv *drv = drm->dev_private;
 412         struct sun8i_mixer *mixer;
 413         struct resource *res;
 414         void __iomem *regs;
 415         int plane_cnt;
 416         int i, ret;
 417
 418         /*
 419          * The mixer uses single 32-bit register to store memory
 420          * addresses, so that it cannot deal with 64-bit memory
 421          * addresses.
 422          * Restrict the DMA mask so that the mixer won't be
 423          * allocated some memory that is too high.
 424          */
 425         ret = dma_set_mask(dev, DMA_BIT_MASK(32));
 426         if (ret) {
 427                 dev_err(dev, "Cannot do 32-bit DMA.\n");
 428                 return ret;
 429         }
 430
 431         mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
 432         if (!mixer)
 433                 return -ENOMEM;
 434         dev_set_drvdata(dev, mixer);
 435         mixer->engine.ops = &sun8i_engine_ops;
 436         mixer->engine.node = dev->of_node;
 437
 438         /*
 439          * While this function can fail, we shouldn't do anything
 440          * if this happens. Some early DE2 DT entries don't provide
 441          * mixer id but work nevertheless because matching between
 442          * TCON and mixer is done by comparing node pointers (old
 443          * way) instead comparing ids. If this function fails and
 444          * id is needed, it will fail during id matching anyway.
 445          */
 446         mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
 447
 448         mixer->cfg = of_device_get_match_data(dev);
 449         if (!mixer->cfg)
 450                 return -EINVAL;
 451
 452         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 453         regs = devm_ioremap_resource(dev, res);
 454         if (IS_ERR(regs))
 455                 return PTR_ERR(regs);
 456
 457         mixer->engine.regs = devm_regmap_init_mmio(dev, regs,
 458                                                    &sun8i_mixer_regmap_config);
 459         if (IS_ERR(mixer->engine.regs)) {
 460                 dev_err(dev, "Couldn't create the mixer regmap\n");
 461                 return PTR_ERR(mixer->engine.regs);
 462         }
 463
 464         mixer->reset = devm_reset_control_get(dev, NULL);
 465         if (IS_ERR(mixer->reset)) {
 466                 dev_err(dev, "Couldn't get our reset line\n");
 467                 return PTR_ERR(mixer->reset);
 468         }
 469
 470         ret = reset_control_deassert(mixer->reset);
 471         if (ret) {
 472                 dev_err(dev, "Couldn't deassert our reset line\n");
 473                 return ret;
 474         }
 475
 476         mixer->bus_clk = devm_clk_get(dev, "bus");
 477         if (IS_ERR(mixer->bus_clk)) {
 478                 dev_err(dev, "Couldn't get the mixer bus clock\n");
 479                 ret = PTR_ERR(mixer->bus_clk);
 480                 goto err_assert_reset;
 481         }
 482         clk_prepare_enable(mixer->bus_clk);
 483
 484         mixer->mod_clk = devm_clk_get(dev, "mod");
 485         if (IS_ERR(mixer->mod_clk)) {
 486                 dev_err(dev, "Couldn't get the mixer module clock\n");
 487                 ret = PTR_ERR(mixer->mod_clk);
 488                 goto err_disable_bus_clk;
 489         }
 490
 491         /*
 492          * It seems that we need to enforce that rate for whatever
 493          * reason for the mixer to be functional. Make sure it's the
 494          * case.
 495          */
 496         if (mixer->cfg->mod_rate)
 497                 clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
 498
 499         clk_prepare_enable(mixer->mod_clk);
 500
 501         list_add_tail(&mixer->engine.list, &drv->engine_list);
 502
 503         /* Reset the registers */
 504         for (i = 0x0; i < 0x20000; i += 4)
 505                 regmap_write(mixer->engine.regs, i, 0);
 506
 507         /* Enable the mixer */
 508         regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
 509                      SUN8I_MIXER_GLOBAL_CTL_RT_EN);
 510
 511         /* Set background color to black */
 512         regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR,
 513                      SUN8I_MIXER_BLEND_COLOR_BLACK);
 514
 515         /*
 516          * Set fill color of bottom plane to black. Generally not needed
 517          * except when VI plane is at bottom (zpos = 0) and enabled.
 518          */
 519         regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL,
 520                      SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
 521         regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
 522                      SUN8I_MIXER_BLEND_COLOR_BLACK);
 523
 524         plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
 525         for (i = 0; i < plane_cnt; i++)
 526                 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(i),
 527                              SUN8I_MIXER_BLEND_MODE_DEF);
 528
 529         regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL,
 530                            SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
 531
 532         return 0;
 533
 534 err_disable_bus_clk:
 535         clk_disable_unprepare(mixer->bus_clk);
 536 err_assert_reset:
 537         reset_control_assert(mixer->reset);
 538         return ret;
 539 }
 540
 541 static void sun8i_mixer_unbind(struct device *dev, struct device *master,
 542                                  void *data)
 543 {
 544         struct sun8i_mixer *mixer = dev_get_drvdata(dev);
 545
 546         list_del(&mixer->engine.list);
 547
 548         clk_disable_unprepare(mixer->mod_clk);
 549         clk_disable_unprepare(mixer->bus_clk);
 550         reset_control_assert(mixer->reset);
 551 }
 552
 553 static const struct component_ops sun8i_mixer_ops = {
 554         .bind   = sun8i_mixer_bind,
 555         .unbind = sun8i_mixer_unbind,
 556 };
 557
 558 static int sun8i_mixer_probe(struct platform_device *pdev)
 559 {
 560         return component_add(&pdev->dev, &sun8i_mixer_ops);
 561 }
 562
 563 static int sun8i_mixer_remove(struct platform_device *pdev)
 564 {
 565         component_del(&pdev->dev, &sun8i_mixer_ops);
 566
 567         return 0;
 568 }
 569
 570 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
 571         .ccsc           = 0,
 572         .scaler_mask    = 0xf,
 573         .ui_num         = 3,
 574         .vi_num         = 1,
 575 };
 576
 577 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
 578         .ccsc           = 1,
 579         .scaler_mask    = 0x3,
 580         .ui_num         = 1,
 581         .vi_num         = 1,
 582 };
 583
 584 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
 585         .ccsc           = 0,
 586         .mod_rate       = 432000000,
 587         .scaler_mask    = 0xf,
 588         .ui_num         = 3,
 589         .vi_num         = 1,
 590 };
 591
 592 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
 593         .vi_num = 2,
 594         .ui_num = 1,
 595         .scaler_mask = 0x3,
 596         .ccsc = 0,
 597         .mod_rate = 150000000,
 598 };
 599
 600 static const struct of_device_id sun8i_mixer_of_table[] = {
 601         {
 602                 .compatible = "allwinner,sun8i-a83t-de2-mixer-0",
 603                 .data = &sun8i_a83t_mixer0_cfg,
 604         },
 605         {
 606                 .compatible = "allwinner,sun8i-a83t-de2-mixer-1",
 607                 .data = &sun8i_a83t_mixer1_cfg,
 608         },
 609         {
 610                 .compatible = "allwinner,sun8i-h3-de2-mixer-0",
 611                 .data = &sun8i_h3_mixer0_cfg,
 612         },
 613         {
 614                 .compatible = "allwinner,sun8i-v3s-de2-mixer",
 615                 .data = &sun8i_v3s_mixer_cfg,
 616         },
 617         { }
 618 };
 619 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
 620
 621 static struct platform_driver sun8i_mixer_platform_driver = {
 622         .probe          = sun8i_mixer_probe,
 623         .remove         = sun8i_mixer_remove,
 624         .driver         = {
 625                 .name           = "sun8i-mixer",
 626                 .of_match_table = sun8i_mixer_of_table,
 627         },
 628 };
 629 module_platform_driver(sun8i_mixer_platform_driver);
 630
 631 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
 632 MODULE_DESCRIPTION("Allwinner DE2 Mixer driver");
 633 MODULE_LICENSE("GPL");