drivers/gpu/drm/tegra/hub.c

   1 /*
   2  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/host1x.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_graph.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/reset.h>
  18
  19 #include <drm/drmP.h>
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_crtc_helper.h>
  23
  24 #include "drm.h"
  25 #include "dc.h"
  26 #include "plane.h"
  27
  28 static const u32 tegra_shared_plane_formats[] = {
  29         DRM_FORMAT_ARGB1555,
  30         DRM_FORMAT_RGB565,
  31         DRM_FORMAT_RGBA5551,
  32         DRM_FORMAT_ARGB8888,
  33         DRM_FORMAT_ABGR8888,
  34         /* new on Tegra114 */
  35         DRM_FORMAT_ABGR4444,
  36         DRM_FORMAT_ABGR1555,
  37         DRM_FORMAT_BGRA5551,
  38         DRM_FORMAT_XRGB1555,
  39         DRM_FORMAT_RGBX5551,
  40         DRM_FORMAT_XBGR1555,
  41         DRM_FORMAT_BGRX5551,
  42         DRM_FORMAT_BGR565,
  43         DRM_FORMAT_XRGB8888,
  44         DRM_FORMAT_XBGR8888,
  45         /* planar formats */
  46         DRM_FORMAT_UYVY,
  47         DRM_FORMAT_YUYV,
  48         DRM_FORMAT_YUV420,
  49         DRM_FORMAT_YUV422,
  50 };
  51
  52 static const u64 tegra_shared_plane_modifiers[] = {
  53         DRM_FORMAT_MOD_LINEAR,
  54         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
  55         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
  56         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
  57         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
  58         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
  59         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
  60         DRM_FORMAT_MOD_INVALID
  61 };
  62
  63 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
  64                                               unsigned int offset)
  65 {
  66         if (offset >= 0x500 && offset <= 0x581) {
  67                 offset = 0x000 + (offset - 0x500);
  68                 return plane->offset + offset;
  69         }
  70
  71         if (offset >= 0x700 && offset <= 0x73c) {
  72                 offset = 0x180 + (offset - 0x700);
  73                 return plane->offset + offset;
  74         }
  75
  76         if (offset >= 0x800 && offset <= 0x83e) {
  77                 offset = 0x1c0 + (offset - 0x800);
  78                 return plane->offset + offset;
  79         }
  80
  81         dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
  82
  83         return plane->offset + offset;
  84 }
  85
  86 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
  87                                     unsigned int offset)
  88 {
  89         return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
  90 }
  91
  92 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
  93                                       unsigned int offset)
  94 {
  95         tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
  96 }
  97
  98 static int tegra_windowgroup_enable(struct tegra_windowgroup *wgrp)
  99 {
 100         mutex_lock(&wgrp->lock);
 101
 102         if (wgrp->usecount == 0) {
 103                 pm_runtime_get_sync(wgrp->parent);
 104                 reset_control_deassert(wgrp->rst);
 105         }
 106
 107         wgrp->usecount++;
 108         mutex_unlock(&wgrp->lock);
 109
 110         return 0;
 111 }
 112
 113 static void tegra_windowgroup_disable(struct tegra_windowgroup *wgrp)
 114 {
 115         int err;
 116
 117         mutex_lock(&wgrp->lock);
 118
 119         if (wgrp->usecount == 1) {
 120                 err = reset_control_assert(wgrp->rst);
 121                 if (err < 0) {
 122                         pr_err("failed to assert reset for window group %u\n",
 123                                wgrp->index);
 124                 }
 125
 126                 pm_runtime_put(wgrp->parent);
 127         }
 128
 129         wgrp->usecount--;
 130         mutex_unlock(&wgrp->lock);
 131 }
 132
 133 int tegra_display_hub_prepare(struct tegra_display_hub *hub)
 134 {
 135         unsigned int i;
 136
 137         /*
 138          * XXX Enabling/disabling windowgroups needs to happen when the owner
 139          * display controller is disabled. There's currently no good point at
 140          * which this could be executed, so unconditionally enable all window
 141          * groups for now.
 142          */
 143         for (i = 0; i < hub->soc->num_wgrps; i++) {
 144                 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
 145
 146                 /* Skip orphaned window group whose parent DC is disabled */
 147                 if (wgrp->parent)
 148                         tegra_windowgroup_enable(wgrp);
 149         }
 150
 151         return 0;
 152 }
 153
 154 void tegra_display_hub_cleanup(struct tegra_display_hub *hub)
 155 {
 156         unsigned int i;
 157
 158         /*
 159          * XXX Remove this once window groups can be more fine-grainedly
 160          * enabled and disabled.
 161          */
 162         for (i = 0; i < hub->soc->num_wgrps; i++) {
 163                 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
 164
 165                 /* Skip orphaned window group whose parent DC is disabled */
 166                 if (wgrp->parent)
 167                         tegra_windowgroup_disable(wgrp);
 168         }
 169 }
 170
 171 static void tegra_shared_plane_update(struct tegra_plane *plane)
 172 {
 173         struct tegra_dc *dc = plane->dc;
 174         unsigned long timeout;
 175         u32 mask, value;
 176
 177         mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index;
 178         tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
 179
 180         timeout = jiffies + msecs_to_jiffies(1000);
 181
 182         while (time_before(jiffies, timeout)) {
 183                 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
 184                 if ((value & mask) == 0)
 185                         break;
 186
 187                 usleep_range(100, 400);
 188         }
 189 }
 190
 191 static void tegra_shared_plane_activate(struct tegra_plane *plane)
 192 {
 193         struct tegra_dc *dc = plane->dc;
 194         unsigned long timeout;
 195         u32 mask, value;
 196
 197         mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index;
 198         tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
 199
 200         timeout = jiffies + msecs_to_jiffies(1000);
 201
 202         while (time_before(jiffies, timeout)) {
 203                 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
 204                 if ((value & mask) == 0)
 205                         break;
 206
 207                 usleep_range(100, 400);
 208         }
 209 }
 210
 211 static unsigned int
 212 tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc)
 213 {
 214         unsigned int offset =
 215                 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
 216
 217         return tegra_dc_readl(dc, offset) & OWNER_MASK;
 218 }
 219
 220 static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc,
 221                                        struct tegra_plane *plane)
 222 {
 223         struct device *dev = dc->dev;
 224
 225         if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) {
 226                 if (plane->dc == dc)
 227                         return true;
 228
 229                 dev_WARN(dev, "head %u owns window %u but is not attached\n",
 230                          dc->pipe, plane->index);
 231         }
 232
 233         return false;
 234 }
 235
 236 static int tegra_shared_plane_set_owner(struct tegra_plane *plane,
 237                                         struct tegra_dc *new)
 238 {
 239         unsigned int offset =
 240                 tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
 241         struct tegra_dc *old = plane->dc, *dc = new ? new : old;
 242         struct device *dev = new ? new->dev : old->dev;
 243         unsigned int owner, index = plane->index;
 244         u32 value;
 245
 246         value = tegra_dc_readl(dc, offset);
 247         owner = value & OWNER_MASK;
 248
 249         if (new && (owner != OWNER_MASK && owner != new->pipe)) {
 250                 dev_WARN(dev, "window %u owned by head %u\n", index, owner);
 251                 return -EBUSY;
 252         }
 253
 254         /*
 255          * This seems to happen whenever the head has been disabled with one
 256          * or more windows being active. This is harmless because we'll just
 257          * reassign the window to the new head anyway.
 258          */
 259         if (old && owner == OWNER_MASK)
 260                 dev_dbg(dev, "window %u not owned by head %u but %u\n", index,
 261                         old->pipe, owner);
 262
 263         value &= ~OWNER_MASK;
 264
 265         if (new)
 266                 value |= OWNER(new->pipe);
 267         else
 268                 value |= OWNER_MASK;
 269
 270         tegra_dc_writel(dc, value, offset);
 271
 272         plane->dc = new;
 273
 274         return 0;
 275 }
 276
 277 static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
 278                                          struct tegra_plane *plane)
 279 {
 280         u32 value;
 281         int err;
 282
 283         if (!tegra_dc_owns_shared_plane(dc, plane)) {
 284                 err = tegra_shared_plane_set_owner(plane, dc);
 285                 if (err < 0)
 286                         return;
 287         }
 288
 289         value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
 290         value |= MODE_FOUR_LINES;
 291         tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
 292
 293         value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
 294         value = SLOTS(1);
 295         tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
 296
 297         /* disable watermark */
 298         value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
 299         value &= ~LATENCY_CTL_MODE_ENABLE;
 300         tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
 301
 302         value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
 303         value |= WATERMARK_MASK;
 304         tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
 305
 306         /* pipe meter */
 307         value = tegra_plane_readl(plane, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
 308         value = PIPE_METER_INT(0) | PIPE_METER_FRAC(0);
 309         tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
 310
 311         /* mempool entries */
 312         value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
 313         value = MEMPOOL_ENTRIES(0x331);
 314         tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
 315
 316         value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_THREAD_GROUP);
 317         value &= ~THREAD_NUM_MASK;
 318         value |= THREAD_NUM(plane->base.index);
 319         value |= THREAD_GROUP_ENABLE;
 320         tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP);
 321
 322         tegra_shared_plane_update(plane);
 323         tegra_shared_plane_activate(plane);
 324 }
 325
 326 static void tegra_dc_remove_shared_plane(struct tegra_dc *dc,
 327                                          struct tegra_plane *plane)
 328 {
 329         tegra_shared_plane_set_owner(plane, NULL);
 330 }
 331
 332 static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
 333                                            struct drm_plane_state *state)
 334 {
 335         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 336         struct tegra_shared_plane *tegra = to_tegra_shared_plane(plane);
 337         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 338         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 339         int err;
 340
 341         /* no need for further checks if the plane is being disabled */
 342         if (!state->crtc || !state->fb)
 343                 return 0;
 344
 345         err = tegra_plane_format(state->fb->format->format,
 346                                  &plane_state->format,
 347                                  &plane_state->swap);
 348         if (err < 0)
 349                 return err;
 350
 351         err = tegra_fb_get_tiling(state->fb, tiling);
 352         if (err < 0)
 353                 return err;
 354
 355         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 356             !dc->soc->supports_block_linear) {
 357                 DRM_ERROR("hardware doesn't support block linear mode\n");
 358                 return -EINVAL;
 359         }
 360
 361         /*
 362          * Tegra doesn't support different strides for U and V planes so we
 363          * error out if the user tries to display a framebuffer with such a
 364          * configuration.
 365          */
 366         if (state->fb->format->num_planes > 2) {
 367                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 368                         DRM_ERROR("unsupported UV-plane configuration\n");
 369                         return -EINVAL;
 370                 }
 371         }
 372
 373         /* XXX scaling is not yet supported, add a check here */
 374
 375         err = tegra_plane_state_add(&tegra->base, state);
 376         if (err < 0)
 377                 return err;
 378
 379         return 0;
 380 }
 381
 382 static void tegra_shared_plane_atomic_disable(struct drm_plane *plane,
 383                                               struct drm_plane_state *old_state)
 384 {
 385         struct tegra_plane *p = to_tegra_plane(plane);
 386         struct tegra_dc *dc;
 387         u32 value;
 388
 389         /* rien ne va plus */
 390         if (!old_state || !old_state->crtc)
 391                 return;
 392
 393         dc = to_tegra_dc(old_state->crtc);
 394
 395         /*
 396          * XXX Legacy helpers seem to sometimes call ->atomic_disable() even
 397          * on planes that are already disabled. Make sure we fallback to the
 398          * head for this particular state instead of crashing.
 399          */
 400         if (WARN_ON(p->dc == NULL))
 401                 p->dc = dc;
 402
 403         pm_runtime_get_sync(dc->dev);
 404
 405         value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
 406         value &= ~WIN_ENABLE;
 407         tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 408
 409         tegra_dc_remove_shared_plane(dc, p);
 410
 411         pm_runtime_put(dc->dev);
 412 }
 413
 414 static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
 415                                              struct drm_plane_state *old_state)
 416 {
 417         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 418         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 419         unsigned int zpos = plane->state->normalized_zpos;
 420         struct drm_framebuffer *fb = plane->state->fb;
 421         struct tegra_plane *p = to_tegra_plane(plane);
 422         struct tegra_bo *bo;
 423         dma_addr_t base;
 424         u32 value;
 425
 426         /* rien ne va plus */
 427         if (!plane->state->crtc || !plane->state->fb)
 428                 return;
 429
 430         if (!plane->state->visible) {
 431                 tegra_shared_plane_atomic_disable(plane, old_state);
 432                 return;
 433         }
 434
 435         pm_runtime_get_sync(dc->dev);
 436
 437         tegra_dc_assign_shared_plane(dc, p);
 438
 439         tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL);
 440
 441         /* blending */
 442         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 443                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 444                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 445         tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
 446
 447         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 448                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 449                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 450         tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
 451
 452         value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
 453         tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
 454
 455         /* bypass scaling */
 456         value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
 457         tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
 458
 459         value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
 460         tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
 461
 462         /* disable compression */
 463         tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
 464
 465         bo = tegra_fb_get_plane(fb, 0);
 466         base = bo->paddr;
 467
 468         tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH);
 469         tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
 470
 471         value = V_POSITION(plane->state->crtc_y) |
 472                 H_POSITION(plane->state->crtc_x);
 473         tegra_plane_writel(p, value, DC_WIN_POSITION);
 474
 475         value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
 476         tegra_plane_writel(p, value, DC_WIN_SIZE);
 477
 478         value = WIN_ENABLE | COLOR_EXPAND;
 479         tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 480
 481         value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
 482         tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE);
 483
 484         tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI);
 485         tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR);
 486
 487         value = PITCH(fb->pitches[0]);
 488         tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
 489
 490         value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL;
 491         tegra_plane_writel(p, value, DC_WIN_SET_PARAMS);
 492
 493         value = OFFSET_X(plane->state->src_y >> 16) |
 494                 OFFSET_Y(plane->state->src_x >> 16);
 495         tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT);
 496
 497         if (dc->soc->supports_block_linear) {
 498                 unsigned long height = state->tiling.value;
 499
 500                 /* XXX */
 501                 switch (state->tiling.mode) {
 502                 case TEGRA_BO_TILING_MODE_PITCH:
 503                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) |
 504                                 DC_WINBUF_SURFACE_KIND_PITCH;
 505                         break;
 506
 507                 /* XXX not supported on Tegra186 and later */
 508                 case TEGRA_BO_TILING_MODE_TILED:
 509                         value = DC_WINBUF_SURFACE_KIND_TILED;
 510                         break;
 511
 512                 case TEGRA_BO_TILING_MODE_BLOCK:
 513                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 514                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 515                         break;
 516                 }
 517
 518                 tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND);
 519         }
 520
 521         /* disable gamut CSC */
 522         value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL);
 523         value &= ~CONTROL_CSC_ENABLE;
 524         tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL);
 525
 526         pm_runtime_put(dc->dev);
 527 }
 528
 529 static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = {
 530         .atomic_check = tegra_shared_plane_atomic_check,
 531         .atomic_update = tegra_shared_plane_atomic_update,
 532         .atomic_disable = tegra_shared_plane_atomic_disable,
 533 };
 534
 535 struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
 536                                             struct tegra_dc *dc,
 537                                             unsigned int wgrp,
 538                                             unsigned int index)
 539 {
 540         enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
 541         struct tegra_drm *tegra = drm->dev_private;
 542         struct tegra_display_hub *hub = tegra->hub;
 543         /* planes can be assigned to arbitrary CRTCs */
 544         unsigned int possible_crtcs = 0x7;
 545         struct tegra_shared_plane *plane;
 546         unsigned int num_formats;
 547         const u64 *modifiers;
 548         struct drm_plane *p;
 549         const u32 *formats;
 550         int err;
 551
 552         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 553         if (!plane)
 554                 return ERR_PTR(-ENOMEM);
 555
 556         plane->base.offset = 0x0a00 + 0x0300 * index;
 557         plane->base.index = index;
 558
 559         plane->wgrp = &hub->wgrps[wgrp];
 560         plane->wgrp->parent = dc->dev;
 561
 562         p = &plane->base.base;
 563
 564         num_formats = ARRAY_SIZE(tegra_shared_plane_formats);
 565         formats = tegra_shared_plane_formats;
 566         modifiers = tegra_shared_plane_modifiers;
 567
 568         err = drm_universal_plane_init(drm, p, possible_crtcs,
 569                                        &tegra_plane_funcs, formats,
 570                                        num_formats, modifiers, type, NULL);
 571         if (err < 0) {
 572                 kfree(plane);
 573                 return ERR_PTR(err);
 574         }
 575
 576         drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs);
 577         drm_plane_create_zpos_property(p, 0, 0, 255);
 578
 579         return p;
 580 }
 581
 582 static struct drm_private_state *
 583 tegra_display_hub_duplicate_state(struct drm_private_obj *obj)
 584 {
 585         struct tegra_display_hub_state *state;
 586
 587         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 588         if (!state)
 589                 return NULL;
 590
 591         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 592
 593         return &state->base;
 594 }
 595
 596 static void tegra_display_hub_destroy_state(struct drm_private_obj *obj,
 597                                             struct drm_private_state *state)
 598 {
 599         struct tegra_display_hub_state *hub_state =
 600                 to_tegra_display_hub_state(state);
 601
 602         kfree(hub_state);
 603 }
 604
 605 static const struct drm_private_state_funcs tegra_display_hub_state_funcs = {
 606         .atomic_duplicate_state = tegra_display_hub_duplicate_state,
 607         .atomic_destroy_state = tegra_display_hub_destroy_state,
 608 };
 609
 610 static struct tegra_display_hub_state *
 611 tegra_display_hub_get_state(struct tegra_display_hub *hub,
 612                             struct drm_atomic_state *state)
 613 {
 614         struct drm_device *drm = dev_get_drvdata(hub->client.parent);
 615         struct drm_private_state *priv;
 616
 617         WARN_ON(!drm_modeset_is_locked(&drm->mode_config.connection_mutex));
 618
 619         priv = drm_atomic_get_private_obj_state(state, &hub->base);
 620         if (IS_ERR(priv))
 621                 return ERR_CAST(priv);
 622
 623         return to_tegra_display_hub_state(priv);
 624 }
 625
 626 int tegra_display_hub_atomic_check(struct drm_device *drm,
 627                                    struct drm_atomic_state *state)
 628 {
 629         struct tegra_drm *tegra = drm->dev_private;
 630         struct tegra_display_hub_state *hub_state;
 631         struct drm_crtc_state *old, *new;
 632         struct drm_crtc *crtc;
 633         unsigned int i;
 634
 635         if (!tegra->hub)
 636                 return 0;
 637
 638         hub_state = tegra_display_hub_get_state(tegra->hub, state);
 639         if (IS_ERR(hub_state))
 640                 return PTR_ERR(hub_state);
 641
 642         /*
 643          * The display hub display clock needs to be fed by the display clock
 644          * with the highest frequency to ensure proper functioning of all the
 645          * displays.
 646          *
 647          * Note that this isn't used before Tegra186, but it doesn't hurt and
 648          * conditionalizing it would make the code less clean.
 649          */
 650         for_each_oldnew_crtc_in_state(state, crtc, old, new, i) {
 651                 struct tegra_dc_state *dc = to_dc_state(new);
 652
 653                 if (new->active) {
 654                         if (!hub_state->clk || dc->pclk > hub_state->rate) {
 655                                 hub_state->dc = to_tegra_dc(dc->base.crtc);
 656                                 hub_state->clk = hub_state->dc->clk;
 657                                 hub_state->rate = dc->pclk;
 658                         }
 659                 }
 660         }
 661
 662         return 0;
 663 }
 664
 665 static void tegra_display_hub_update(struct tegra_dc *dc)
 666 {
 667         u32 value;
 668
 669         pm_runtime_get_sync(dc->dev);
 670
 671         value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);
 672         value &= ~LATENCY_EVENT;
 673         tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
 674
 675         value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
 676         value = CURS_SLOTS(1) | WGRP_SLOTS(1);
 677         tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
 678
 679         tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
 680         tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
 681         tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
 682         tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
 683
 684         pm_runtime_put(dc->dev);
 685 }
 686
 687 void tegra_display_hub_atomic_commit(struct drm_device *drm,
 688                                      struct drm_atomic_state *state)
 689 {
 690         struct tegra_drm *tegra = drm->dev_private;
 691         struct tegra_display_hub *hub = tegra->hub;
 692         struct tegra_display_hub_state *hub_state;
 693         struct device *dev = hub->client.dev;
 694         int err;
 695
 696         hub_state = to_tegra_display_hub_state(hub->base.state);
 697
 698         if (hub_state->clk) {
 699                 err = clk_set_rate(hub_state->clk, hub_state->rate);
 700                 if (err < 0)
 701                         dev_err(dev, "failed to set rate of %pC to %lu Hz\n",
 702                                 hub_state->clk, hub_state->rate);
 703
 704                 err = clk_set_parent(hub->clk_disp, hub_state->clk);
 705                 if (err < 0)
 706                         dev_err(dev, "failed to set parent of %pC to %pC: %d\n",
 707                                 hub->clk_disp, hub_state->clk, err);
 708         }
 709
 710         if (hub_state->dc)
 711                 tegra_display_hub_update(hub_state->dc);
 712 }
 713
 714 static int tegra_display_hub_init(struct host1x_client *client)
 715 {
 716         struct tegra_display_hub *hub = to_tegra_display_hub(client);
 717         struct drm_device *drm = dev_get_drvdata(client->parent);
 718         struct tegra_drm *tegra = drm->dev_private;
 719         struct tegra_display_hub_state *state;
 720
 721         state = kzalloc(sizeof(*state), GFP_KERNEL);
 722         if (!state)
 723                 return -ENOMEM;
 724
 725         drm_atomic_private_obj_init(&hub->base, &state->base,
 726                                     &tegra_display_hub_state_funcs);
 727
 728         tegra->hub = hub;
 729
 730         return 0;
 731 }
 732
 733 static int tegra_display_hub_exit(struct host1x_client *client)
 734 {
 735         struct drm_device *drm = dev_get_drvdata(client->parent);
 736         struct tegra_drm *tegra = drm->dev_private;
 737
 738         drm_atomic_private_obj_fini(&tegra->hub->base);
 739         tegra->hub = NULL;
 740
 741         return 0;
 742 }
 743
 744 static const struct host1x_client_ops tegra_display_hub_ops = {
 745         .init = tegra_display_hub_init,
 746         .exit = tegra_display_hub_exit,
 747 };
 748
 749 static int tegra_display_hub_probe(struct platform_device *pdev)
 750 {
 751         struct tegra_display_hub *hub;
 752         unsigned int i;
 753         int err;
 754
 755         hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL);
 756         if (!hub)
 757                 return -ENOMEM;
 758
 759         hub->soc = of_device_get_match_data(&pdev->dev);
 760
 761         hub->clk_disp = devm_clk_get(&pdev->dev, "disp");
 762         if (IS_ERR(hub->clk_disp)) {
 763                 err = PTR_ERR(hub->clk_disp);
 764                 return err;
 765         }
 766
 767         hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc");
 768         if (IS_ERR(hub->clk_dsc)) {
 769                 err = PTR_ERR(hub->clk_dsc);
 770                 return err;
 771         }
 772
 773         hub->clk_hub = devm_clk_get(&pdev->dev, "hub");
 774         if (IS_ERR(hub->clk_hub)) {
 775                 err = PTR_ERR(hub->clk_hub);
 776                 return err;
 777         }
 778
 779         hub->rst = devm_reset_control_get(&pdev->dev, "misc");
 780         if (IS_ERR(hub->rst)) {
 781                 err = PTR_ERR(hub->rst);
 782                 return err;
 783         }
 784
 785         hub->wgrps = devm_kcalloc(&pdev->dev, hub->soc->num_wgrps,
 786                                   sizeof(*hub->wgrps), GFP_KERNEL);
 787         if (!hub->wgrps)
 788                 return -ENOMEM;
 789
 790         for (i = 0; i < hub->soc->num_wgrps; i++) {
 791                 struct tegra_windowgroup *wgrp = &hub->wgrps[i];
 792                 char id[8];
 793
 794                 snprintf(id, sizeof(id), "wgrp%u", i);
 795                 mutex_init(&wgrp->lock);
 796                 wgrp->usecount = 0;
 797                 wgrp->index = i;
 798
 799                 wgrp->rst = devm_reset_control_get(&pdev->dev, id);
 800                 if (IS_ERR(wgrp->rst))
 801                         return PTR_ERR(wgrp->rst);
 802
 803                 err = reset_control_assert(wgrp->rst);
 804                 if (err < 0)
 805                         return err;
 806         }
 807
 808         /* XXX: enable clock across reset? */
 809         err = reset_control_assert(hub->rst);
 810         if (err < 0)
 811                 return err;
 812
 813         platform_set_drvdata(pdev, hub);
 814         pm_runtime_enable(&pdev->dev);
 815
 816         INIT_LIST_HEAD(&hub->client.list);
 817         hub->client.ops = &tegra_display_hub_ops;
 818         hub->client.dev = &pdev->dev;
 819
 820         err = host1x_client_register(&hub->client);
 821         if (err < 0)
 822                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
 823                         err);
 824
 825         return err;
 826 }
 827
 828 static int tegra_display_hub_remove(struct platform_device *pdev)
 829 {
 830         struct tegra_display_hub *hub = platform_get_drvdata(pdev);
 831         int err;
 832
 833         err = host1x_client_unregister(&hub->client);
 834         if (err < 0) {
 835                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
 836                         err);
 837         }
 838
 839         pm_runtime_disable(&pdev->dev);
 840
 841         return err;
 842 }
 843
 844 static int __maybe_unused tegra_display_hub_suspend(struct device *dev)
 845 {
 846         struct tegra_display_hub *hub = dev_get_drvdata(dev);
 847         int err;
 848
 849         err = reset_control_assert(hub->rst);
 850         if (err < 0)
 851                 return err;
 852
 853         clk_disable_unprepare(hub->clk_hub);
 854         clk_disable_unprepare(hub->clk_dsc);
 855         clk_disable_unprepare(hub->clk_disp);
 856
 857         return 0;
 858 }
 859
 860 static int __maybe_unused tegra_display_hub_resume(struct device *dev)
 861 {
 862         struct tegra_display_hub *hub = dev_get_drvdata(dev);
 863         int err;
 864
 865         err = clk_prepare_enable(hub->clk_disp);
 866         if (err < 0)
 867                 return err;
 868
 869         err = clk_prepare_enable(hub->clk_dsc);
 870         if (err < 0)
 871                 goto disable_disp;
 872
 873         err = clk_prepare_enable(hub->clk_hub);
 874         if (err < 0)
 875                 goto disable_dsc;
 876
 877         err = reset_control_deassert(hub->rst);
 878         if (err < 0)
 879                 goto disable_hub;
 880
 881         return 0;
 882
 883 disable_hub:
 884         clk_disable_unprepare(hub->clk_hub);
 885 disable_dsc:
 886         clk_disable_unprepare(hub->clk_dsc);
 887 disable_disp:
 888         clk_disable_unprepare(hub->clk_disp);
 889         return err;
 890 }
 891
 892 static const struct dev_pm_ops tegra_display_hub_pm_ops = {
 893         SET_RUNTIME_PM_OPS(tegra_display_hub_suspend,
 894                            tegra_display_hub_resume, NULL)
 895 };
 896
 897 static const struct tegra_display_hub_soc tegra186_display_hub = {
 898         .num_wgrps = 6,
 899 };
 900
 901 static const struct of_device_id tegra_display_hub_of_match[] = {
 902         {
 903                 .compatible = "nvidia,tegra186-display",
 904                 .data = &tegra186_display_hub
 905         }, {
 906                 /* sentinel */
 907         }
 908 };
 909 MODULE_DEVICE_TABLE(of, tegra_display_hub_of_match);
 910
 911 struct platform_driver tegra_display_hub_driver = {
 912         .driver = {
 913                 .name = "tegra-display-hub",
 914                 .of_match_table = tegra_display_hub_of_match,
 915                 .pm = &tegra_display_hub_pm_ops,
 916         },
 917         .probe = tegra_display_hub_probe,
 918         .remove = tegra_display_hub_remove,
 919 };